CN101026107A - Wafer level package bump manufacturing method - Google Patents
Wafer level package bump manufacturing method Download PDFInfo
- Publication number
- CN101026107A CN101026107A CNA2006100550280A CN200610055028A CN101026107A CN 101026107 A CN101026107 A CN 101026107A CN A2006100550280 A CNA2006100550280 A CN A2006100550280A CN 200610055028 A CN200610055028 A CN 200610055028A CN 101026107 A CN101026107 A CN 101026107A
- Authority
- CN
- China
- Prior art keywords
- wafer
- conductive layer
- those
- layer
- level packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
This invention provides a manufacturing method for salient blocks of wafer package including the following steps: providing a wafer with multiple solder pads and a protection layer exposing the pads, in which, the protection layer among the pads can contain cut channels for segmenting the chip after the package, forming a conduction layer on the wafer connected with the pads electrically and filled into the cut channels, forming a photoresist layer on the conduction layer to be patternized to form an opening exposing the conduction layer above the pads and forming an opening not exposing the conduction layer in the regions out of the pads and forming salient blocks in the opening above the pads to connect to the conduction layer.
Description
[technical field]
The present invention is about a kind of chip encapsulating manufacturing procedure, particularly about a kind of bump manufacturing method of wafer-level packaging.
[background technology]
In today of advanced IT application, the market prospects of integrated circuit are more and more wide, and are corresponding, integrated circuit (IC) design, chip manufacturing and all fast developments of integrated circuit encapsulation industry.In China, the integrated circuit encapsulation had become the important point of economic increase of IC industry already.In order to satisfy many-sided demands such as integrated circuit package high speed processingization, multifunction, integrated, miniaturization and and low priceization, the integrated circuit encapsulation technology also need be and then towards microminiaturized, densification development.Integrated circuit encapsulation technology at present commonly used include the encapsulation of sphere grid array formula (Ball Grid Array, BGA), chip size packages (Chip-Scale Package, CSP) and multi-chip module (Multi-Chip Module, MCM).In the integrated circuit encapsulation technology, the integrated circuit packaging density refers to how many degree of stitch that unit are contains (pin) number, for the high density integrated circuit encapsulation, the length that shortens distribution helps to improve the signal transmission speed, so the application of projection becomes the main flow of high-density packages gradually.
Please refer to shown in Figure 1A to 1H, Figure 1A to 1H has shown the manufacture process of projection in the traditional die encapsulation procedure.At first, provide a wafer 100, dispose a plurality of weld pads (pad) 101a on this wafer, 101b and in order to the protective layer 103 of protection wafer 100 is cut apart chip and may contain between weld pad 101a and the weld pad 101b after Cutting Road 105 confession Chip Packaging are finished.Then, and formation ball substrate layer on wafer 100 (Under Bump Metallurgy, UBM) 107, with joint interface as follow-up formed projection (bump) and weld pad.After forming ball substrate layer 107, form photoresistance 109 on wafer 100, this photoresistance 109 for example is the dry film photoresistance, photoresistance 109 with weld pad 101a, the position of 101b correspondence forms a plurality of opening 111a, 111b is to provide the formation position of follow-up projection.Then at opening 111a, 111b electroplates at the place scolder, removal photoresistance 109 and unnecessary ball substrate layer 107 and reflow steps such as (reflow) just can form a plurality of projection 113a, 113b afterwards on base material.
Yet, it should be noted that at above-mentioned plating scolder to the step of opening, from the stress of scolder both sides dry film photoresist layer extruding regular meeting is caused wafer deflection, even can cause wafer that breakage is arranged.Therefore just can reduce the reliability and the yield thereof of chip encapsulating manufacturing procedure greatly.
[summary of the invention]
In view of above problem, the present invention mainly provides a kind of bump manufacturing method of wafer-level packaging, by forming the not opening of standard-sized sheet with the photoresist layer of exterior domain at weld pad, alleviate the stress that both sides produce because of scolder, thereby improve chip encapsulating manufacturing procedure reliability, increase yield.
One of for achieving the above object, the present invention adopts following technical scheme: the bump manufacturing method that the invention provides a kind of wafer-level packaging.One wafer at first is provided, forms some Cutting Roads and protective layer on wafer, wherein defined several zones between the Cutting Road, each zone comprises several weld pads, and this protective layer be disposed at each should the zone on, expose those weld pads; Form conductive layer then on wafer, this conductive layer and weld pad electrically connect and insert Cutting Road; Then on conductive layer, form photoresist layer; Moreover the patterning photoresist layer, form several in the weld pad top and expose the opening of conductive layer, and the zone beyond weld pad forms the opening that several do not expose conductive layer; Last opening part above weld pad forms several projections with connecting conductive layer.
On be set forth in the step that zone beyond the weld pad forms several openings that do not expose conductive layer and can utilize laser, can heat the mode that cutter cutting, control exposure or double exposure develop and carry out.
Compared with prior art, the invention has the advantages that: form in the step of opening at photoresist layer, zone beyond weld pad forms the not opening of standard-sized sheet, make follow-up both-side opening fill the stress that is produced when scolder forms solder projection and had the space that alleviates, so can avoid the stressed deflection of wafer even therefore breakage can reach reliability that improves chip encapsulating manufacturing procedure and then the effect that improves yield.
Below in execution mode, be described in detail detailed features of the present invention and advantage, its content is enough to make any those skilled in the art that have the knack of related art techniques to understand technology contents of the present invention and implements according to this, and according to the disclosed content of this specification, claim and graphic, any those of ordinary skills all can understand purpose and the advantage that the present invention is correlated with easily.
[description of drawings]
Figure 1A to 1H is the manufacturing process schematic diagram of projection in the traditional die encapsulation procedure; And
Fig. 2 A to 2H is the manufacturing process schematic diagram of a preferred embodiment of bump manufacturing method in the wafer-level packaging of the present invention, and Fig. 2 A to 2H illustrates the product of different phase in the manufacture process respectively.
[embodiment]
For making purpose of the present invention, structure, feature and function there are further understanding, describe in detail below in conjunction with specific embodiment.
Fig. 2 A to 2H is the manufacturing process schematic diagram of bump manufacturing method one preferred embodiment in the wafer-level packaging of the present invention.
At first please refer to shown in Fig. 2 A, a wafer 200 is provided, dispose a plurality of weld pad 201a on the wafer 200,201b and protective layer 203.Wherein protective layer 203 is disposed at the surface of wafer 200, in order to protect wafer 200 surfaces and to expose described a plurality of weld pad 201a, 201b to the open air.Be formed with Cutting Road 205 on the protective layer 203 between weld pad 201a and the weld pad 201b in addition, use when cutting apart chip for follow-up.
Above-mentioned wafer 200 can be printed circuit board (PCB) or the available loading plate of other encapsulation.
The material of above-mentioned protective layer 203 can comprise nitride (nitride), silicon nitride (siliconnitride), phosphorosilicate glass (phosphosilicate glass, PSG) or silica (siliconoxide).
Please refer to then shown in Fig. 2 B, at the weld pad 201a of wafer 200, last formation one conductive layer 207 of 201b, this conductive layer 207 is inserted in the Cutting Road 205 simultaneously.This conductive layer 207 can be formed by plating mode, its material can comprise titanium, titanium-tungsten, aluminium, nickel vanadium, nickel, copper or chromium for instance, or be the three-decker of titanium/nickel-vanadium alloy/copper or aluminium/nickel-vanadium alloy/copper, or be the two-layer structure of titanium/copper alloy, also can be the four-layer structure of aluminium/titanium/nickel-vanadium alloy/copper.
Please refer to shown in Fig. 2 C again, form a photoresist layer 209 at the upper surface of wafer 200, it covers conductive layer 207.This photoresist layer 209 for example can be a dry film photoresist layer.
Then please refer to shown in Fig. 2 D, this photoresist layer 209 of patterning is at corresponding weld pad 201a, the 201b place forms the opening 211a that exposes below conductive layer 207,211b, and at weld pad 201a, the zone beyond the 201b forms the opening 211c that at least one does not expose this conductive layer.In the explanation and diagram of this preferred embodiment, be example only, but this is not in order to restriction the present invention with opening 211c corresponding to Cutting Road 205 places.
The generation type of opening 211c can use laser or heatable cutter to be cut into for instance, or utilize the mode of controlling exposure, make the degree of depth of opening 211c more shallow, the mode that also can use re-expose to develop in addition, in first time during exposure imaging, at corresponding weld pad 201a, zone beyond 201b place and the weld pad all forms the opening that does not expose the below conductive layer, and in second time during exposure imaging, at corresponding weld pad 201a, the opening at 201b place makes its standard-sized sheet expose the conductive layer of below again.
Continuation is filled in weld pad 201a with reference to shown in Fig. 2 E with scolder, the opening 211a of 201b top, among the 211b to form solder projection 213a, 213b.The method of filling scolder can be electroplating process for instance.This scolder for example comprises tin-lead metal.
Refer again to shown in Fig. 2 F to 2H, remove photoresist layer 209, and with solder projection 213a, 213b removes unnecessary conductive layer as shielding, carry out back welding process at last so that solder projection 213a, 213b forms the ball sample and also is fixed on the conductive layer 207.
In sum, because of forming in the step of opening at photoresist layer, zone beyond weld pad forms the not opening of standard-sized sheet, make follow-up both-side opening fill the stress that is produced when scolder forms solder projection and had the space that alleviates, so can avoid the stressed deflection of wafer even therefore breakage can reach reliability that improves chip encapsulating manufacturing procedure and then the effect that improves yield.
Though the present invention discloses as above with aforesaid embodiment, it is not in order to limit the present invention.Without departing from the spirit and scope of the present invention, those of ordinary skill in the art can carry out various changes to the present invention.If modification of the present invention is belonged within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes interior.
Claims (10)
1. the bump manufacturing method of a wafer-level packaging, comprise: a wafer is provided, on this wafer, form some Cutting Roads and a protective layer, between those Cutting Roads, define several zones, each zone comprises some weld pads, and this protective layer is disposed on each zone, exposes described several weld pads; Form a conductive layer on wafer, this conductive layer and those weld pads electrically connect and insert those Cutting Roads; And on conductive layer, form a photoresist layer; It is characterized in that: this method also comprises after forming photoresist layer:
This photoresist layer of patterning forms several in those weld pad tops and expose the opening of conductive layer, and the zone beyond weld pad forms at least one opening that does not expose conductive layer; And opening part forms several projections with connecting conductive layer above described some weld pads.
2. the bump manufacturing method of wafer-level packaging as claimed in claim 1, it is characterized in that: the step of described patterning photoresist layer comprises:
Utilize the photoresist layer of those weld pad tops of one first exposure exposure imaging; And
Utilize the photoresist layer of one second those weld pads of exposure exposure imaging top, zone in addition, wherein this second exposure is less than this first exposure.
3. the bump manufacturing method of wafer-level packaging as claimed in claim 1 is characterized in that: the step of described patterning light sun layer comprises:
Utilize one first exposure imaging program to form the opening that several do not expose this conductive layer; And
Utilize one second exposure imaging program to form several and expose the opening of this conductive layer in those weld pad tops.
4. the bump manufacturing method of wafer-level packaging as claimed in claim 1 is characterized in that: the weld pad that is set forth in adopt laser or cutters cutting with steps that the exterior domain top forms several openings that do not expose conductive layer.
5. the bump manufacturing method of wafer-level packaging as claimed in claim 1, it is characterized in that: the step of described formation projection comprises:
Fill scolder in those weld pads top openings with connecting conductive layer; And
Remove photoresist layer so that those scolders form those projections.
6. the bump manufacturing method of wafer-level packaging as claimed in claim 5 is characterized in that: also comprise after the step of described formation projection:
Remove the conductive layer that is not hidden by those projections; And
Those projections of reflow.
7. the bump manufacturing method of wafer-level packaging as claimed in claim 5 is characterized in that: the step employing electro-plating method of described filling scolder.
8. the bump manufacturing method of wafer-level packaging as claimed in claim 1, it is characterized in that: in the step of described formation protective layer, the material of this protective layer comprises nitride.
9. the bump manufacturing method of wafer-level packaging as claimed in claim 1, it is characterized in that: in the step of described formation protective layer, the material of this protective layer comprises silica.
10. the bump manufacturing method of wafer-level packaging as claimed in claim 1, it is characterized in that: in the step of described formation conductive layer, the material of this conductive layer is selected from one of them in the group that is made up of titanium, titanium-tungsten, aluminium, nickel vanadium, nickel, copper and chromium and those combination.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100550280A CN101026107A (en) | 2006-02-24 | 2006-02-24 | Wafer level package bump manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100550280A CN101026107A (en) | 2006-02-24 | 2006-02-24 | Wafer level package bump manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101026107A true CN101026107A (en) | 2007-08-29 |
Family
ID=38744233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006100550280A Pending CN101026107A (en) | 2006-02-24 | 2006-02-24 | Wafer level package bump manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101026107A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102122624A (en) * | 2011-02-01 | 2011-07-13 | 南通富士通微电子股份有限公司 | Wafer packaging method |
| CN102479750A (en) * | 2010-11-29 | 2012-05-30 | 中国科学院微电子研究所 | Chemical mechanical planarization method |
| CN103137567A (en) * | 2011-11-30 | 2013-06-05 | 和舰科技(苏州)有限公司 | Wafer structure for reducing damage of wafer cutting stress and layout design method |
| CN103922267A (en) * | 2013-01-10 | 2014-07-16 | 深迪半导体(上海)有限公司 | Inertial sensor production and wafer level package process based on MEMS (micro-electromechanical system) |
| CN108962764A (en) * | 2017-05-22 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | Forming method, semiconductor chip, packaging method and the structure of semiconductor structure |
-
2006
- 2006-02-24 CN CNA2006100550280A patent/CN101026107A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479750A (en) * | 2010-11-29 | 2012-05-30 | 中国科学院微电子研究所 | Chemical mechanical planarization method |
| CN102479750B (en) * | 2010-11-29 | 2015-12-16 | 中国科学院微电子研究所 | Chemical mechanical planarization method |
| CN102122624A (en) * | 2011-02-01 | 2011-07-13 | 南通富士通微电子股份有限公司 | Wafer packaging method |
| CN102122624B (en) * | 2011-02-01 | 2013-02-13 | 南通富士通微电子股份有限公司 | Wafer packaging method |
| CN103137567A (en) * | 2011-11-30 | 2013-06-05 | 和舰科技(苏州)有限公司 | Wafer structure for reducing damage of wafer cutting stress and layout design method |
| CN103922267A (en) * | 2013-01-10 | 2014-07-16 | 深迪半导体(上海)有限公司 | Inertial sensor production and wafer level package process based on MEMS (micro-electromechanical system) |
| CN108962764A (en) * | 2017-05-22 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | Forming method, semiconductor chip, packaging method and the structure of semiconductor structure |
| US11335648B2 (en) | 2017-05-22 | 2022-05-17 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor chip fabrication and packaging methods thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6740980B2 (en) | Semiconductor device | |
| DE69627565T2 (en) | Packaging of multi-chip modules without wire connection | |
| US6784087B2 (en) | Method of fabricating cylindrical bonding structure | |
| US5898223A (en) | Chip-on-chip IC packages | |
| CN101859752B (en) | Stacking package structure with chip embedded inside and grain having through silicon via and method of manufacturing the same | |
| US20060035409A1 (en) | Methods and apparatuses for providing stacked-die devices | |
| CN102376687A (en) | Semiconductor component packaging structure and manufacturing method thereof | |
| CN101197356A (en) | Multi-chip package structure and its forming method | |
| US20030218249A1 (en) | High-density integrated circuit package and method for the same | |
| CN101800209A (en) | Flip chip mounted semiconductor device package having a dimpled leadframe | |
| CN101282622B (en) | Circuit board and method for manufacturing the same | |
| CN102088013A (en) | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same | |
| CN101026107A (en) | Wafer level package bump manufacturing method | |
| CN101859733B (en) | Semiconductor packaging structure, support plate for same, and manufacture method thereof | |
| CN105244339B (en) | The method for packing and encapsulating structure of image sensing chip | |
| CN100481420C (en) | Stack type chip packaging structure, chip packaging body and manufacturing method thereof | |
| CN101504919A (en) | Encapsulation structure and method for semi-conductor | |
| US20090014896A1 (en) | Flip-chip package structure, and the substrate and the chip thereof | |
| CN101510515A (en) | Circuit board, manufacturing method thereof and chip packaging structure | |
| CN108231729A (en) | A kind of package substrate, chip packing-body and chip stack package method | |
| CN101320719A (en) | Line carrier plate and preparation thereof | |
| CN212461680U (en) | Three-dimensional package structure that piles up of wafer level chip fan-out | |
| JP2002012997A (en) | Method for plating columnar protrusion in integrated circuit substrate | |
| CN100490103C (en) | Making method for base plate welding cover layer and its structure | |
| CN100367464C (en) | Method for manufacturing metal coupling |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20070829 |