CN101320719A - Line carrier plate and preparation thereof - Google Patents
Line carrier plate and preparation thereof Download PDFInfo
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- CN101320719A CN101320719A CNA2008101356696A CN200810135669A CN101320719A CN 101320719 A CN101320719 A CN 101320719A CN A2008101356696 A CNA2008101356696 A CN A2008101356696A CN 200810135669 A CN200810135669 A CN 200810135669A CN 101320719 A CN101320719 A CN 101320719A
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- carrier plate
- solder mask
- opening
- line carrier
- aperture
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The invention provides a wiring support plate, suitable for connecting at least one projection, comprising: a base plate having a surface, at least one joint cushion and a solder mask. The joint cushion is configured on surface of the base plate so as to connect the projection. The solder mask, having an opening, is covered on surface of the base plate so as to expose part of the joint cushion. The invention is characterized in that the opening is provided with a first end and a second end. The first end is far from the joint cushion, compared with the second end, and the first end is provided with an aperture bigger than the same of the second end.
Description
Technical field
The invention relates to a kind of line carrier plate and preparation method thereof, and particularly have at least one up big and down small line carrier plate with the opening that goes out joint sheet cruelly and preparation method thereof relevant for a kind of its surperficial solder mask.
Background technology
Electronic product is along with the demand in market and under advanced technology cooperatively interacts at present, add every 3C Product and hammer at the universalness of the portable convenience and the market demand, traditional one chip encapsulation technology can't satisfy the noveltyization market demand day by day gradually, and possessing light, thin, short, little product performance and increase packaging density and manufacturing and designing of low-cost characteristic is well known product trend.Therefore, under light, thin, short, little prerequisite, the packaged type that utilizes various differences to pile up the integrated circuit (IC) of various difference in functionalitys is integrated and is reduced encapsulation volume and package thickness, is the main flow of present various encapsulating products developing target market researchs.With present volume production encapsulating products of all kinds, wherein the product of POP (Package on Package) and PIP (Package in Package) is exactly the main flow new product of being researched and developed in response to epoch trend.
Figure 1A illustrates for the pre-welding material on known a kind of its line carrier plate of POP encapsulating structure and with projection on the packaging body that it docks and does not engage preceding generalized section.Figure 1B illustrates and is the local enlarged diagram after pre-welding material shown in Figure 1A and the bump bond.Please also refer to shown in Figure 1A and the 1B, when first packaging body 100 and second packaging body 200 pile up, be to utilize the mode of reflow to make the tin ball 110 that is disposed on first packaging body 100 be molten condition and engage, electrically connect and the two is constituted with corresponding projection 210 on second packaging body 200.
Yet, shown in Figure 1B, in the process of reflow, because the less and capillary pass of bore size of tin ball 110 upper ends is can upwards be overflowed by the opening part of its upper end after 110 fusions of tin ball, and its below can present the state of hollow.So, can cause the situation that electrically can't be connected between first packaging body 100 and second packaging body 200, and then reduce the yield of product.
Summary of the invention
The invention provides a kind of line carrier plate and preparation method thereof, it is mainly by the thickness that changes solder mask and the shape of opening thereof, make the pre-welding material that is arranged in opening overflow the reliability when engaging with other packaging body by opening in that the technology of reflow is unlikely to increase line carrier plate.
The invention provides a kind of line carrier plate, be suitable for connecting at least one projection.This line carrier plate comprises a substrate, at least one joint sheet and a solder mask.Substrate has a surface.This bond pad arrangement is on the surface of substrate, to connect above-mentioned projection.Solder mask is covered in the surface of substrate and has an opening, to expose the joint sheet of part.Wherein, this opening has one first end and one second end, and first end compared to second end away from this joint sheet, and the aperture of first end is greater than the aperture of second end.
In one embodiment of this invention, the thickness of solder mask is greater than 30 μ m.
In one embodiment of this invention, the thickness of solder mask is preferably between 50 μ m-150 μ m.
In one embodiment of this invention, the ratio in the aperture of the aperture of second end and first end is preferably between 0.8-0.9.
In one embodiment of this invention, above-mentioned opening is a conical mouths.
In one embodiment of this invention, line carrier plate also comprises a pre-welding material, and it is disposed on the joint sheet that exposes, and joint sheet is to be connected with projection via pre-welding material.
In one embodiment of this invention, solder mask is to form by multilayer scolder mask stack is folded.
The present invention provides a kind of manufacture method of line carrier plate in addition, and it comprises the following steps.At first, provide a core layer, one first patterned line layer and one second patterned line layer.Wherein, first patterned line layer and second patterned line layer are disposed at respectively on the first surface and a second surface of core layer, being electrically connected to each other by a plurality of conductive through holes that run through this core layer, and first patterned line layer has at least one joint sheet.Then, on first patterned line layer, form a solder mask.At last, in solder mask, form an opening, to expose the joint sheet of part.Wherein, this opening has one first end and one second end, and first end compared to second end away from this joint sheet, and the aperture of first end is greater than the aperture of second end.
In one embodiment of this invention, the thickness of solder mask is greater than 30 μ m.
In one embodiment of this invention, the thickness of solder mask is preferably between 50 μ m-150 μ m.
In one embodiment of this invention, the ratio in the aperture of the aperture of second end and first end is preferably between 0.8-0.9.
In one embodiment of this invention, above-mentioned opening is a conical mouths.
In one embodiment of this invention, solder mask is to form by multilayer scolder mask stack is folded.Have an opening in each solder mask respectively, and the aperture of second end of each opening is greater than the aperture of first end of the opening that is positioned at its below.
In one embodiment of this invention, form a pre-welding material on the joint sheet that the manufacture method of line carrier plate also is included in opening and is exposed.
Line carrier plate of the present invention and preparation method thereof mainly is by the thickness that increases solder mask, and forms in order to expose the up big and down small opening of joint sheet in solder mask.Because the aperture of the upper end of this opening is greater than the aperture of its lower end, therefore, when carrying out reflow process, be arranged in that the pre-welding material of opening is unlikely to be overflowed the reliability when engaging with other packaging body with the increase line carrier plate by opening.
Description of drawings
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below, wherein:
Figure 1A illustrates for the pre-welding material on known a kind of its line carrier plate of POP encapsulating structure and with projection on the packaging body that it docks and does not engage preceding generalized section.
Figure 1B illustrates and is the local enlarged diagram after pre-welding material shown in Figure 1A and the bump bond.
Fig. 2 A-2C illustrates and is the making flow process generalized section according to a kind of line carrier plate of one embodiment of the invention.
Fig. 2 D illustrates to form the generalized section of a pre-welding material on the joint sheet shown in Fig. 2 C.
Fig. 3 A-3I illustrates the making flow process generalized section into according to another embodiment of the present invention a kind of line carrier plate.
Fig. 4 illustrates the generalized section that engages with other chip-packaging structure into the chip-packaging structure shown in Fig. 3 I.
Fig. 5 illustrates the generalized section that engages with other chip-packaging structure for the line carrier plate that carries chip.
Embodiment
Fig. 2 A-2C illustrates and is the making flow process generalized section according to a kind of line carrier plate of one embodiment of the invention.At first, please refer to shown in Fig. 2 A, a core layer 310, one first patterned line layer 320 and one second patterned line layer 330 are provided.First patterned line layer 320 and second patterned line layer 330 are disposed at respectively on the first surface 310a and second surface 310b of core layer 310, to be electrically connected to each other by a plurality of conductive through holes 312 that run through this core layer 310.In this embodiment, core layer 310 can be for by the substrate that dielectric material constituted, and first patterned line layer 320 and one second patterned line layer 330 for example are to be formed by the Copper Foil etching.In addition, has at least one joint sheet 322 on first patterned line layer 320.
Then, please refer to shown in Fig. 2 B, on first patterned line layer 320, form a solder mask 340.Wherein, the thickness of this solder mask 340 for example is greater than 30 μ m, and its thickness is preferably between 50 μ m-150 μ m.And when being on first patterned line layer 320 to form solder mask 340, also can form another solder mask 350 on second patterned line layer 330, but, this solder mask 350 does not need special thickening, as long as identical, be about 30 μ m and get final product with the thickness of general solder mask 350.
Afterwards, please refer to shown in Fig. 2 C, in solder mask 340, form an opening 342, to expose the joint sheet 322 of part.This opening 342 has one first end 342a and one second end 342b, and away from this joint sheet 322, and the aperture D1 of the first end 342a promptly slightly is the opening of a taper greater than the aperture D2 of the second end 342b to this first end 342a compared to the second end 342b.So, promptly finish the basic making flow process of line carrier plate of the present invention 300.When actual fabrication, can form this up big and down small opening 342 by the parameter of control exposure, development.In addition, in one embodiment of this invention, the ratio of the aperture D1 of the aperture D2 of the second end 342b and the first end 342a is preferably between 0.8-0.9.And in this embodiment, solder mask 340 also can come out the part in the middle of first patterned line layer 320, with carries chips.
After finishing above-mentioned making flow process, next, please refer to shown in Fig. 2 D, can on the joint sheet 322 that opening 342 is come out, form a pre-welding material 360.Because the opening 342 in the solder mask 340 of the present invention presents a up big and down small shape, therefore, follow-up carry out reflow process with this pre-welding material 360 when docking the bump bond of packaging body, unlikely generation pre-welding material 360 is by the situation of upwards inhaling and overflowing, therefore, can help to promote the reliability of the POP encapsulating structure that completes.
Fig. 3 A-3I illustrates the making flow process generalized section into according to another embodiment of the present invention a kind of line carrier plate.Because when making solder mask, its thickness possibly can't once promptly reach 50 μ m-150 μ m, therefore, can piling up by the multilayer solder mask to reach required thickness.At first, please refer to shown in Fig. 3 A, a core layer 310, one first patterned line layer 320 and one second patterned line layer 330 are provided.First patterned line layer 320 and second patterned line layer 330 are disposed at respectively on the first surface 310a and second surface 310b of core layer 310, to be electrically connected to each other by a plurality of conductive through holes 312 that run through this core layer 310.Has at least one joint sheet 322 on this first patterned line layer 320.
Afterwards, please refer to shown in Fig. 3 B, on first patterned line layer 320, form a solder mask 370.The thickness of this solder mask 370 can be identical with the thickness of general solder mask, is about 30 μ m and gets final product.Next, please refer to shown in Fig. 3 C, in solder mask 370, form an opening 372, to expose the joint sheet 322 of part.Similarly, the aperture at the top of this opening 372 promptly slightly is the opening of a taper greater than the aperture of its bottom.
Come again, please refer to shown in Fig. 3 D, on solder mask 370, form another solder mask 380.And the thickness of the solder mask 380 that is this time piled up is like this approximately between 20 μ m-120 μ m, can make the thickness of whole solder mask reach the thickness of 50 μ m-150 μ m.Afterwards, please refer to shown in Fig. 3 E, in solder mask 380, form an opening 382.Similarly, the aperture at the top of this opening 382 is greater than the aperture of its bottom.In addition, the aperture of the bottom of opening 382 can be greater than the aperture at opening 372 its tops below it, to form a up big and down small and stepped opening.In this embodiment, be with two-layer solder mask be stacked as example explaining, yet, also can form solder mask, and in each solder mask, form a up big and down small opening respectively and get final product by piling up of a plurality of solder masks with desired thickness.
Next, please refer to shown in Fig. 3 F, on joint sheet 322, form a pre-welding material 360, and shown in Fig. 3 G, this pre-welding material 360 of reflow.Afterwards, please refer to shown in Fig. 3 H, with mode therewith first patterned line layer 320 electric connections of line carrier plate 300 of a chip 400 with chip bonding, and on line carrier plate 300, form a packing colloid 390, to cover this chip 400, so, promptly form a chip-packaging structure 500.At last, please refer to shown in Fig. 3 I, remove the packing colloid 390 of part,, so, can be connected with the packaging body of butt joint to expose the scolder that is filled in opening 372 and 382.Because on this line carrier plate 300, no matter packing colloid 390 is to be cut to which kind of degree of depth, its opening 372 and 382 all is to present up big and down small state.Therefore, when carrying out reflow process, with the bump bond of the scolder of line carrier plate 300 and other packaging body the time, be arranged in that the scolder of opening of solder mask is all unlikely to be overflowed by opening, and the phenomenon of generation hollow, the reliability when engaging with other packaging body to increase line carrier plate.
Fig. 4 illustrates the generalized section that engages with other chip-packaging structure into the chip-packaging structure shown in Fig. 3 I.Please refer to shown in Figure 4, another is to be stacked on the chip-packaging structure 500 with the chip-packaging structure 600 that the routing juncture forms, and by the solder bonds of reflow process with projection on the substrate of chip-packaging structure 600 and chip-packaging structure 500, chip-packaging structure 500 is constituted with chip-packaging structure 600 electrically connect, to form the encapsulating structure of a POP pattern.
Fig. 5 illustrates the generalized section that engages with other chip-packaging structure for the line carrier plate that carries chip.Please refer to shown in Figure 5ly, a chips 400 ' is that the mode with chip bonding is disposed on the line carrier plate 300, to form a chip-packaging structure 500 '.Afterwards, another is to be stacked on the chip-packaging structure 500 ' with the chip-packaging structure 600 that the routing juncture forms, and by the solder bonds of reflow process with projection on the substrate of chip-packaging structure 600 and chip-packaging structure 500 ', chip-packaging structure 500 is constituted with chip-packaging structure 600 ' electrically connect, to form the encapsulating structure of another kind of POP pattern.
In sum, line carrier plate of the present invention and preparation method thereof mainly is by the thickness that increases solder mask, and forms up big and down small in order to expose the opening of joint sheet in solder mask.So, when carrying out reflow process with the time with the bump bond of the scolder of line carrier plate and other packaging body, be arranged in that the scolder of opening of solder mask is unlikely to be overflowed by opening, and the phenomenon of hollow take place, the reliability when engaging with other packaging body to increase line carrier plate.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that claim scope of the present invention defined.
Claims (14)
1. a line carrier plate is suitable for connecting at least one projection, it is characterized in that, comprising:
One substrate has a surface;
At least one joint sheet is configured in this surface of this substrate, in order to connect this projection; And
One solder mask, be covered in the surface of this substrate, and this solder mask has an opening, to expose this joint sheet of part, wherein this opening has one first end and one second end, and this first end compared to this second end away from this joint sheet, and the aperture of this first end is greater than the aperture of this second end.
2. line carrier plate as claimed in claim 1 is characterized in that, wherein the thickness of this solder mask is greater than 30 μ m.
3. line carrier plate as claimed in claim 2 is characterized in that, wherein the thickness of this solder mask is preferably between 50 μ m-150 μ m.
4. line carrier plate as claimed in claim 1 is characterized in that, wherein the ratio in the aperture of the aperture of this second end and this first end is preferably between 0.8-0.9.
5. line carrier plate as claimed in claim 1 is characterized in that, wherein this opening is a conical mouths.
6. line carrier plate as claimed in claim 1 is characterized in that, wherein also comprises a pre-welding material, and it is disposed on this joint sheet of part that exposes, and this joint sheet is to be connected with this projection via this pre-welding material.
7. line carrier plate as claimed in claim 1 is characterized in that, wherein this solder mask is to form by multilayer scolder mask stack is folded.
8. the manufacture method of a line carrier plate is characterized in that, comprising:
One core layer, one first patterned line layer and one second patterned line layer are provided, wherein this first patterned line layer and this second patterned line layer are disposed at respectively on the first surface and a second surface of this core layer, being electrically connected to each other by a plurality of conductive through holes that run through this core layer, and this first patterned line layer has at least one joint sheet;
On this first patterned line layer, form a solder mask; And
Form an opening in this solder mask, to expose this joint sheet of part, wherein this opening has one first end and one second end, and this first end compared to this second end away from this joint sheet, and the aperture of this first end is greater than the aperture of this second end.
9. the manufacture method of line carrier plate as claimed in claim 8 is characterized in that, wherein the thickness of this solder mask is greater than 30 μ m.
10. the manufacture method of line carrier plate as claimed in claim 9 is characterized in that, wherein the thickness of this solder mask is preferably between 50 μ m-150 μ m.
11. the manufacture method of line carrier plate as claimed in claim 8 is characterized in that, wherein the ratio in the aperture of the aperture of this second end and this first end is preferably between 0.8-0.9.
12. the manufacture method of line carrier plate as claimed in claim 8 is characterized in that, wherein this opening is a conical mouths.
13. the manufacture method of line carrier plate as claimed in claim 8, it is characterized in that, wherein this solder mask is to form by multilayer scolder mask stack is folded, and respectively have an opening respectively in this solder mask, and respectively the aperture of this second end of this opening greater than the aperture of this first end of this opening that is positioned at its below.
14. the manufacture method of line carrier plate as claimed in claim 8 is characterized in that, forms a pre-welding material on this joint sheet that wherein also is included in this opening and is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101356696A CN101320719A (en) | 2008-07-09 | 2008-07-09 | Line carrier plate and preparation thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101356696A CN101320719A (en) | 2008-07-09 | 2008-07-09 | Line carrier plate and preparation thereof |
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| Publication Number | Publication Date |
|---|---|
| CN101320719A true CN101320719A (en) | 2008-12-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008101356696A Pending CN101320719A (en) | 2008-07-09 | 2008-07-09 | Line carrier plate and preparation thereof |
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| CN (1) | CN101320719A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103819956A (en) * | 2014-03-01 | 2014-05-28 | 陈廷 | Pen for covering metal foils on copper-clad plate |
| CN104409437A (en) * | 2014-12-04 | 2015-03-11 | 江苏长电科技股份有限公司 | Packaging structure for rewiring of packaged two-sided BUMP chip and manufacturing method of packaging structure |
| TWI604575B (en) * | 2017-01-26 | 2017-11-01 | 欣興電子股份有限公司 | Package structure and method of bonding substrate |
| CN114365584A (en) * | 2020-06-29 | 2022-04-15 | 庆鼎精密电子（淮安）有限公司 | Circuit board and manufacturing method thereof |
-
2008
- 2008-07-09 CN CNA2008101356696A patent/CN101320719A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103819956A (en) * | 2014-03-01 | 2014-05-28 | 陈廷 | Pen for covering metal foils on copper-clad plate |
| CN104409437A (en) * | 2014-12-04 | 2015-03-11 | 江苏长电科技股份有限公司 | Packaging structure for rewiring of packaged two-sided BUMP chip and manufacturing method of packaging structure |
| TWI604575B (en) * | 2017-01-26 | 2017-11-01 | 欣興電子股份有限公司 | Package structure and method of bonding substrate |
| CN114365584A (en) * | 2020-06-29 | 2022-04-15 | 庆鼎精密电子（淮安）有限公司 | Circuit board and manufacturing method thereof |
| TWI770547B (en) * | 2020-06-29 | 2022-07-11 | 大陸商慶鼎精密電子（淮安）有限公司 | Circuit board and manufacturing method thereof |
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