CN101859733B - Semiconductor packaging structure, support plate for same, and manufacture method thereof - Google Patents
Semiconductor packaging structure, support plate for same, and manufacture method thereof Download PDFInfo
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- CN101859733B CN101859733B CN2009101345520A CN200910134552A CN101859733B CN 101859733 B CN101859733 B CN 101859733B CN 2009101345520 A CN2009101345520 A CN 2009101345520A CN 200910134552 A CN200910134552 A CN 200910134552A CN 101859733 B CN101859733 B CN 101859733B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
The invention discloses a semiconductor packaging structure, a support plate for the same and a manufacture method thereof. A groove is formed in a solder pad of the support plate so as to be filled with solder and enable the solder to be distributed on the upper surface of the solder pad. After the solder pad and the solder are welded, a thermal stress focal point can be transferred to the contact of the solder and the opening edge of the groove so as to reduce the risk of forming a fracture surface on the upper surface on the solder pad; meanwhile, the groove with the structure can also reduce the maximum value of the thermal stress, thereby improving the yield of reliable test and prolonging the service life of the product.
Description
[technical field]
The invention relates to a kind of semiconductor packaging structure, semiconductor packaging structure with support plate and manufacturing approach thereof, particularly relevant for a kind of in order to the semiconductor packaging structure that increases the reliable welding degree, semiconductor packaging structure with support plate and manufacturing approach thereof.
[background technology]
Now; The semiconductor packages industry develops the packaging structure that various different types gradually in order to satisfy the demand of various high-density packages, and wherein common packaging structure with substrate (substrate) comprises ball grid array packaging structure (ball grid array; BGA), pin array packaging structure (pin grid array; PGA), the land array packaging structure (land grid array, chip encapsulation construction LGA) or on the substrate (board onchip, BOC) etc.In above-mentioned packaging structure, a upper surface of said substrate carries at least one chip, and several connection pads of chip is electrically connected to several weld pads of the upper surface of said substrate through routing (wire bonding) or projection (bumping) manufacture process.Simultaneously, a lower surface of said substrate also must provide a large amount of weld pads, to weld several outputs.Moreover; For the substrate that utilizes projection combination chip; Said substrate is selected from a multilayer circuit board usually, and it provides the surface circuit layer forming required weld pad at upper surface, and according to product demand; Sometimes said weld pad possibly be pre-formed pre-welding material (pre-solder), to increase the reliability that combines with the projection of chip.Therefore, how to make base plate for packaging, also be an important key technology of encapsulation industry with pre-welding material.
Please with reference to shown in Figure 1A and the 1B; It discloses a kind of existing structure and assembling sketch map that has the base plate for packaging of pre-welding material and have the chip of projection; Wherein a base plate for packaging 10 is selected from a multilayer circuit board, and it provides a circuit layer 11 and a welding resisting layer 12 (solder mask) at upper surface.Said welding resisting layer 12 covers said circuit layer 11, and said welding resisting layer 12 has several openings 121 simultaneously, and it exposes the part surface of said circuit layer 11 to the open air, for forming a weld pad 13.Then further form a pre-welding material 14 on each said weld pad 13.Moreover a chip 20 is that (indicate) goes up and form several circuit layers 21, a protective layer 22, several projection lower metal layers (UBM) 23 and several projections 24 on an active surface.Said protective layer 22 covers said circuit layer 21, and said protective layer 22 has several openings (not indicating) simultaneously, and it exposes the part surface of said circuit layer 21 to the open air.Said projection lower metal layer 23 is formed on the circuit layer 21 in the said opening.Said projection 24 is formed on the said projection lower metal layer 23.When utilizing high temperature to weld; The projection 24 of the circuit layer 21 of said chip 20 through the auxiliary of said pre-welding material 14 solder bond on the weld pad 13 of said base plate for packaging 10; And said pre-welding material 14 incorporates in the said projection 24; Thereby accomplish the welding action, said chip 20 is electrically connected on the said base plate for packaging 10.
Yet the pre-welding material 14 of said base plate for packaging 10 still has following problems on reality is used, and for example: along with the trend toward miniaturization of semiconductor packaging structure, the size and the spacing of the weld pad 13 of said base plate for packaging 10 are dwindled day by day.When the upper surface reduced diameter to 80 of said weld pad 13 micron below (um) and the adjacent spacing of said weld pad 13 when being contracted to below 160 microns; Though said pre-welding material 14 can promote the welding character between said projection 24 and the weld pad 13; But when encapsulating products being carried out reliability test (130 ℃/humidity 85% continued 96/168 hour and carrying out 500 circulations under-55 to 125 ℃), but produce a plane of fracture (fracture) 15 and cause test crash at the binding site place of said circuit layer 11 easily with weld pad 13 follow-up.Though the reason of the said plane of fracture 15 of above-mentioned generation is said circuit layer 11 and is identical material (being mainly copper) with weld pad 13; But because of weld pad 13 is in the re-plating afterwards; Therefore the adhesion at binding site place at both is comparatively fragile; Thermal stress is concentrated and produce the test defect of the said plane of fracture 15 at binding site so that work as, and then influences test yields (yield).
So, be necessary to provide a kind of semiconductor packaging structure, semiconductor packaging structure with support plate and manufacturing approach thereof, to solve the existing in prior technology problem.
[summary of the invention]
Main purpose of the present invention is to provide a kind of semiconductor packaging structure, semiconductor packaging structure with support plate and manufacturing approach thereof; It is in the weld pad of support plate, to form groove; So that insert scolder, and make scolder be covered with the upper surface of weld pad, after weld pad and scolder weld; It can be transferred to the thermal stress concentrated position outlet lip of groove; To reduce the risk that between weld pad and circuit layer, forms the plane of fracture, the structure of groove also can reduce the thermal stress maximum simultaneously, and then promotes yields and product useful life of reliability test.
For reaching above-mentioned purpose, the present invention provides a kind of semiconductor packaging structure to use support plate, and it is on a support plate, to be provided with: a circuit layer is formed on the surface of said support plate; One insulating barrier covers on the said circuit layer, and several openings of said insulating barrier formation, with the said circuit layer of an exposed part; Several weld pads be formed on the circuit layer in the said opening, and each said weld pad are concaved with a groove; And several scolders, be respectively formed in the groove of each said weld pad, and be covered with the upper surface of each said weld pad.
In one embodiment of this invention, said support plate is selected from a circuit substrate, and said scolder is as a pre-welding material; Perhaps, said support plate is selected from a chip, and said scolder is as a projection.
In one embodiment of this invention, the bottom portion of groove of said weld pad extends downward in the depressed part of said circuit layer; Perhaps, the bottom portion of groove of said weld pad runs through downwards through said circuit layer.
In one embodiment of this invention, the adjacent spacing of the weld pad of said support plate is less than 160 microns; And the upper surface external diameter of the weld pad of said support plate is less than 80 microns.
Moreover; The present invention provides the manufacturing approach of a kind of semiconductor packaging structure with support plate, and it comprises step: a support plate is provided, and it is provided with a circuit layer and an insulating barrier on a surface; Said insulating barrier covers said circuit layer and forms several openings, with the said circuit layer of an exposed part; Remove at least a portion thickness of the circuit layer in the said opening; Form on the circuit layer of a weld pad in each said opening, said weld pad has a groove; And, in the groove of each said weld pad, form a scolder, and make said scolder be covered with the upper surface of each said weld pad.
In one embodiment of this invention, in the step of at least a portion thickness of removing said circuit layer, select to utilize etching solution (etchant) or plasma (plasma) to carry out etching, so that said circuit layer forms a depressed part; Perhaps, select to utilize laser drill (laser drilling) or machine drilling (mechanicaldrilling) to run through the circuit layer in the said opening.
In one embodiment of this invention, in the step that forms said weld pad, utilize and form said weld pad on the circuit layer of electroless plating (electroless plating) program in each said opening with said groove.
In one embodiment of this invention, in the step that forms said scolder, utilize plating (plating) or printing (printing) in the groove of each said weld pad, to insert said scolder, and make it be covered with the upper surface of each said weld pad.
In one embodiment of this invention, after the step that forms said scolder, other comprises: said scolder is carried out Reflow Soldering (reflow).
In one embodiment of this invention, said support plate is selected from a circuit substrate, and said scolder is as a pre-welding material; Perhaps, said support plate is selected from a chip, and said scolder is as a projection.
In one embodiment of this invention, the adjacent spacing of the weld pad of said support plate is less than 160 microns; And the upper surface external diameter of the weld pad of said support plate is less than 80 microns.
In addition, the present invention provides a kind of semiconductor packaging structure, and it comprises: a circuit substrate, and it has: one first circuit layer is formed on the surface of said circuit substrate; One first insulating barrier covers on said first circuit layer, and several first openings of said first insulating barrier formation, with said first circuit layer of an exposed part; And several first weld pads, be formed on first circuit layer in said first opening; One chip, it has: a second circuit layer is formed on the active surface of said chip; One second insulating barrier covers on the said second circuit layer, and several second openings of said second insulating barrier formation, with the said second circuit layer of an exposed part; And several second weld pads, being formed on the second circuit layer in said second opening, one of them side of first weld pad of wherein said circuit substrate and second weld pad of said chip is concaved with a groove; And several projections be connected between said first weld pad and said second weld pad, and the scolder of said projection are inserted in the said groove.
In one embodiment of this invention, said first weld pad is provided with said groove, and said bottom portion of groove extends downward in the depressed part of said first circuit layer; Perhaps, said bottom portion of groove runs through downwards through said first circuit layer.
In one embodiment of this invention, said first weld pad is provided with said groove, and the adjacent spacing of said first weld pad is less than 160 microns; And the upper surface external diameter of the weld pad of said first support plate is less than 80 microns.
In one embodiment of this invention, said second weld pad is provided with said groove, and said bottom portion of groove extends downward in the depressed part of said second circuit layer; Perhaps, said bottom portion of groove runs through downwards through said second circuit layer.
[description of drawings]
Figure 1A and 1B: the existing sketch map that has the base plate for packaging of pre-welding material and have the chip of projection.
Fig. 2: the semiconductor packaging structure of first embodiment of the invention is with the sketch map of support plate.
Fig. 3 A to 3D: the semiconductor packaging structure of first embodiment of the invention is with the flow chart of the manufacturing approach of support plate.
Fig. 4: the sketch map of the semiconductor packaging structure of first embodiment of the invention before carrying out solder bond.
Fig. 5: the sketch map of the semiconductor packaging structure of first embodiment of the invention after carrying out solder bond.
Fig. 6 A to 6D: the semiconductor packaging structure of second embodiment of the invention is with the flow chart of the manufacturing approach of support plate.
Fig. 7: the sketch map of the semiconductor packaging structure of third embodiment of the invention before carrying out solder bond.
[embodiment]
For making above-mentioned purpose of the present invention, characteristic and advantage more obviously understandable, hereinafter is special lifts preferred embodiment of the present invention, and conjunction with figs., elaborates as follows:
In preferred embodiment of the present invention, semiconductor packaging structure of the present invention mainly is that a circuit layer, an insulating barrier, several weld pads and several scolders are set on a support plate with support plate.Said support plate mainly is selected from base plate for packaging, or also possibly be selected from chip.The present invention is arranged with in order to the middle position at the weld pad of said support plate and forms a groove, to fill scolder and to make it be covered with the upper surface of said weld pad.For example, please with reference to shown in Figure 2, the semiconductor packaging structure of first embodiment of the invention mainly is on a circuit substrate 30, to be provided with support plate: a circuit layer 31 is formed on the surface of said circuit substrate 30; One insulating barrier 32 covers on the said circuit layer 31, and said insulating barrier 32 several openings 321 of formation, with the said circuit layer 31 of an exposed part; Several weld pads 33 be formed on the circuit layer 31 in the said opening 321, and each said weld pad 33 are concaved with a groove 331; And several scolders 34, be respectively formed in the groove 331 of each said weld pad 33, and be covered with the upper surface of each said weld pad 33.The present invention will utilize Fig. 3 A to 3D to specify manufacturing process and the detail structure thereof of the semiconductor packaging structure of Fig. 2 with support plate one by one in hereinafter.
Please with reference to shown in Fig. 3 A; The semiconductor packaging structure of first embodiment of the invention with the manufacturing approach first step of support plate is: a circuit substrate 30 is provided; It is provided with a circuit layer 31 and an insulating barrier 32 on a surface; Said insulating barrier 32 covers said circuit layer 31 and forms several openings 321, with the said circuit layer 31 of an exposed part.In this step; Said circuit substrate 30 (that is support plate) is to be selected from the semiconductor encapsulation to use circuit substrate; For example be selected from tellite, ceramic circuit board or the flexible circuit board of single or multiple lift; And said circuit substrate 30 preferably is selected from a flip-chip (flip chip, FC) base plate for packaging.(for example upper surface) is provided with said circuit layer 31 to said circuit substrate 30 on a surface; And the packaging structure that said circuit substrate 30 is looked its application possibly have other circuit design; For example said circuit substrate 30 portion within it is provided with other interconnective internal circuit layers (not indicating); And be provided with another surface circuit layer (indicating) on another surface, with provide several I/O ends (input/output, IO).In the present embodiment, the material of said circuit layer 31 preferably is selected from copper, aluminium, gold, silver or its equivalent conducting metal.Said insulating barrier 32 covers said circuit layer 31; And said insulating barrier 32 is preferably by the formed welding resisting layer of liquid photosensitive material (solder mask); It can form said several openings 321 through existing manufacturing process such as exposure and developments, with the said circuit layer 31 of an exposed part.
Please with reference to shown in Fig. 3 B, the semiconductor packaging structure of first embodiment of the invention with manufacturing approach second step of support plate is: at least a portion thickness of removing the circuit layer 31 in the said opening 321.In this step; The present invention selects to utilize etching solution (etchant) or plasma (plasma) to carry out etching, to remove at least a portion thickness of the circuit layer 31 in the said opening 321, does not run through said circuit layer 31 but suitably be controlled to; So not only can clean the surface of said circuit layer 31; And can form a depressed part 311, increasing the bonded area of said circuit layer 31 and the weld pad 33 of follow-up formation, and then increase both bond strengths.In above-mentioned etching program, only can increase the degree of depth of said opening 321, but can not enlarge the internal diameter size of said opening 321 usually because of having produced said depressed part 311.
Please with reference to shown in Fig. 3 C, the semiconductor packaging structure of first embodiment of the invention with the manufacturing approach third step of support plate is: form on the circuit layer 31 of a weld pad 33 in each said opening 321, said weld pad 33 has a groove 331.In this step; The present invention preferably utilizes electroless plating (electrolessplating) program to form said weld pad 33; And before carrying out the electroless plating program; Preferably be pre-formed a patterning photoresist layer (not illustrating) on said insulating barrier 32, the corresponding said opening 321 of said patterning photoresist layer forms several windows (not illustrating), so that define the upper surface external diameter of said weld pad 33 through said window.The material of said weld pad 33 preferably is selected from copper, aluminium, gold, silver or its equivalent conducting metal.The present invention does not limit the long-pending thickness in Shen of said weld pad 33, but the upper surface external diameter of said weld pad 33 preferably is controlled at less than 80 microns, and the adjacent spacing of said weld pad 33 preferably is controlled at less than 160 microns.Processing conditions through suitable control electroless plating program; Said weld pad 33 amasss Shen on the depressed part 311 that is formed on the circuit layer 31 in each said opening 321; And extend out to the upper surface of said insulating barrier 32 along the hole wall of said opening 321, and said weld pad 33 will form said groove 331 in its middle position.The shape of said groove 331 is shapes of corresponding said opening 321, and both are all cylindrically usually, but are not limited to this.The quantity of the said groove 331 that each said weld pad 33 has is preferably 1, but also is not limited thereto.
Please with reference to shown in Fig. 3 D, the semiconductor packaging structure of first embodiment of the invention with manufacturing approach the 4th step of support plate is: in the groove 331 of each said weld pad 33, form a scolder 34, and make said scolder 34 be covered with the upper surface of each said weld pad 33.In this step, the present invention can select to utilize the program of electroplating (plating) or printing (printing) in the groove 331 of each said weld pad 33, to insert said scolder 34.The material of said scolder 34 can be selected from tin, solder containing pb or lead-free solder; For example: above-mentioned solder containing pb can be selected from Sn63/Pb37 (containing 63% tin and 37% lead); And above-mentioned lead-free solder can be selected from Sn0.7Cu (containing 0.7% copper), Sn3.5Ag (containing 3.5% copper), Sn3.5Ag0.7Cu (containing 3.5% silver and 0.7% copper), Sn9Zn (containing 9% zinc), Sn5Sb (containing 5% antimony), Sn58Bi (containing 58% bismuth), Sn52In (containing 52% indium), In3Ag (containing 97% indium and 3% silver), Au20Sn (containing 80% gold and 20% tin), but is not limited to this.After accomplishing plating or print routine, said scolder 34 will fill up said groove 331 and overflow outer to the entire upper surface that is covered with said weld pad 33, to use as pre-welding material.Moreover as shown in Figure 2 in one embodiment, the present invention in addition can be after forming said scolder 34, further to said scolder 34 Reflow Solderings (reflow), forms circular-arc outward appearance because of cohesive force when making said scolder 34 fusions.
Please with reference to shown in Figure 4, the circuit substrate 30 of first embodiment of the invention is a base plate for packaging, and it is can be in order to combine a chip 40, to constitute a flip-chip type semiconductor packaging structure.In one embodiment, said chip 40 is to be selected from the silicon that is formed by semiconductor crystal wafer cutting, and it is (to indicate) on an active surface to go up to form several circuit layers 41, an insulating barrier 42, several projection lower metal layers 43 and several projections 44.Said insulating barrier 42 covers said circuit layer 41, and said insulating barrier 42 has several openings 421 simultaneously, and it exposes the part surface of said circuit layer 41 to the open air.Said projection lower metal layer 43 is formed on the circuit layer 41 in the said opening 421.Said projection 44 is formed on the said projection lower metal layer 43.Said projection 44 can be selected from identical or be different from the material of said scolder 34, for example is selected from tin or various solder containing pb or lead-free solder.
Please with reference to shown in Figure 5; When utilizing high temperature to weld; The projection 44 of the circuit layer 41 of said chip 40 through the auxiliary of said scolder 34 solder bond on the weld pad 33 of said circuit substrate 30; And the scolder 34 in the upper surface of said weld pad 33 and the groove 331 incorporates in the said projection 44 and becomes a welding structure, thereby said chip 40 is electrically connected on the said circuit substrate 30.After said flip-chip type semiconductor packaging structure was manufactured in completion, then the present invention carried out reliability test (130 ℃/humidity 85% continued 96/168 hour and under-55 to 125 ℃, carried out 500 times to circulate) to it.Test result shows; Even below the upper surface reduced diameter to 80 of the weld pad 33 of said circuit substrate 30 micron and the adjacent spacing of said weld pad 33 be contracted to below 160 microns; Welding structure between said projection 44 and the weld pad 33 still is enough to bear because of thermal coefficient of expansion (CTE) thermal stress that difference caused, and does not form the plane of fracture (fracture).Confirm that through analyzing because the weld pad 33 of circuit substrate 30 of the present invention is provided with said groove 331 ccontaining said scolders 34, therefore said groove 331 can provide bigger surface area, makes to have bigger welding combination area between said weld pad 33 and the projection 44.Simultaneously, the thermal stress centrostigma S of said welding structure also will be transferred to the outlet lip place of the groove 33 of said weld pad 33, and that the maximum of thermal stress also can reduce significantly is many.Be with; The design that the present invention utilizes said groove 331 ccontaining said scolders 34 really can be in the solder bond intensity of strengthening during the high-temperature soldering between said projection 44 and the weld pad 33; And reduce the test defect incidence, and then promote yields (yield) and product useful life of test.
Please with reference to shown in Fig. 6 A to 6D; The semiconductor packaging structure of second embodiment of the invention is similar in appearance to first embodiment of the invention with the manufacturing approach of support plate; And roughly continue to use same reference numbers, in second step circuit layer 31 in the opening of selecting to utilize laser drill (laser drilling) or machine drilling (mechanical drilling) to run through said insulating barrier 32 321 but difference is in said second embodiment.Therefore, in third step, groove 331 bottoms of said weld pad 33 will be run through downwards through a bit of approximately predetermined length of said circuit layer 31, and the said length that runs through is suitably to adjust according to product demand.By this, can further increase the bonded area of the weld pad 33 of said circuit layer 31 and follow-up formation, and then increase both bond strengths.Moreover in the 4th step, said groove 331 can ccontaining more said scolder 34.When said circuit substrate 30 is incorporated into a chip 40 (shown in Fig. 4 and 5), said groove 331 also can provide bigger surface area, makes to have bigger welding combination area between said weld pad 33 and the projection 44.Simultaneously, the thermal stress centrostigma S of the welding structure of said weld pad 33 and projection 44 also will be transferred to the outlet lip of the groove 33 of said weld pad 33, and the maximum of thermal stress also can significantly reduce.Be with, second embodiment of the invention can further be strengthened the solder bond intensity of said projection 44.
Please with reference to shown in Figure 7; The semiconductor packaging structure of third embodiment of the invention is similar in appearance to first embodiment of the invention; And roughly continue to use same reference numbers; But it is groove design to be applied on the said chip 40 that difference is in said the 3rd embodiment, carries out etching on the said circuit layer 41 that wherein utilizes etching solution or plasma that the opening 421 of the insulating barrier 42 of said chip 40 is exposed earlier, to remove at least a portion thickness of the circuit layer 41 in the said opening 421; But do not run through said circuit layer 41, so can form a depressed part 411 on the surface of said circuit layer 41.Then, and on the depressed part 411 of the circuit layer 41 of said chip 40, form a weld pad 45, and each said weld pad 45 entreats therein the position to be arranged with to form a groove 451, and make a scolder 46 insert in the said groove 451 and be covered with the upper surface of each said weld pad 45.Said scolder 46 more further Reflow Soldering forms projection (bump) shape.Moreover in the 3rd embodiment, said circuit substrate 30 is that a Flip-Chip Using is used substrate, and the weld pad 33 of its upper surface can have the design of said groove 331 equally, uses as pre-welding material with ccontaining said scolder 34.By this; When high-temperature soldering combines said chip 40 and circuit substrate 30; The groove 451 of the weld pad 45 of said chip 40 can increase the solder bond intensity between said weld pad 45 and the scolder 46 equally; And change the outlet lip place of thermal stress centrostigma S to said groove 451, and the thermal stress maximum be can reduce, and yields and product useful life of reliability test promoted.
Moreover; In the 3rd embodiment; In order to make said weld pad 45 have enough height (thickness); The present invention can be on the active lip-deep protective layer 42a of said chip 40 further an extra rerouting insulating barrier (the redistribution insulation layer) 42b that manufactures as said insulating barrier 42, to reach the purpose of the height (thickness) that increases said weld pad 45.In addition; If 41 designs of the circuit layer on the active surface of said chip 40 allow; Circuit layer 41 in the opening 421 that then also possibly select to utilize laser drill or machine drilling to run through said insulating barrier 42; Groove 451 bottoms of said weld pad 45 are run through downwards through a bit of approximately predetermined length of said circuit layer 41 (not illustrating),, and then increased bond strength with the bonded area of the said circuit layer 41 of further increase with the weld pad 45 of follow-up formation.Perhaps; In another embodiment; Weld pad 45 at said chip 40 has possessed under the preceding topic of said groove 451; It is smooth that the upper surface of the weld pad 33 of said circuit substrate 30 also can keep, and omits the design of said groove 331 is set, and only lay traditional pre-welding material (not illustrating) at the upper surface of said weld pad 33.
As stated; Pre-welding material 14 on the weld pad 13 of Fig. 1 and 2 existing base plate for packaging 10 with projection 24 solder bond of said chip 20 after; Still concentrate problems such as producing the said plane of fracture 15 at the binding site place of said circuit layer 11 and weld pad 13 because of thermal stress easily; The present invention of Fig. 3 to 5 is through forming said groove 331 in the weld pad 33 of said structure such as circuit substrate 30 support plates such as grade; So that insert said scolder 34, and make said scolder 34 be covered with the upper surface of said weld pad 33, it can effectively increase bonded area and bond strength between said scolder 34 and the weld pad 33 really.Moreover; After said weld pad 33 and scolder 34 weld; It can be transferred to thermal stress centrostigma S the outlet lip of said groove 331; To reduce the risks that form the planes of fracture on depressed part 311 surfaces of said weld pad 31, the structure of said groove 331 also can reduce the thermal stress maximum simultaneously, and then promotes yields and product useful life of reliability test.
The present invention is described by above-mentioned related embodiment, yet the foregoing description is merely the example of embodiment of the present invention.Must be pointed out that disclosed embodiment does not limit scope of the present invention.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope includes in scope of the present invention.
Claims (11)
1. a semiconductor packaging structure is used support plate, it is characterized in that: on a support plate, be provided with:
One circuit layer is formed on the surface of said support plate;
One insulating barrier covers on the said circuit layer, and several openings of said insulating barrier formation, with the said circuit layer of an exposed part;
Several weld pads be formed on the circuit layer in the said opening, and each said weld pad are concaved with a groove; And
Several scolders are respectively formed in the groove of each said weld pad, and are covered with the upper surface of each said weld pad; Wherein said support plate is a circuit substrate, and the circuit layer in the said opening is removed a part of at least thickness, make said circuit layer form a depressed part, and the bottom portion of groove of said weld pad extends downward in the depressed part of said circuit layer.
2. semiconductor packaging structure as claimed in claim 1 is used support plate, it is characterized in that: said scolder is as a pre-welding material.
3. semiconductor packaging structure as claimed in claim 1 is used support plate, it is characterized in that: the adjacent spacing of the weld pad of said support plate is less than 160 microns; And the upper surface external diameter of the weld pad of said support plate is less than 80 microns.
4. a semiconductor packaging structure is used support plate, it is characterized in that: on a support plate, be provided with:
One circuit layer is formed on the surface of said support plate;
One insulating barrier covers on the said circuit layer, and several openings of said insulating barrier formation, with the said circuit layer of an exposed part;
Several weld pads be formed on the circuit layer in the said opening, and each said weld pad are concaved with a groove; And
Several scolders are respectively formed in the groove of each said weld pad, and are covered with the upper surface of each said weld pad;
Wherein said support plate is a circuit substrate, and the bottom portion of groove of said weld pad runs through downwards through said circuit layer.
5. semiconductor packaging structure as claimed in claim 4 is used support plate, it is characterized in that: said scolder is as a pre-welding material.
6. semiconductor packaging structure as claimed in claim 4 is used support plate, it is characterized in that: the adjacent spacing of the weld pad of said support plate is less than 160 microns; And the upper surface external diameter of the weld pad of said support plate is less than 80 microns.
7. a semiconductor packaging structure is with the manufacturing approach of support plate, and it is characterized in that: said manufacturing approach comprises step:
One support plate is provided, and it is provided with a circuit layer and an insulating barrier on a surface, and said insulating barrier covers said circuit layer and forms several openings, with the said circuit layer of an exposed part;
Remove at least a portion thickness of the circuit layer in the said opening;
Form on the circuit layer of a weld pad in each said opening, said weld pad has a groove; And
In the groove of each said weld pad, form a scolder, and make said scolder be covered with the upper surface of each said weld pad.
8. semiconductor packaging structure, it is characterized in that: said semiconductor packaging structure comprises:
One circuit substrate, it has:
One first circuit layer is formed on the surface of said circuit substrate;
One first insulating barrier covers on said first circuit layer, and several first openings of said first insulating barrier formation, with said first circuit layer of an exposed part, and;
Several first weld pads are formed on first circuit layer in said first opening;
One chip, it has:
One second circuit layer is formed on the active surface of said chip;
One second insulating barrier covers on the said second circuit layer, and several second openings of said second insulating barrier formation, with the said second circuit layer of an exposed part; And
Several second weld pads are formed on the second circuit layer in said second opening; And
Several projections are connected between second weld pad of first weld pad and said chip of said circuit substrate;
Wherein said first weld pad is concaved with a groove, and the scolder of said projection is inserted in the said groove; And
First circuit layer in wherein said first opening is removed a part of at least thickness, make said first circuit layer form a depressed part, and the bottom portion of groove of said first weld pad extends downward in the depressed part of said first circuit layer.
9. semiconductor packaging structure as claimed in claim 8 is characterized in that: said first weld pad is provided with said groove, and the adjacent spacing of said first weld pad is less than 160 microns; And the upper surface external diameter of said first weld pad is less than 80 microns.
10. a semiconductor packaging structure is characterized in that
One circuit substrate, it has:
One first circuit layer is formed on the surface of said circuit substrate;
One first insulating barrier covers on said first circuit layer, and several first openings of said first insulating barrier formation, with said first circuit layer of an exposed part, and;
Several first weld pads are formed on first circuit layer in said first opening;
One chip, it has:
One second circuit layer is formed on the active surface of said chip;
One second insulating barrier covers on the said second circuit layer, and several second openings of said second insulating barrier formation, with the said second circuit layer of an exposed part; And
Several second weld pads are formed on the second circuit layer in said second opening; And
Several projections are connected between second weld pad of first weld pad and said chip of said circuit substrate;
Wherein said first weld pad is provided with a groove, and the scolder of said projection is inserted in the said groove, and said bottom portion of groove runs through downwards through said first circuit layer.
11. semiconductor packaging structure as claimed in claim 10 is characterized in that: said first weld pad is provided with said groove, and the adjacent spacing of said first weld pad is less than 160 microns; And the upper surface external diameter of said first weld pad is less than 80 microns.
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| CN2009101345520A CN101859733B (en) | 2009-04-13 | 2009-04-13 | Semiconductor packaging structure, support plate for same, and manufacture method thereof |
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| CN2009101345520A CN101859733B (en) | 2009-04-13 | 2009-04-13 | Semiconductor packaging structure, support plate for same, and manufacture method thereof |
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| CN102779800B (en) * | 2011-05-09 | 2015-10-07 | 精材科技股份有限公司 | Wafer encapsulation body and forming method thereof |
| TWI489605B (en) * | 2011-05-13 | 2015-06-21 | Xintec Inc | Chip package and manufacturing method thereof |
| US8853853B2 (en) * | 2011-07-27 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures |
| CN103367298B (en) * | 2012-04-09 | 2016-04-20 | 颀邦科技股份有限公司 | Semiconductor package and method for packing thereof |
| US10269747B2 (en) | 2012-10-25 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company | Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices |
| KR102256591B1 (en) * | 2014-10-31 | 2021-05-27 | 서울바이오시스 주식회사 | High efficiency light emitti ng device |
| CN110970390B (en) * | 2019-12-12 | 2021-05-07 | 南通大学 | Fine-spacing copper pillar wafer-level packaging structure and reliability optimization method |
| CN114121868A (en) * | 2020-08-28 | 2022-03-01 | 京东方科技集团股份有限公司 | Substrate and manufacturing method thereof, display device and manufacturing method thereof |
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| JP2002299373A (en) * | 2001-04-02 | 2002-10-11 | Hitachi Ltd | Manufacturing method of semiconductor device |
| CN2689448Y (en) * | 2004-03-04 | 2005-03-30 | 威盛电子股份有限公司 | Circuit carried boards |
| CN2845167Y (en) * | 2005-06-14 | 2006-12-06 | 威盛电子股份有限公司 | Reversed sheet packing structure |
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| JP2002299373A (en) * | 2001-04-02 | 2002-10-11 | Hitachi Ltd | Manufacturing method of semiconductor device |
| CN2689448Y (en) * | 2004-03-04 | 2005-03-30 | 威盛电子股份有限公司 | Circuit carried boards |
| CN2845167Y (en) * | 2005-06-14 | 2006-12-06 | 威盛电子股份有限公司 | Reversed sheet packing structure |
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