JP2007324406A - Substrate treatment method and manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for supporting a substrate capable of properly supporting the substrate without using an adhesive requiring a temporary fixing property and peeling performance, and capable of properly removing even a support substrate and a manufacturing method for a semiconductor device. <P>SOLUTION: The support substrate 29 and a wafer (substrate to be treated) W are joined by solid-phase junction between metallic layers 28 (28A and 28B) formed on each joint surface, and the support substrate 29 is removed by polishing the support substrate 29. Accordingly, since an organic adhesive having the temporary fixing property and the peeling performance which have been required in a conventional device is not needed, and a machining process can be carried out to the wafer W without receiving the constraint of a heat-resistant temperature and the chemical resistance of the adhesive, the formation of an insulating film having excellent adhesion and the stable pattern processing of a terminal surface are enabled. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a substrate processing method for processing a substrate to be processed such as a semiconductor substrate supported by a support substrate, and a semiconductor device manufacturing method using this method.

  In recent years, along with demands for higher functionality and lighter and thinner electronic devices, electronic components have become more densely integrated and densely mounted, and MCM (multi-chip module) or SIP (system-in) using flip-chip mounting. Package) type semiconductor devices are becoming mainstream. Some semiconductor devices of this type employ a configuration in which a second semiconductor chip is flip-chip mounted on a first semiconductor chip.

  FIG. 6 is a cross-sectional view showing a schematic configuration of this type of conventional semiconductor device. The illustrated semiconductor device includes a first semiconductor chip 1 and a second semiconductor chip 2. The second semiconductor chip 2 is flip-chip mounted using a plurality of bumps 3 at substantially the center of the main surface of the first semiconductor chip 1. A plurality of electrode pads 4 are formed on the periphery of the first semiconductor chip 1 so as to surround a region where the second semiconductor chip 2 is mounted. A dam 5 is provided on the main surface of the first semiconductor chip 1 and between the chip mounting area and the electrode pad 4 formation area. The dam 5 is formed in a rectangular frame shape in plan view so as to surround the chip mounting region inside the region where the electrode pad 4 is formed. An underfill material 6 is filled between the first semiconductor chip 1 and the second semiconductor chip 2 inside the dam 5.

  The conventional semiconductor device configured as described above is bonded to the mounting substrate 7 via the adhesive material layer 8 as shown in FIG. 6, and then the electrode pad 4 on the first semiconductor chip 1 and the mounting substrate. 7 is electrically connected to the land 9 on the 7 through a bonding wire 10.

  In recent years, this type of MCM or SIP type semiconductor device has been required to increase the speed of signal processing and reduce the mounting area. That is, the semiconductor device mounted by the wire bonding method shown in FIG. 6 has a problem of securing a mounting area necessary for routing of the bonding wire 10 and a signal transmission delay due to the wiring length of the bonding wire 10.

  Therefore, as schematically shown in FIG. 7, the bump 3 bonded to the second semiconductor chip 2 on the upper layer side and the bump bonded to the mounting substrate 7 on the lower layer side with respect to the first semiconductor chip 1. By forming vias (through electrodes) 11 that connect the layers 12 to each other, it is very advantageous because an increase in signal speed and a reduction in mounting area can be realized at the same time.

  In order to form the through electrode, it is necessary to reduce the thickness of the wafer in order to reduce the processing time and reduce the pitch. Conventionally, back grinding has been performed to reduce the thickness of a wafer. Therefore, as a through electrode formation method, a method is known in which a through electrode is embedded and formed on the wafer surface, and then the back surface of the wafer is ground to expose the terminal surface of the through electrode to the outside (see Patent Document 1 below).

  Further, when the thickness of the wafer is reduced, the wafer is likely to be warped, and handling becomes difficult. Therefore, a support substrate (support substrate) is bonded to the surface of the wafer to enhance the supportability of the wafer. On the other hand, when processing on the substrate to be processed is completed, it is necessary to properly remove the support substrate from the substrate to be processed. .

  As described above, the adhesive that bonds the support substrate and the wafer is required to have a temporary fixability that can withstand the wafer processing process and a peelability after the completion of the wafer processing process. And regarding the peeling technique of an adhesive agent, a method of dissolving and removing the adhesive agent with a solvent, a method of reducing adhesiveness by ultraviolet irradiation, and the like have been proposed (see Patent Documents 2 and 3 below).

  8 to 10 are process cross-sectional views for explaining a semiconductor device manufacturing method as a first conventional example.

  First, as shown in FIG. 8A, a wafer 100 is prepared in which a semiconductor element such as a transistor, an element layer 102 including a wiring 103, an insulating layer 104, and the like are formed on the surface of a substrate body (semiconductor substrate) 101 made of silicon. . An electrode pad 105 that is electrically connected to a part of the wiring layer 103 is formed on the surface of the element layer 102, and an embedded conductor layer 106P that is electrically connected to a part of the wiring 103 is formed on the surface of the substrate body 101. ing.

  Next, as shown in FIG. 8B, solder bumps 107 are formed on the electrode pads 105 on the surface of the element layer 102. Subsequently, as shown in FIG. 8C, an adhesive is applied to the entire surface of the element layer 102 including the solder bumps 107 to form an adhesive material layer 108, and a support substrate 109 is bonded onto the adhesive material layer 108. To do. The support substrate 109 is formed of a glass substrate or a silicon substrate in which a plurality of through holes 109a for supplying a stripping solution are formed in the surface.

  Subsequently, as shown in FIG. 8D, while the wafer 100 is supported by the support substrate 109, the back surface of the substrate body 101 is ground to reduce the thickness of the substrate body 101 to a predetermined thickness and to reduce the thickness of the substrate body 101t. The front end portion 106a of the through electrode (embedded conductor layer) 106 is exposed from the back surface of the electrode. Although simply shown in the figure, the thinned substrate body 101t is actually formed thicker than the element layer 102, and the support substrate 109 is actually formed thicker than the substrate body 101t. In FIG. 8D and subsequent figures, the front and back of the wafer 100 are shown inverted.

  Thereafter, as shown in FIG. 9E, the insulating film 111 is formed on the back surface of the substrate body 101t, and the external connection terminal 112 is formed on the tip portion 106a of the through electrode 106. Then, as shown in FIG. 9F, after the semiconductor chip 113 is flip-chip mounted on the external connection terminal 112, an underfill layer 114 is formed on the mounting portion as shown in FIG. 9G.

  Next, as illustrated in FIG. 10H, the support substrate 109 is peeled from the adhesive material layer 108. The support substrate 109 is peeled off by supplying a peeling liquid (for example, alcohol) through a plurality of through holes 109 a formed in the surface of the support substrate 109 and dissolving the adhesive material layer 108. Then, after the adhesive material layer 108 is dissolved and removed as shown in FIG. 10I, the wafer 100 is separated into chips (dicing) in units of chips, thereby providing a chip-on-chip structure having through electrodes 106 as shown in FIG. 10J. The semiconductor device 100A is manufactured.

  11 to 13 are process cross-sectional views illustrating a method for manufacturing a semiconductor device as a second conventional example. In the figure, portions corresponding to those of the above-described first conventional example are denoted by the same reference numerals, and detailed description thereof is omitted.

  In this conventional example, after the solder bumps 107 are formed on the surface of the wafer 100, the process of bonding the support substrate is the same as that in the first conventional example (FIGS. 11A to 11C). However, in this conventional example, the support substrate 119 is bonded to the surface of the wafer 100 through an adhesive material layer 118 made of an adhesive whose adhesiveness deteriorates when irradiated with ultraviolet rays. It is different from the example. The support substrate 119 is made of a glass substrate that is transparent to ultraviolet rays.

  Thereafter, as in the first conventional example, the substrate body 101 is thinned (FIG. 11D), the external connection terminal 112 is formed (FIG. 12E), the semiconductor chip 113 is mounted (FIG. 12F), and the underfill layer 114 is formed (FIG. FIG. 12G) is performed. Thereafter, the adhesive material layer 118 is irradiated with ultraviolet rays through the support substrate 119, whereby the support substrate 119 is peeled from the wafer 100 (FIG. 13H). Then, by dividing the wafer 100 into chips (dicing), a semiconductor device 100A having a chip-on-chip structure including the through electrode 106 as shown in FIG. 13I is manufactured.

JP 2004-241479 A JP 2003-171624 A JP 2005-191550 A

  As described above, the adhesive material layers 108 and 118 that bond between the wafer 100 and the support substrates 109 and 119 are required to have temporary fixing properties that can withstand the wafer processing process and peelability after the completion of the wafer processing process. In the above-described conventional example, as the adhesive material layers 108 and 118, an adhesive dissolved in an organic solvent or an adhesive whose adhesive strength is reduced by irradiation with ultraviolet rays is used.

  However, these adhesives generally have low heat resistance, and when heated to a temperature higher than the heat resistant temperature, the adhesiveness is reduced or the peelability is impaired, so that the wafer processing process has a temperature higher than the heat resistant temperature of the adhesive material layers 108 and 118. There is a problem that high temperature treatment cannot be performed.

For example, in the case of an insulating film such as a SiO ₂ film, the higher the film formation temperature, the better the film quality and the better the adhesion with the silicon substrate. Such a high temperature treatment cannot be performed, and a low temperature film formation method such as a low temperature CVD method must be used. Therefore, it is difficult to ensure the reliability of the insulating film 111 in the step of forming the insulating film 111 on the back surface of the substrate body 101t (FIGS. 9E and 12E). Further, in the bonding step of the semiconductor chip 113 (FIGS. 9F and 12F), it is necessary to use a low-temperature solder that melts at a temperature lower than the heat resistant temperature of the adhesive material layers 108 and 118, and there is a restriction on material selection.

  In addition, the above-described adhesive material layers 108 and 118 have not only heat resistance but also low chemical resistance, and there are problems such as restrictions on chemicals and processing methods that can be processed without being damaged by dissolution or deterioration. In particular, the adhesive material layer 108 has low resistance to a resist stripping solution containing a solvent such as PGMEA (propylene glycol monomethyl ether acetate) or ECA (ethyl cellosolve acetate). For this reason, in the patterning process of the insulating film 111 and the process of forming the external connection terminals 112 (FIG. 9E), there are problems such as restrictions on the pattern resist processing method (dipping cannot be performed).

  The present invention has been made in view of the above-described problems, and a substrate processing method capable of properly supporting a substrate without using an adhesive material layer that requires temporary fixing properties and peelability, and capable of properly removing a supporting substrate, and It is an object to provide a method for manufacturing a semiconductor device.

  In solving the above-described problems, the substrate processing method of the present invention processes a substrate to be processed in a state in which one surface of the substrate to be processed is bonded to a support substrate and the substrate to be processed is supported by the support substrate. And a step of removing the support substrate from the substrate to be processed. In the step of bonding the substrate to be processed to the support substrate, solid phase bonding between the metal layers formed on the bonding surfaces of the substrate to be processed and the support substrate is performed. In the step of bonding the substrate to be processed to the support substrate and removing the support substrate from the substrate to be processed, the support substrate is polished and removed.

  In the present invention, the support substrate and the substrate to be processed are bonded by solid phase bonding between metal layers formed on the respective bonding surfaces, and the support substrate is removed by polishing the support substrate. Therefore, an organic adhesive having temporary fixability and peelability, which has been conventionally required, can be eliminated. As a result, a processing process can be performed on the substrate to be processed without being restricted by the heat-resistant temperature and chemical resistance of the adhesive, so that, for example, an insulating film having excellent adhesion and a stable pattern processing of the terminal surface can be performed. It becomes possible.

  In particular, the step of bonding the substrate to be processed to the support substrate includes the step of forming a metal layer made of the same material on each bonding surface of the substrate to be processed and the support substrate, and the surface of these metal layers is activated in a vacuum. Then, a bonding step is included. Thereby, the bonded body of the to-be-processed substrate and the support substrate having the desired bonding strength at room temperature can be obtained. Examples of the surface activation treatment method for the metal layer include irradiation with argon plasma or particle beam in a vacuum. The metal layer for bonding is not particularly limited. For example, by using a good conductor such as copper or gold, the metal layer can be used as a wiring layer after the support substrate is removed.

  In addition, by using the substrate processing method according to the present invention described above, a semiconductor device having a chip-on-chip structure in which a through electrode for interlayer connection is formed in a lower semiconductor chip is manufactured with high accuracy and high reliability. Can do.

  That is, in the method for manufacturing a semiconductor device of the present invention, a step of preparing a semiconductor wafer having an external connection terminal formed on one surface, a step of forming a first metal layer over the entire area of one surface of the semiconductor wafer, A step of preparing a support substrate having a second metal layer formed on the entire bonding surface; a step of bonding one surface of the semiconductor wafer to the support substrate via the first and second metal layers; Polishing the other surface and thinning the semiconductor wafer; forming a connection electrode electrically connected to the external connection terminal on the other surface of the semiconductor wafer; and a semiconductor chip on the connection electrode A step of mounting, a step of polishing and removing the supporting substrate, a step of removing the first and second metal layers by etching, and a step of dividing the semiconductor wafer into chips.

  Here, before the step of forming the first metal layer, an insulating material is filled around the external connection terminals to flatten one surface of the semiconductor wafer so that the bonding step with the support substrate is performed properly and stably. Can be done.

  Formation of the through electrode on the semiconductor wafer can be performed during the thinning process in a state where the semiconductor wafer is supported by the support substrate or after the thinning process is performed. As a method for forming a through electrode at the time of the thinning process of a semiconductor wafer, an embedded conductor layer electrically connected to an external connection terminal is formed in advance, and the embedded conductor layer is formed at the time of thinning. Is exposed from the polished surface of the wafer. Then, this terminal surface is processed to form a connection electrode joined to the upper semiconductor chip.

  The support substrate is removed after the semiconductor chip is mounted on the semiconductor wafer. At this time, by polishing the semiconductor chip on the semiconductor wafer to form a pseudo wafer, the support substrate can be stably polished and removed.

  The support substrate is preferably removed by a polishing method, in which the polishing process is terminated before the metal layer is exposed and the remainder is dissolved and removed by etching. In this case, the metal layer functions as an etching stopper layer, and the support substrate can be appropriately removed. Further, the subsequent removal process of the metal layer can be dissolved and removed by etching, but it is not limited to removing the entire metal layer, and the metal layer may be used as a part of the wiring by pattern etching.

  As described above, according to the substrate processing method of the present invention, the substrate to be processed is supported by the support substrate and the support substrate is removed from the substrate to be processed without using an adhesive that requires temporary fixability and peelability. Can be performed properly.

  Further, according to the method for manufacturing a semiconductor device of the present invention, a semiconductor device having a chip-on-chip structure in which through electrodes for interlayer connection are formed can be manufactured with high accuracy and high reliability.

  Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, an example in which the present invention is applied to a method of manufacturing a semiconductor device having a chip-on-chip structure will be described.

  1 to 5 are process cross-sectional views illustrating a method for manufacturing a semiconductor device having a chip-on-chip structure according to an embodiment of the present invention.

  First, as shown in FIG. 1A, a semiconductor wafer in which a semiconductor element such as a transistor, an element layer 22 including a wiring 23, an insulating layer 24, and the like are formed on the surface of a substrate body (semiconductor substrate) 21 made of silicon (hereinafter simply referred to as a semiconductor wafer). “Wafer”) W is prepared. The wafer W corresponds to a “substrate to be processed” according to the present invention.

  A plurality of external connection terminals 25 that are electrically connected to a part of the wiring 23 are arranged on the surface of the element layer 22. The external connection terminal 25 includes, for example, electrode pads arranged on the surface of the element layer 22 and plating bumps formed thereon, and is formed to protrude from the surface of the element layer 22.

In the element layer 22, a buried conductor layer 26P made of, for example, copper is formed in advance. The buried conductor layer 26 </ b> P is formed with a predetermined depth (for example, 150 μm or less) that does not penetrate the substrate body 21, and is electrically connected to the external connection terminal 25 through a part of the wiring 23. The periphery of the buried conductor layer 26P is covered with an insulating film such as SiO ₂ and is electrically insulated from the substrate body 21.

Next, as shown in FIG. 1B, an insulating film 27 is formed on the surface of the element layer 22. The insulating film 27 is made of an insulating material such as a SiO ₂ film formed by CVD, for example, and is formed with a thickness equal to or greater than the thickness of the external connection terminal 25, so that the periphery of the external connection terminal 25 is filled with the insulating film 27. In addition, the upper surface of the external connection terminal 25 is covered with an insulating film 27.

  After the formation of the insulating film 27, as shown in FIG. 1C, the surface of the element layer 22 is subjected to polishing such as a CMP (Chemical Mechanical Polishing) method or an etch back process to flatten the insulating film 27 and the external connection terminal 25. Process. Thereby, the external connection terminals 25 and the insulating film 27 are formed in the same plane, and the external connection terminals 25 are exposed from the surface of the wafer W.

  As another method for forming the external connection terminal 25 and the insulating film 27 in the same plane as described above, a damascene method may be employed. In addition, the external connection terminals 25 and the insulating film 27 may be flattened with a level of accuracy that allows subsequent bonding to the support substrate 29.

  Next, as shown in FIG. 1D, a first bonding metal layer 28 </ b> A is formed on the planarized external connection terminal 25 and insulating film 27 over the entire surface. The first bonding metal layer 28A is for bonding the wafer W to a support substrate 29 described later. The formed first joining metal layer 28 </ b> A is electrically connected to the external connection terminal 25. The constituent material of the first bonding metal layer 28A is not particularly limited, but copper (Cu) is used in the present embodiment, and the first bonding metal layer 28A is formed to have a thickness of about 0.5 μm to 1.0 μm, for example.

  On the other hand, as shown in FIG. 2E, a support substrate 29 having a second bonding metal layer 28B formed on the entire bonding surface is prepared. The second bonding metal layer 28 </ b> B is for bonding to the first bonding metal layer 28 </ b> A formed on the surface of the wafer W. The constituent material of the second bonding metal layer 28B is not particularly limited, but in the present embodiment, the same copper as that of the first bonding metal layer 28A is used, and is formed to have a thickness of about 0.5 μm to 1.0 μm, for example.

  The support substrate 29 is made of a material having a thermal expansion coefficient equivalent to that of the substrate body 21 such as a glass substrate or a silicon substrate. Although the thickness of the support substrate 29 is not particularly limited, it is preferably formed with a thickness that can secure a rigidity that can be handled when the substrate body 21 is thinned, as will be described later. For example, the thickness is 700 μm or more. It is assumed.

  Then, as shown in FIG. 2F, the wafer W and the support substrate 29 are bonded together, and a predetermined bonding load is applied to both the substrates. Thus, the surface of the wafer W is bonded to the support substrate 29 by solid phase bonding of the first and second bonding metal layers 28A and 28B formed on the bonding surfaces. Bonding between the wafer W and the support substrate 29 is performed by surface activated bonding between the first and second bonding metal layers 28A and 28B in a vacuum at room temperature. The first and second bonding metal layers 28 </ b> A and 28 </ b> B function as the metal layer 28 that bonds the wafer W and the support substrate 29 by being integrally bonded with a predetermined bonding load.

  The first and second bonding metal layers 28 </ b> A and 28 </ b> B are formed on the bonding surfaces of the wafer W and the support substrate 29 by sputtering in a reduced-pressure atmosphere, respectively. By forming the first and second metal layers 28 </ b> A and 28 </ b> B by sputtering, the metal layers 28 </ b> A and 28 </ b> B can be formed with high adhesion to the wafer W and the support substrate 29.

  At this time, the surfaces of the first and second metal layers 28A and 28B are oxidized by being released to the atmosphere, and as such, bonding by metal bonding cannot be performed. Therefore, when bonding is performed in vacuum, the surfaces of the metal layers 28A and 28B are activated to remove the oxide film formed on the surfaces, thereby refreshing the surfaces. Stable solid-phase bonding between 28B can be ensured. As the surface activation treatment, for example, etching removal of an oxide film by argon plasma irradiation, ion beam irradiation, or the like is applicable, and can be performed immediately before the bonding step in the same chamber.

  As described above, since the wafer W and the support substrate 29 are fixed using metal bonding between the first and second bonding metal layers 28A and 28B, an organic adhesive that has been conventionally used is used. It is possible to fix the wafer W and the support substrate 29 without any problems, and it is possible to process without being restricted by heat resistance and chemical resistance in the subsequent processes.

  Next, as shown in FIG. 2G, the back surface of the wafer W supported by the support substrate 29 is polished to thin the substrate body 21, and the through electrode 26 (embedded conductor) is formed from the back surface of the thinned substrate body 21t. The tip 26a of the layer 26P) is exposed.

  In this step, for example, the substrate body 21 is polished until the tip portion 26a of the through electrode 26 is exposed from the back surface (polished surface) of the substrate body 21, and then the back surface of the substrate body 21t is subjected to chemical etching to The distal end portion 26a is protruded. In addition, as a grinding | polishing method, well-known polish techniques, such as back surface grinding (BGR) and chemical mechanical polishing (CMP), can be used individually or in combination.

Subsequently, as shown in FIG. 3H, a predetermined insulating process such as forming an insulating film 30 with SiO ₂ or the like is performed on the back surface of the substrate body 21t, and a connection electrode 31 is formed at the tip portion 26a of the through electrode 26. . The connection electrode 31 is electrically connected to the external connection terminal 25 through the through electrode 26 and the wiring 23. The connection electrode 31 can be formed using a wafer level CSP rewiring technique, a bump forming technique, a semiconductor process wiring technique, or the like.

  Next, as shown in FIG. 3I, a plurality of semiconductor chips 32 are mounted on the connection electrodes 31 on the wafer W. The semiconductor chip 32 has a plurality of bumps 33 formed in advance on its mounting surface, and is flip-chip bonded onto the connection electrode 31 via these bumps 36. Thereafter, as shown in FIG. 3I, a step of forming an underfill layer 34 between the wafer W and the semiconductor chip 32 is performed. As the resin material constituting the underfill layer 34, an epoxy-based thermosetting resin used for general flip chip bonding can be used.

  Next, as shown in FIG. 3J, the semiconductor chip 32 is molded on the wafer W to form a pseudo wafer. In this step, the sealing layer 35 is formed on the wafer W, and the mounting interval of the semiconductor chips 32 is filled with the constituent resin of the sealing layer 35 and then flattened. The sealing layer 35 can be formed by, for example, a wafer mold technique used in a wafer level CSP. If necessary, the sealing layer 35 may be polished to reduce the thickness of the semiconductor chip 32.

  By forming the semiconductor chip 32 into a pseudo wafer by using the sealing layer 35 as described above, the subsequent processing process can be handled in a wafer state, so that an existing processing apparatus can be used as it is. Further, the sealing layer 35 is formed so as to fill the level difference between the wafer W and the semiconductor chip 32 and become flat, so that the support substrate 29 is ground and removed without damaging the wafer W and the semiconductor chip 32 in the next process. Can be carried out.

  Subsequently, as shown in FIGS. 4K and 4L, a polishing removal process of the support substrate 29 is performed. As a polishing method, BGR, CMP, or a combination thereof can be used. Here, it is of course possible to remove the entire thickness of the support substrate 29 by polishing, but in this embodiment, the removal process of the support substrate 29 is a process of thinning the support substrate 29 by polishing (FIG. 4K). And the step of dissolving and removing the thinned support substrate by etching (FIG. 4L). Thereby, appropriate removal of the support substrate 29 and uniform thickness of the metal layer 28 can be achieved.

  In this case, by finishing the polishing of the support substrate 29 before the metal layer 28 is exposed (for example, the remaining thickness is about 10 μm), the working time of the dissolution and removal process can be shortened, and the workability can be improved. . In the case where the support substrate 29 is formed of a silicon substrate, hydrofluoric acid or the like is applicable as an etchant used for dissolution and removal, and the metal layer 28 functions as an etching stopper layer.

  Next, a step of removing the bonding metal layer 28 exposed to the outside by removing the support substrate 29 is performed. The metal layer 28 is not limited to removing all of the metal layer 28. In the present embodiment, by using the metal layer 28 as a wiring material, the metal layer 28 is pattern-etched into a predetermined conductor shape communicating with the external connection terminal 25 as shown in FIG. 4M. In particular, since the metal layer 28 is made of copper, it can be suitably used as a wiring material. As a pattern etching processing method of the metal layer 28, an etching method used for rewiring formation such as a wafer level CSP can be applied.

  After pattern etching of the metal layer 28, an external connection electrode 36 electrically connected to the external connection terminal 25 is formed by forming a Ni (nickel) / Au (gold) plating layer by an electroless plating method. . Then, as shown in FIG. 4N, solder bumps 37 are formed on the external connection electrodes 36. As a method for forming the solder bump 37, it can be formed by a general plating method or printing method. The formation of the solder bumps 37 is arbitrary, and the formation of the solder bumps 37 may be omitted depending on the specifications.

  Finally, as shown in FIG. 5, the wafer W is divided into chips, and a semiconductor device 20 having a three-dimensional structure of a first semiconductor chip 38 on the lower layer side and a second semiconductor chip 32 on the upper layer side. Is made.

  The semiconductor device 20 is provided between the second semiconductor chip 32 and the first semiconductor chip 38 and between the second semiconductor chip 32 and the solder bump 37 via the through electrode 26 formed in the first semiconductor chip 38. Is electrically connected. In addition, an exterior package is configured by the sealing layer 35 that covers the periphery of the second semiconductor chip 32.

  As described above, according to the present embodiment, the bonding of the wafer W and the support substrate 29 is performed by solid-phase bonding between the metal layers 28A and 28B formed on each bonding surface. Since the removal is performed mainly by polishing the support substrate 29, it is possible to eliminate the need for an organic adhesive having temporary fixability and peelability, which has been conventionally required. Thereby, since the processing process for the wafer W can be performed without being restricted by the heat-resistant temperature and chemical resistance of the adhesive, for example, the formation of the insulating film 30 having excellent adhesion and the stable pattern processing of the connection electrode 31 are possible. Is possible.

  As mentioned above, although embodiment of this invention was described, of course, this invention is not limited to this, A various deformation | transformation is possible based on the technical idea of this invention.

  For example, in the above embodiment, the example in which the present invention is applied to the manufacture of the semiconductor device 20 having the chip-on-chip structure has been described. However, the present invention is not limited to this, and the thinning process by the back surface grinding of the substrate to be processed at the wafer level. The present invention can also be applied to the element mounting process on the substrate to be processed.

  In the above embodiment, the manufacture of the semiconductor device in which the first and second semiconductor chips are stacked has been described as an example. However, the number of stacked semiconductor chips may be further increased.

It is process sectional drawing explaining the manufacturing method of the semiconductor device by embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device by embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device by embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device by embodiment of this invention. It is sectional drawing which shows schematic structure of the semiconductor device by embodiment to this invention. It is sectional drawing which shows typically the example of 1 structure of the semiconductor device of a chip-on-chip structure. It is sectional drawing which shows typically the example of another structure of the semiconductor device of a chip on chip structure. It is process sectional drawing explaining the manufacturing method of the semiconductor device by a 1st prior art example. It is process sectional drawing explaining the manufacturing method of the semiconductor device by a 1st prior art example. It is process sectional drawing explaining the manufacturing method of the semiconductor device by a 1st prior art example. It is process sectional drawing explaining the manufacturing method of the semiconductor device by the 2nd prior art example. It is process sectional drawing explaining the manufacturing method of the semiconductor device by the 2nd prior art example. It is process sectional drawing explaining the manufacturing method of the semiconductor device by the 2nd prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 20 ... Semiconductor device, 32, 38 ... Semiconductor chip, 21, 21t ... Substrate body, 22 ... Element layer, 23 ... Wiring, 24 ... Insulating layer, 25 ... External connection terminal, 26 ... Through electrode, 26P ... Embedded conductor layer 27 ... insulating film, 28 ... metal layer, 28A ... first bonding metal layer, 28B ... second bonding metal layer, 29 ... support substrate, 30 ... insulating film, 31 connection electrode, 35 ... sealing layer, 36 ... External connection electrode, 37 ... Solder bump, W ... Wafer

Claims (11)

Bonding one surface of the substrate to be processed to a support substrate;
Processing the target substrate in a state where the target substrate is supported by the support substrate;
Removing the support substrate from the substrate to be processed.
In the step of bonding the substrate to be processed to the support substrate, the substrate to be processed and the support substrate are bonded to the support substrate by solid phase bonding between the metal layers formed on the bonding surfaces of the substrate to be processed and the support substrate,
In the step of removing the support substrate from the substrate to be processed, the support substrate is removed by polishing. The step of bonding the substrate to be processed to the support substrate includes:
The method includes a step of forming a metal layer made of the same material on each joint surface of the substrate to be processed and the support substrate, and a step of bonding the surface of the metal layer after activation processing in vacuum. The substrate processing method according to claim 1. The step of removing the support substrate from the substrate to be processed includes:
2. The method according to claim 1, comprising a step of thinning the support substrate by polishing, a step of dissolving and removing the thinned support substrate, and a step of removing part or all of the metal layer. The substrate processing method as described. The substrate processing method according to claim 1, wherein the step of processing the substrate to be processed includes a step of thinning the other surface of the substrate to be processed by polishing. The substrate processing method according to claim 1, wherein the step of processing the substrate to be processed includes a step of mounting an element on the other surface of the substrate to be processed. Preparing a semiconductor wafer having external connection terminals formed on one surface;
Forming a first metal layer over the entire area of one surface of the semiconductor wafer;
Preparing a support substrate having a second metal layer formed on the entire bonding surface;
Bonding one surface of the semiconductor wafer to the support substrate via the first and second metal layers;
Polishing the other surface of the semiconductor wafer to thin the semiconductor wafer;
Forming a connection electrode electrically connected to the external connection terminal on the other surface of the semiconductor wafer;
Mounting a semiconductor chip on the connection electrode;
Polishing and removing the support substrate;
Etching away the first and second metal layers;
And a step of dividing the semiconductor wafer into chips. A method for manufacturing a semiconductor device, comprising: The step of flattening one surface of the semiconductor wafer by filling the periphery of the external connection terminal with an insulating material before the step of forming the first metal layer. Semiconductor device manufacturing method. An embedded conductor layer electrically connected to the external connection terminal is formed in the semiconductor wafer in advance, and at the same time as the semiconductor wafer is thinned, the tip of the embedded conductor layer is placed on the semiconductor wafer. The method for manufacturing a semiconductor device according to claim 6, wherein the connection electrode is formed so as to be exposed from the other surface of the semiconductor device. The method for manufacturing a semiconductor device according to claim 6, further comprising a step of molding the semiconductor chip on the semiconductor wafer to form a pseudo wafer after the semiconductor chip is mounted. 7. The step of etching and removing the first and second metal layers includes pattern etching the first and second metal layers into a predetermined conductor shape communicating with the external connection terminal. A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 10, further comprising forming a solder bump on the first and second metal layers that have been subjected to pattern etching.

Images