JP4443549B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device having a metal film connected to a metal pad formed on a semiconductor substrate through an opening formed from the back surface of the semiconductor substrate.

  Conventionally, there is a BGA (Ball Grid Array) type semiconductor device as a kind of surface mount type semiconductor device. This is done by arranging a plurality of ball-shaped conductive terminals made of a metal member such as solder in a grid pattern on one main surface of the package substrate, and bonding it to a semiconductor chip mounted on the other main surface of the substrate. To do. And when incorporating in an electronic device, each conductive terminal is heat-welded to the wiring pattern on a printed circuit board, and a semiconductor chip and the external circuit mounted on a printed circuit board are electrically connected.

  Such a BGA type semiconductor device has a larger number of connection terminals than other surface mount type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side surface of the semiconductor device. It can be installed, and it is known that downsizing is advantageous.

  In recent years, this BGA type semiconductor device has been incorporated into the field of CCD image sensors, and is used as an image sensor chip for a digital camera mounted on a mobile phone that is strongly demanded for miniaturization.

  Further, three-dimensional mounting technology using wafer level CSP (Chip Size Package) or silicon (Si) penetration technology has been attracting attention. In these techniques, a method of stacking chips after stacking layers and then penetrating Si, or passing Si wafers through Si from the surface and then stacking them has been studied.

  However, the conventional three-dimensional mounting technology performs processing such as Si penetration from the surface to form a copper (Cu) via hole, so that CMP (Chemical Mechanical Polishing) processing is necessary on the surface side, or Cu via formation Since rewiring for connecting the Cu via and the pad later is necessary, the number of manufacturing steps increases. Therefore, the semiconductor device itself is also expensive.

Therefore, a method for manufacturing a semiconductor device according to the present invention includes a step of preparing a semiconductor substrate having a metal pad formed on the surface side, and bonding the semiconductor substrate and a support substrate supporting the semiconductor substrate through an organic film. A step of forming an opening from the back surface of the semiconductor substrate; a step of forming a metal layer electrically connected to the metal pad through the opening after forming an insulating film on a side wall portion of the opening; The step of dicing from the back surface of the semiconductor substrate to the position of the organic film, and after the dicing , heating the semiconductor substrate to which the support substrate is bonded, thereby melting the organic film, and the semiconductor substrate and the support substrate. And a step of separating.

Moreover, it has the process of forming a conductive terminal on the said metal layer, It is characterized by the above-mentioned.

Furthermore, before the step of forming the opening from the back surface of the semiconductor substrate, the back surface is polished .

Further, as the support substrate, a Si substrate, an oxide film, a glass substrate, or a ceramic substrate is used .

Furthermore, it has a process of forming an electrode connection part on the metal pad .

The semiconductor device may further include a step of stacking the semiconductor device and another semiconductor device .

Furthermore, the step of stacking the semiconductor device and another semiconductor device is characterized in that the electrode connection part of one semiconductor device and the conductive terminal of the other semiconductor device are connected .

  In the present invention, unlike the conventional three-dimensional mounting technique, processing such as Si penetration is performed from the surface and a via hole of copper (Cu) is not formed, and therefore CMP processing is not required on the surface side. In addition, since the rewiring for connecting the Cu via and the pad is not required after the Cu via is formed, the number of manufacturing steps does not increase.

  Further, the support plate and the Si substrate can be easily separated.

  Accordingly, it is possible to provide a semiconductor device that realizes cost reduction.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of a semiconductor device and a method for manufacturing the same according to the invention will be described with reference to the drawings.

First, as shown in FIG. 1A, an oxide film is formed on a silicon wafer (hereinafter referred to as Si substrate) 1 having a thickness of about 600 μm, and a metal (for example, Al) pad 2 is formed on the oxide film. Then, an oxide film 3 having a predetermined thickness made of a SiO ₂ film or a PSG film is formed by plasma CVD so as to cover the Al pad 2. In particular, when flatness is required, the oxide film may be subjected to, for example, CMP polishing. Then, using the photoresist film (not shown) as a mask, the oxide film 3 on the Al pad 2 is etched to expose a part (surface portion) of the Al pad 2. In the present embodiment, the thickness of the oxide film 3 is about 5 μm as a whole.

  Next, as shown in FIG. 1B, a polyimide film is formed on the Al pad 2 and the oxide film 3, and the polyimide film is etched using a photoresist film (not shown) as a mask to form the polyimide film on the Al pad 2. A polyimide film 4 having an opening is formed. Then, after nickel (Ni) 5 and gold (Au) 6 are formed in the opening, copper (Cu) is plated thereon and Cu 7 is embedded. Further, Au may be plated on Cu7 for preventing corrosion of Cu7. In the present embodiment, the film thickness of the conductive member (Ni, Au, Cu, Au) embedded in the opening is about 25 μm as a whole.

  Here, when this process is employed in a CCD image sensor, the polyimide film 4 needs to be formed using a screen printing method, such as a transparent polyimide film or a transparent glass epoxy resin.

  Furthermore, if the present process is applied to a CSP process that is not used in a three-dimensional process, it is not necessary to form an opening, and the entire surface of the polyimide film 4 may be applied.

  Further, as shown in FIG. 8A, TiW21 (or Cu may be formed on TiW) is formed on the oxide film 3 including the Al pad 2 and patterned to a predetermined pattern. . A so-called rewiring structure in which Cu7A (Au) is formed via the polyimide film 4A may be employed.

  Subsequently, as shown in FIG. 2A, an insulating film 10 is pasted on the polyimide film 4 including the Cu7 (Au), and the support plate 11 and the Si substrate 1 side are pasted through the film 10.

  Here, the support plate 11 is a support for preventing the Si substrate 1 from cracking or the like during BG (back grinding) of the Si substrate 1 to be described later. For example, the Si substrate, oxide film (glass substrate), ceramic, etc. Is used. In the present embodiment, the film thickness necessary for the support is about 400 μm.

  The film 10 employs an organic film soluble in acetone for the purpose of improving workability in the process of separating the Si substrate 1 and the support plate 11 described later. In this embodiment, the film 10 has a thickness of about 400 μm.

  Furthermore, the film 10 is sealed and hardened by filling the outer peripheral portion of the film 10 with an epoxy resin 12 as shown in FIG. This prevents infiltration of chemicals such as organic solvents during various operations.

  If the back grind film thickness in the BG process of the Si substrate 1 is small, the process of attaching the support plate 11 can be omitted.

  Next, as shown in FIG. 3A, the Si substrate 1 side can be BG-processed to reduce the thickness of the Si substrate 1 to about 10 to 100 μm. At this time, the support plate 11 supports the Si substrate 1 during the BG process. Then, an oxide film 13 of about 0.01 μm is formed on the back side of the Si substrate 1 subjected to the BG treatment. Instead of the oxide film 13, an organic insulator made of a silicon nitride film or polyimide may be formed. Furthermore, since it does not depend on the flatness on Cu in the BG process, back grinding can be performed as it is, and workability is good.

  Further, as shown in FIG. 3B, the oxide film 13 and the Si substrate 1 are etched using a photoresist film (not shown) as a mask to form an opening 14. Subsequently, as shown in FIG. 4A, the oxide film 3 exposed from the opening 14 is etched to expose the Al pad 2. Then, an oxide film is formed by CVD so as to cover the oxide film 13 including the Al pad 2 in the opening 14a, and the oxide film is anisotropically etched to form a sidewall on the opening 14a. The sidewall spacer film 15 is formed by leaving the oxide film. Note that the CVD film forming temperature for the oxide film is preferably as low as about 200 ° C. Further, the sidewall spacer film 15 may be formed using a silicon nitride film.

  Next, as shown in FIG. 4B, a barrier film 16 such as titanium nitride (TiN) or tantalum nitride (TaN) is formed by sputtering in the opening 14a through the sidewall spacer film 15, and the barrier film is formed. Cu 17 is embedded in the opening 14 a through 16. In this step, first, a Cu seed and Cu plating treatment is performed on the barrier film 16, and the Cu is annealed. And the said Cu is embed | buried in the opening part 14a. Here, when flatness is particularly required, the Cu is subjected to CMP polishing.

  Further, as shown in FIG. 5A, a solder mask 18 having an opening that is somewhat wider than the opening size of the opening 14a in which the Cu 17 is embedded is formed on the Cu 17, and the A solder paste 19 is formed on the Cu 17 by screen printing a solder paste on the opening and reflowing the solder paste. In the present embodiment, as the solder mask 18, a polyimide film made of Rica coat that can be imidized at 200 ° C. is used.

  As shown in FIG. 8B, an Al film 31 and a Ni film (Au film) 32 are formed on the oxide film 13 including the Cu 17 and patterned to have a predetermined pattern. And you may employ | adopt the structure which forms 19A of solder balls via the solder mask 18A.

  Subsequently, as shown in FIG. 5B, the Si substrate 1 side is diced to a position reaching the film 10.

  Then, by immersing the Si substrate 1 in an acetone solution tank (not shown), acetone enters from the dicing line (D) and dissolves the film 10 as shown in FIG. Therefore, the Si substrate 1 (each chip) and the support plate 11 are automatically separated, and a single CSP chip 20 as shown in FIG. 6A is completed.

  As described above, in the present embodiment, since the Si substrate 1 and the support plate 11 are bonded together using the organic film 10 that dissolves in acetone, after dicing, the both can be simply performed by immersing the Si substrate 1 in acetone. The workability is good.

  Further, instead of the film 10, a film having a weak adhesive force may be used to physically peel the chip after dicing. Furthermore, when transparent glass is used as the support plate 11, a UV tape is applied as the organic film 10, UV irradiation is performed after dicing, and the chip is peeled off.

  In addition, after dicing, for example, by applying heat from the back surface of the wafer with a hot plate, the organic film (film 10) sandwiched between the wafer and the support plate 11 is melted and softened to peel off both. good. At this time, when the film 10 is an organic film that is soluble in acetone, the film 10 is melted by heating at about 200 ° C., and when a polyimide film is used, the film 10 is heated at about 400 ° C.

  As another form of peeling the Si substrate 1 and the support plate 11, there is a method in which the epoxy resin at the edge is rotated with the wafer lengthwise before dicing and the outer periphery is immersed in a chemical such as acid. There is also a method of separating the blade by putting it in an epoxy resin at the edge between the wafer and the chip. And after both methods, a BG tape is stuck and it dices.

  Then, as shown in FIG. 7, the CSP chip 20 is bonded (laminated) with Cu7 (Au) and the solder ball 19 by metal contact with Cu7 (Au), thereby enabling three-dimensional mounting (any number of layers). If the chip size is the same (memory or the like), the capacity can be increased.

It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of other embodiment of this invention.

Claims (7)

Prepare a semiconductor substrate with metal pads on the surface side,
Bonding the semiconductor substrate and a support substrate supporting the semiconductor substrate through an organic film;
Forming an opening from the back surface of the semiconductor substrate;
Forming an insulating film on the side wall of the opening and then forming a metal layer electrically connected to the metal pad through the opening;
Dicing from the back surface of the semiconductor substrate to the organic film position;
A method of manufacturing a semiconductor device comprising: a step of heating the semiconductor substrate to which the support is bonded after dicing, thereby melting the organic film and separating the semiconductor substrate and the support substrate. . The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a conductive terminal on the metal layer. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the back surface is polished before the step of forming the opening from the back surface of the semiconductor substrate.   The method for manufacturing a semiconductor device according to claim 1, wherein an Si substrate, an oxide film, a glass substrate, or a ceramic substrate is used as the support substrate.   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming an electrode connection portion on the metal pad.   A method for manufacturing a stacked semiconductor device, comprising a step of stacking the semiconductor device according to claim 1 and another semiconductor device.   The step of stacking the semiconductor device according to any one of claims 1 to 5 with another semiconductor device includes the electrode connection portion of one semiconductor device and the conductive terminal of the other semiconductor device. A method for manufacturing a stacked semiconductor device, characterized in that: