JP4212293B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4212293B2
JP4212293B2 JP2002111571A JP2002111571A JP4212293B2 JP 4212293 B2 JP4212293 B2 JP 4212293B2 JP 2002111571 A JP2002111571 A JP 2002111571A JP 2002111571 A JP2002111571 A JP 2002111571A JP 4212293 B2 JP4212293 B2 JP 4212293B2
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film
semiconductor device
manufacturing
semiconductor wafer
support
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JP2003309221A5 (en
JP2003309221A (en
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崇 野間
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
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    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2225/06503—Stacked arrangements of devices
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置の製造方法に関し、更に言えば、ボール状の導電端子を有するＢＧＡ（Ball Grid Array）型の半導体装置の製造方法に関する。
【０００２】
【従来の技術】
従来より表面実装型の半導体装置の一種としてＢＧＡ型の半導体装置がある。これは、半田等の金属部材から成るボール状の導電端子をパッケージ基板一主面上に格子状に複数配列し、基板の他の主面上に搭載される半導体チップとボンディングしてパッケージングするものである。そして、電子機器に組み込まれる際には、各導電端子をプリント基板上の配線パターンに熱溶着し、半導体チップとプリント基板上に搭載される外部回路とを電気的に接続する。
【０００３】
このようなＢＧＡ型の半導体装置は、半導体装置の側面に突出したリードピンを有するＳＯＰ（Small Outline Package）やＱＦＰ(Quad Flat Package)等の他の表面実装型の半導体装置に比べ多数の接続端子を設置することができ、小型化が有利なものとして知られている。
【０００４】
近年において、このＢＧＡ型の半導体装置がＣＣＤイメージセンサの分野にも取り入れられ、小型化の要望が強い携帯電話機に搭載されるデジタルカメラのイメージセンサチップとして用いられている。
【０００５】
また、ウエハレベルのＣＳＰ（Chip Size Package）やシリコン（Ｓｉ）貫通技術を用いた３次元実装技術が注目されてきている。これらの技術は、チップを何層にも貼り合わせた後、Ｓｉを貫通させたり、Ｓｉウエハを表面からＳｉ貫通させた後、積み上げる方法等が研究されている。
【０００６】
【発明が解決しようとする課題】
しかし、従来の３次元実装技術は、表面からＳｉ貫通等の加工を行い、銅（Ｃｕ）のビアホールを形成するため、表面側にＣＭＰ（Chemical Mechanical Polishing）処理が必要であったり、Ｃｕビア形成後に当該Ｃｕビアとパッドとを繋ぐための再配線が必要であるため、製造工数が多くなってしまう。
【０００７】
【課題を解決するための手段】
そこで、本発明の半導体装置の製造方法上記課題に鑑み、表面側に金属パッドが形成された半導体ウエハを準備し、前記半導体ウエハの前記金属パッドが形成された表面側に対して、当該半導体ウエハを支持する支持体を溶液に溶ける有機膜から成るフィルムを介して貼り合わせる工程と、前記支持体が貼り合わされた前記半導体ウエハの裏面から前記金属パッドまで貫通する開口を形成する工程と、前記開口の側壁部に絶縁膜を形成した後に、当該開口内に金属層を形成する工程と、前記支持体が貼り合わされた前記半導体ウエハの裏面から前記フィルムまでダイシングする工程と、前記半導体ウエハと前記支持体とを分離する工程とを有することを特徴とするものである。
【０００８】
また、前記ウエハと当該ウエハを支持する支持体とをフィルムを介して貼り合わせる工程が、前記ウエハと前記支持体の外径よりも小さい外径を有するフィルムを前記ウエハと前記支持体とで挟んだ状態で、その周端部のみエポキシ樹脂を用いて貼り合わせる工程であることを特徴とするものである。
【００１０】
また、前記フィルムが、粘着性を有するフィルムであることを特徴とするものである。
【００１２】
そして、前記金属層上に電極を形成する工程が、当該金属層上に金属配線を形成し、当該金属配線上に電極を形成する工程を有することを特徴とするものである。
【００１３】
【発明の実施の形態】
以下、本発明の半導体装置の製造方法に係る一実施形態について図面を参照しながら説明する。
【００１４】
先ず、図１（ａ）に示すようにおよそ６００μｍの膜厚のシリコンウエハ（以下、Ｓｉ基板）１上に酸化膜が形成され、当該酸化膜上に金属（例えば、Ａｌ）パッド２が形成され、当該Ａｌパッド２を被覆するようにプラズマＣＶＤ法によるＳｉＯ2膜またはＰＳＧ膜から成る所定膜厚の酸化膜３を形成する。尚、特に平坦性を必要とする場合には酸化膜を例えばＣＭＰ研磨等しても良い。そして、不図示のフォトレジスト膜をマスクにＡｌパッド２上の酸化膜３をエッチングして当該Ａｌパッド２の一部（表面部）を露出させる。尚、本実施形態では、前記酸化膜３の膜厚は、全体でおよそ５μｍ程度としている。
【００１５】
次に、図１（ｂ）に示すように前記Ａｌパッド２及び酸化膜３上にポリイミド膜を形成し、当該ポリイミド膜を不図示のフォトレジスト膜をマスクにエッチングして前記Ａｌパッド２上に開口部を有するポリイミド膜４を形成する。そして、前記開口部内にニッケル（Ｎｉ）５、金（Ａｕ）６を形成した後に、その上に銅（Ｃｕ）メッキしてＣｕ７を埋め込む。また、当該Ｃｕ７上に当該Ｃｕ７の腐食防止用としてＡｕをメッキ形成しても良い。尚、本実施形態では、前記開口部内に埋設された導電部材（Ｎｉ，Ａｕ，Ｃｕ，Ａｕ）の膜厚は、全体でおよそ２５μｍ程度としている。
【００１６】
ここで、本プロセスが、ＣＣＤイメージセンサに採用される場合には、前記ポリイミド膜４は透明性のポリイミド膜または透明ガラスエポキシ樹脂等をスクリーン印刷法を用いて形成する必要がある。
【００１７】
更に言えば、本プロセスを３次元プロセスに用いないＣＳＰプロセスに適用するものである場合には、開口部を形成する必要はなく、ポリイミド膜４の全面塗布で構わない。
【００１８】
また、図８（ａ）に示すように前記Ａｌパッド２上を含む酸化膜３上にＴｉＷ２１（もしくはＴｉＷ上にＣｕを形成しても良い。）を形成し、所定パターンと成るようにパターニングする。そして、ポリイミド膜４Ａを介してＣｕ７Ａ（Ａｕ）を形成する、いわゆる再配線構造を採用しても良い。
【００１９】
続いて、図２（ａ）に示すように前記Ｃｕ７（Ａｕ）上を含むポリイミド膜４上に絶縁フィルム１０を貼り、当該フィルム１０を介して支持板１１と前記Ｓｉ基板１側を貼り合わせる。
【００２０】
ここで、前記支持板１１は、後述するＳｉ基板１のＢＧ（バックグラインド）時に、Ｓｉ基板１の割れ等を防止するための支持体で、例えばＳｉ基板や酸化膜（ガラス基板）やセラミック等を利用している。尚、本実施形態では、支持体として必要な膜厚として、およそ４００μｍ程度としている。
【００２１】
また、前記フィルム１０は、後述するＳｉ基板１と支持板１１との分離工程における作業性向上を図る目的で、アセトンに溶ける有機膜を採用している。尚、本実施形態では、フィルム１０の膜厚をおよそ４００μｍ程度としている。
【００２２】
更に、当該フィルム１０の外周部には、図２（ｂ）に示すようにエポキシ樹脂１２を充填することで、当該フィルム１０を密封し、固めている。これにより、各種作業中における有機溶媒等の薬液の侵入を防止している。
【００２３】
尚、Ｓｉ基板１のＢＧ工程におけるバックグラインド膜厚が少ない場合には、支持板１１を貼り付ける工程は省略できる。
【００２４】
次に、図３（ａ）に示すようにＳｉ基板１側をＢＧ処理して、当該Ｓｉ基板１の膜厚をおよそ１０〜１００μｍ程度まで薄膜化できる。このとき、前記支持板１１が、ＢＧ工程時にＳｉ基板１を支持する。そして、ＢＧ処理したＳｉ基板１の裏面側におよそ０．０１μｍ程度の酸化膜１３を形成する。尚、前記酸化膜１３の代わりにシリコン窒化膜やポリイミドから成る有機系絶縁物を形成しても良い。更に言えば、前記ＢＧ工程において、Ｃｕ上の平坦性に左右されないため、そのままバックグラインド可能であり、作業性が良い。
【００２５】
更に、図３（ｂ）に示すように不図示のフォトレジスト膜をマスクに前記酸化膜１３及びＳｉ基板１をエッチングして開口部１４を形成する。続いて、図４（ａ）に示すように前記開口部１４から露出した酸化膜３をエッチングして、前記Ａｌパッド２を露出させる。そして、開口部１４ａ内の前記Ａｌパッド２上を含む酸化膜１３上を被覆するようにＣＶＤ法による酸化膜を形成し、当該酸化膜を異方性エッチングして開口部１４ａの側壁部に酸化膜を残膜させてサイドウォールスペーサ膜１５を形成する。尚、酸化膜のＣＶＤ成膜処理温度は、２００℃程度の低温度が良い。また、シリコン窒化膜を用いてサイドウォールスペーサ膜１５を形成しても良い。
【００２６】
次に、図４（ｂ）に示すように前記開口部１４ａ内にサイドウォールスペーサ膜１５を介して窒化チタン（ＴｉＮ）または窒化タンタル（ＴａＮ）等のバリア膜１６をスパッタ形成し、当該バリア膜１６を介して前記開口部１４ａ内にＣｕ１７を埋設する。尚、本工程では、先ずバリア膜１６上にＣｕシード、Ｃｕメッキ処理を施し、当該Ｃｕをアニール処理する。そして、当該Ｃｕを開口部１４ａ内に埋設させている。ここで、平坦性を特に必要とする場合は、当該ＣｕをＣＭＰ研磨する。
【００２７】
更に、図５（ａ）に示すように前記Ｃｕ１７上に、当該Ｃｕ１７が埋設された開口部１４ａの開口サイズよりも幾分広い開口を有するソルダーマスク１８を形成し、当該マスク１８を介して当該開口上に半田ペーストをスクリーン印刷し、当該半田ペーストをリフロー処理することで、Ｃｕ１７上に半田ボール１９を形成する。尚、本実施形態では、ソルダーマスク１８として、２００℃でイミド化可能なリカコートから成るポリイミド膜を用いている。
【００２８】
尚、図８（ｂ）に示すように前記Ｃｕ１７上を含む酸化膜１３上にＡｌ膜３１及びＮｉ膜（Ａｕ膜）３２を形成し、所定パターンと成るようにパターニングする。そして、ソルダーマスク１８Ａを介して半田ボール１９Ａを形成する構造を採用しても良い。
【００２９】
続いて、図５（ｂ）に示すように前記Ｓｉ基板１側を前記フィルム１０に到達する位置までダイシングする。
【００３０】
そして、不図示のアセトン溶液槽内に当該Ｓｉ基板１を浸すことで、図６（ｂ）に示すように前記ダイシングライン（Ｄ）からアセトンが侵入し、前記フィルム１０を溶解する。従って、前記Ｓｉ基板１（各チップ）と支持板１１とが自動的に分離され、図６（ａ）に示すような単体のＣＳＰチップ２０が完成する。
【００３１】
このように本実施形態では、アセトンに溶解する有機系のフィルム１０を用いてＳｉ基板１と支持板１１とを貼り合わせているため、ダイシング後に、Ｓｉ基板１をアセトンに浸すだけで両者を簡単に分離することができ、作業性が良い。
【００３２】
また、前記フィルム１０の代わりに粘着力の弱いフィルムを用いて、ダイシング後に、物理的にチップを剥がすものであっても良い。更に言えば、支持板１１として透明ガラスを用いる場合には、有機系フィルム１０としてＵＶテープを貼り、ダイシング後にＵＶ照射をし、チップを剥がせば良い。
【００３３】
加えて、ダイシングした後に、例えばウエハの裏面からホットプレートで熱を加えて、ウエハと支持基板１１で挟まれた有機膜（フィルム１０）を溶かして軟化させることで両者を剥がすものであっても良い。このとき、フィルム１０がアセトンに溶ける有機膜であるときは、２００℃程度の加熱で、ポリイミド膜を利用した場合では４００℃程度の加熱で当該フィルム１０は溶ける。
【００３４】
Ｓｉ基板１と支持板１１とを剥がす別形態としては、ダイシング前に、エッジのエポキシ樹脂を、ウエハを縦にして回転させ、外周だけ酸などの薬品に浸して剥がす方法もある。又、刃物をウエハとチップの間のエッジのエポキシ樹脂に入れて切り離す方法もある。そして、両方法の後、ＢＧテープを貼ってダイシングする。
【００３５】
そして、図７に示すように前記単体のＣＳＰチップ２０をＣｕ７（Ａｕ）と半田ボール１９とを金属密着でＣＳＰチップ２０同士を密着（積層）させることで、３次元実装が（何層でも）可能となり、チップサイズの同じもの（メモリ等）であれば大容量化が図れる。
【００３６】
【発明の効果】
本発明では、従来の３次元実装技術のように表面からＳｉ貫通等の加工を行い、銅（Ｃｕ）のビアホールを形成するため、表面側にＣＭＰ（Chemical Mechanical Polishing）処理を必要としない。また、Ｃｕビア形成後に当該Ｃｕビアとパッドとを繋ぐための再配線が不要であるため、製造工数が増大することがない。
【００３７】
更に言えば、Ｃｕ上の平坦性に左右されないため、そのままバックグラインド可能である。
【００３８】
また、支持板１１とＳｉ基板１とは、貼り合わせた後にＢＧ（バックグラインド）及びその後の処理をしているため、チップの膜厚は必要に応じて薄くできる。
【図面の簡単な説明】
【図１】本発明の一実施形態の半導体装置の製造方法を示す断面図である。
【図２】本発明の一実施形態の半導体装置の製造方法を示す断面図である。
【図３】本発明の一実施形態の半導体装置の製造方法を示す断面図である。
【図４】本発明の一実施形態の半導体装置の製造方法を示す断面図である。
【図５】本発明の一実施形態の半導体装置の製造方法を示す断面図である。
【図６】本発明の一実施形態の半導体装置の製造方法を示す断面図である。
【図７】本発明の一実施形態の半導体装置の製造方法を示す断面図である。
【図８】本発明の他の実施形態の半導体装置の製造方法を示す断面図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a BGA (Ball Grid Array) type semiconductor device having ball-shaped conductive terminals.
[0002]
[Prior art]
Conventionally, there is a BGA type semiconductor device as a kind of surface mount type semiconductor device. In this method, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a grid pattern on one main surface of a package substrate, and bonded to a semiconductor chip mounted on the other main surface of the substrate for packaging. Is. And when incorporating in an electronic device, each conductive terminal is heat-welded to the wiring pattern on a printed circuit board, and a semiconductor chip and the external circuit mounted on a printed circuit board are electrically connected.
[0003]
Such a BGA type semiconductor device has a larger number of connection terminals than other surface mount type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side surface of the semiconductor device. It can be installed , and it is known that downsizing is advantageous.
[0004]
In recent years, this BGA type semiconductor device has been incorporated into the field of CCD image sensors, and is used as an image sensor chip for a digital camera mounted on a mobile phone that is strongly demanded for miniaturization.
[0005]
Further, three-dimensional mounting technology using wafer level CSP (Chip Size Package) and silicon (Si) penetration technology has been attracting attention. In these techniques, a method of stacking chips after stacking layers and then penetrating Si, or passing Si wafers through Si from the surface and then stacking them has been studied.
[0006]
[Problems to be solved by the invention]
However, the conventional three-dimensional mounting technology performs processing such as Si penetration from the surface to form a copper (Cu) via hole, so that CMP (Chemical Mechanical Polishing) processing is necessary on the surface side, or Cu via formation Since rewiring for connecting the Cu via and the pad later is necessary, the number of manufacturing steps increases.
[0007]
[Means for Solving the Problems]
Accordingly, in view of the above-described problem, a method for manufacturing a semiconductor device according to the present invention provides a semiconductor wafer having a metal pad formed on the surface side, and the semiconductor wafer is formed on the surface side of the semiconductor wafer on which the metal pad is formed. Bonding a support that supports the substrate through a film made of an organic film that dissolves in the solution, forming an opening that penetrates from the back surface of the semiconductor wafer to which the support is bonded to the metal pad, and the opening Forming a metal layer in the opening, forming a metal layer in the opening, dicing from the back surface of the semiconductor wafer to which the support is bonded to the film, the semiconductor wafer and the support And a step of separating the body.
[0008]
Further, the wafer and the step of bonding via a support film for supporting the wafer, across the film having a smaller outer diameter than the outer diameter of the support and the wafer and the support and the wafer In this state, only the peripheral end portion is bonded using an epoxy resin.
[0010]
Further, the film is a film having adhesiveness.
[0012]
The step of forming an electrode on the metal layer includes a step of forming a metal wiring on the metal layer and forming an electrode on the metal wiring.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment according to a method of manufacturing a semiconductor device of the present invention will be described with reference to the drawings.
[0014]
First, as shown in FIG. 1A, an oxide film is formed on a silicon wafer (hereinafter referred to as Si substrate) 1 having a thickness of about 600 μm, and a metal (for example, Al) pad 2 is formed on the oxide film. Then, an oxide film 3 having a predetermined thickness made of a SiO 2 film or a PSG film is formed by plasma CVD so as to cover the Al pad 2. In particular, when flatness is required, the oxide film may be subjected to, for example, CMP polishing. Then, using the photoresist film (not shown) as a mask, the oxide film 3 on the Al pad 2 is etched to expose a part (surface portion) of the Al pad 2. In the present embodiment, the thickness of the oxide film 3 is about 5 μm as a whole.
[0015]
Next, as shown in FIG. 1B, a polyimide film is formed on the Al pad 2 and the oxide film 3, and the polyimide film is etched using a photoresist film (not shown) as a mask to form the polyimide film on the Al pad 2. A polyimide film 4 having an opening is formed. Then, after nickel (Ni) 5 and gold (Au) 6 are formed in the opening, copper (Cu) is plated thereon and Cu 7 is embedded. Further, Au may be plated on Cu7 for preventing corrosion of Cu7. In the present embodiment, the film thickness of the conductive member (Ni, Au, Cu, Au) embedded in the opening is about 25 μm as a whole.
[0016]
Here, when this process is employed in a CCD image sensor, the polyimide film 4 needs to be formed using a screen printing method, such as a transparent polyimide film or a transparent glass epoxy resin.
[0017]
Furthermore, if the present process is applied to a CSP process that is not used in a three-dimensional process, it is not necessary to form an opening, and the entire surface of the polyimide film 4 may be applied.
[0018]
Further, as shown in FIG. 8A, TiW21 (or Cu may be formed on TiW) is formed on the oxide film 3 including the Al pad 2 and patterned to a predetermined pattern. . A so-called rewiring structure in which Cu7A (Au) is formed via the polyimide film 4A may be employed.
[0019]
Subsequently, as shown in FIG. 2A, an insulating film 10 is pasted on the polyimide film 4 including the Cu7 (Au), and the support plate 11 and the Si substrate 1 side are pasted through the film 10.
[0020]
Here, the support plate 11 is sometimes of the Si substrate 1 to be described later BG (back grinding), a support for preventing the cracks of the Si substrate 1, for example, Si substrate or an oxide film (glass substrate) or ceramic Is used. In the present embodiment, the film thickness necessary for the support is about 400 μm.
[0021]
The film 10 employs an organic film soluble in acetone for the purpose of improving workability in the process of separating the Si substrate 1 and the support plate 11 described later. In this embodiment, the film 10 has a thickness of about 400 μm.
[0022]
Furthermore, the film 10 is sealed and hardened by filling the outer peripheral portion of the film 10 with an epoxy resin 12 as shown in FIG. This prevents the entry of chemicals such as organic solvents during various operations.
[0023]
If the back grind film thickness in the BG process of the Si substrate 1 is small, the process of attaching the support plate 11 can be omitted.
[0024]
Next, as shown in FIG. 3A, the Si substrate 1 side can be BG-processed to reduce the thickness of the Si substrate 1 to about 10 to 100 μm. At this time, the support plate 11 supports the Si substrate 1 during the BG process. Then, an oxide film 13 of about 0.01 μm is formed on the back side of the Si substrate 1 subjected to the BG treatment. Instead of the oxide film 13, an organic insulator made of a silicon nitride film or polyimide may be formed. Furthermore, since it does not depend on the flatness on Cu in the BG process, it can be back-ground as it is and the workability is good.
[0025]
Further, as shown in FIG. 3B, the oxide film 13 and the Si substrate 1 are etched using a photoresist film (not shown) as a mask to form an opening 14. Subsequently, as shown in FIG. 4A, the oxide film 3 exposed from the opening 14 is etched to expose the Al pad 2. Then, an oxide film is formed by CVD so as to cover the oxide film 13 including the Al pad 2 in the opening 14a, and the oxide film is anisotropically etched to oxidize the side wall of the opening 14a. The sidewall spacer film 15 is formed with the film remaining. Note that the CVD film forming temperature for the oxide film is preferably as low as about 200 ° C. Further, the sidewall spacer film 15 may be formed using a silicon nitride film.
[0026]
Next, as shown in FIG. 4B, a barrier film 16 such as titanium nitride (TiN) or tantalum nitride (TaN) is formed by sputtering in the opening 14a through the sidewall spacer film 15, and the barrier film is formed. Cu 17 is embedded in the opening 14 a through 16. In this step, first, a Cu seed and Cu plating treatment is performed on the barrier film 16, and the Cu is annealed. And the said Cu is embed | buried in the opening part 14a. Here, when flatness is particularly required, the Cu is subjected to CMP polishing.
[0027]
Further, as shown in FIG. 5A, a solder mask 18 having an opening that is somewhat wider than the opening size of the opening 14a in which the Cu 17 is embedded is formed on the Cu 17, and the A solder paste 19 is formed on the Cu 17 by screen printing a solder paste on the opening and reflowing the solder paste. In the present embodiment, as the solder mask 18, a polyimide film made of Rica coat that can be imidized at 200 ° C. is used.
[0028]
As shown in FIG. 8B, an Al film 31 and a Ni film (Au film) 32 are formed on the oxide film 13 including the Cu 17 and patterned to have a predetermined pattern. And you may employ | adopt the structure which forms 19A of solder balls via the solder mask 18A.
[0029]
Subsequently, as shown in FIG. 5B, the Si substrate 1 side is diced to a position reaching the film 10.
[0030]
Then, by immersing the Si substrate 1 in an acetone solution tank (not shown), acetone enters from the dicing line (D) and dissolves the film 10 as shown in FIG. Therefore, the Si substrate 1 (each chip) and the support plate 11 are automatically separated, and a single CSP chip 20 as shown in FIG. 6A is completed.
[0031]
As described above, in the present embodiment, since the Si substrate 1 and the support plate 11 are bonded together using the organic film 10 that is dissolved in acetone, after dicing, the both can be simply performed by immersing the Si substrate 1 in acetone. The workability is good.
[0032]
Further, instead of the film 10, a film having a weak adhesive force may be used to physically peel the chip after dicing. Furthermore, when transparent glass is used as the support plate 11, a UV tape is applied as the organic film 10, UV irradiation is performed after dicing, and the chip is peeled off.
[0033]
In addition, after dicing, for example, heat is applied from the back surface of the wafer with a hot plate, and the organic film (film 10) sandwiched between the wafer and the support substrate 11 is melted and softened to peel off both. good. At this time, when the film 10 is an organic film soluble in acetone, by heating at about 200 ° C., in case of using the polyimide film the film 10 by heating at about 400 ° C. is Keru soluble.
[0034]
As another form of peeling the Si substrate 1 and the support plate 11, there is a method in which the epoxy resin at the edge is rotated with the wafer vertically and soaked in chemicals such as acid only on the outer periphery before dicing. There is also a method of separating the blade by putting it in an epoxy resin at the edge between the wafer and the chip. And after both methods, a BG tape is stuck and it dices.
[0035]
Then, as shown in FIG. 7, the CSP chip 20 is bonded (laminated) with Cu7 (Au) and the solder ball 19 by metal contact with the CSP chip 20, thereby enabling three-dimensional mounting (any number of layers). If the chip size is the same (memory or the like), the capacity can be increased.
[0036]
【The invention's effect】
In the present invention, processing such as Si penetration is performed from the surface as in the conventional three-dimensional mounting technique, and a copper (Cu) via hole is formed, so that CMP (Chemical Mechanical Polishing) processing is not required on the surface side. In addition, since the rewiring for connecting the Cu via and the pad is not required after the Cu via is formed, the number of manufacturing steps does not increase.
[0037]
Furthermore, since it does not depend on the flatness on Cu, it can be back ground as it is.
[0038]
Further, the support plate 11 and the Si substrate 1, since the a BG (back grinding) and subsequent treatment after a laminated adhered Ri, the thickness of the chip can be reduced as required.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device of one embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present invention.

Claims (9)

表面側に金属パッドが形成された半導体ウエハを準備し、
前記半導体ウエハの前記金属パッドが形成された表面側に対して、当該半導体ウエハを支持する支持体を溶液に溶ける有機膜から成るフィルムを介して貼り合わせる工程と、
前記支持体が貼り合わされた前記半導体ウエハの裏面から前記金属パッドまで貫通する開口を形成する工程と、
前記開口の側壁部に絶縁膜を形成した後に、当該開口内に金属層を形成する工程と、
前記支持体が貼り合わされた前記半導体ウエハの裏面から前記フィルムまでダイシングする工程と、
前記半導体ウエハと前記支持体とを分離する工程とを有することを特徴とする半導体装置の製造方法。Prepare a semiconductor wafer with metal pads on the surface side,
Bonding the support for supporting the semiconductor wafer to the surface side of the semiconductor wafer on which the metal pads are formed via a film made of an organic film that dissolves in a solution ;
Forming an opening penetrating from the back surface of the semiconductor wafer to which the support is bonded to the metal pad;
Forming an insulating film on the side wall of the opening and then forming a metal layer in the opening;
Dicing from the back surface of the semiconductor wafer to which the support is bonded to the film;
A method for manufacturing a semiconductor device, comprising the step of separating the semiconductor wafer and the support. 前記半導体ウエハの前記金属パッドが形成された表面側に対して、当該半導体ウエハを支持する支持体をフィルムを介して貼り合わせる工程が、前記半導体ウエハと前記支持体の外径よりも小さい外径を有するフィルムを前記半導体ウエハと前記支持体とで挟んだ状態で、その周端部のみエポキシ樹脂を用いて貼り合わせる工程であることを特徴とする請求項１に記載の半導体装置の製造方法。  The step of bonding a support for supporting the semiconductor wafer via a film to the surface side of the semiconductor wafer on which the metal pad is formed has an outer diameter smaller than the outer diameter of the semiconductor wafer and the support. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the film is a step of bonding the peripheral edge portion of the film having an adhesive between the semiconductor wafer and the support using an epoxy resin. 前記フィルムが、粘着性を有するフィルムであることを特徴とする請求項１、２のいずれかに記載の半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 1, wherein the film is an adhesive film . 前記金属層上に電極を形成する工程を有することを特徴とする請求項１乃至請求項３のいずれかに記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming an electrode on the metal layer . 前記金属層上に電極を形成する工程が、当該金属層上に金属配線を形成し、当該金属配線上に電極を形成する工程を有することを特徴とする請求項４に記載の半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming an electrode on the metal layer includes a step of forming a metal wiring on the metal layer and forming an electrode on the metal wiring. Method. 前記半導体ウエハ裏面に前記開口を形成する前に、その裏面を研磨することを特徴とする請求項１乃至請求項５のいずれかに記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1, wherein the back surface is polished before forming the opening on the back surface of the semiconductor wafer . 前記金属パッド上に電極接続用の金属層を形成する工程を有することを特徴とする請求項１乃至請求項６のいずれかに記載の半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a metal layer for electrode connection on the metal pad . 一方の半導体装置の前記金属層と他方の半導体装置の前記電極とを積層する工程を有することを特徴とする請求項７に記載の半導体装置の製造方法。 8. The method of manufacturing a semiconductor device according to claim 7 , further comprising a step of stacking the metal layer of one semiconductor device and the electrode of the other semiconductor device . 前記支持体は、Ｓｉ基板、酸化膜、ガラス基板、セラミックのいずれかから成ることを特徴とする請求項１乃至請求項８のいずれかに記載の半導体装置の製造方法。 9. The method of manufacturing a semiconductor device according to claim 1, wherein the support is made of any one of a Si substrate, an oxide film, a glass substrate, and a ceramic .
JP2002111571A 2002-04-15 2002-04-15 Manufacturing method of semiconductor device Expired - Fee Related JP4212293B2 (en)

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Families Citing this family (41)

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Publication number Priority date Publication date Assignee Title
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