JP4845368B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a through electrode and a manufacturing method thereof.

  In recent years, CSP (Chip Size Package) has attracted attention as a three-dimensional mounting technique and a new packaging technique. The CSP refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip.

  Conventionally, a BGA type semiconductor device having a through electrode is known as a kind of CSP. This BGA type semiconductor device has a through electrode that penetrates through a semiconductor substrate and is connected to a pad electrode. In addition, the semiconductor device has a plurality of ball-shaped conductive terminals made of a metal member such as solder arranged in a lattice pattern on the back surface.

  When the semiconductor device is incorporated into an electronic device, each conductive terminal is connected to a wiring pattern on a circuit board (for example, a printed board). Such a BGA type semiconductor device is provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. It has the advantage that it can be reduced in size.

  Next, an outline of a method for manufacturing a BGA type semiconductor device having a through electrode according to a conventional example will be described. First, a support is bonded to the surface of the semiconductor substrate on which the pad electrode is formed via the first insulating film via a resin layer. In addition, a support body should just be adhere | attached as needed, and does not necessarily need to be adhere | attached.

  Next, a via hole reaching the pad electrode from the back surface of the semiconductor substrate is formed by etching the semiconductor substrate. Further, a second insulating film exposing the pad electrode at the bottom of the via hole is formed on the back surface of the semiconductor substrate including the inside of the via hole.

  Further, a through electrode electrically connected to the pad electrode exposed at the bottom is formed on the second insulating film in the via hole. At the same time, a wiring layer connected to the through electrode is formed on the second insulating film on the back surface of the semiconductor substrate. Then, a protective layer is formed on the back surface of the semiconductor substrate including the wiring layer. Further, a part of the protective layer may be opened to expose a part of the wiring layer, and a conductive terminal may be formed on the wiring layer. Thereafter, the semiconductor substrate is cut and separated into a plurality of semiconductor chips by dicing.

In addition, as a related technical document, the following patent documents are mentioned, for example.
JP 2003-309221 A

Next, some steps of the above-described conventional semiconductor device manufacturing method will be described with reference to the drawings. 1 4 and 1 5 are sectional views showing a manufacturing method of a semiconductor device according to a conventional example.

In the semiconductor device of conventional example, as shown in FIG. 1 4, by a so-called pre-process, the pad electrode 52 through the insulating film 51 is formed on the surface of the semiconductor substrate 50. In a subsequent process, a support 56 is bonded to the surface of the semiconductor substrate 50 on which the pad electrode 52 is formed via a resin layer 55. Here, the inventor considers that thermal stress (residual stress or intrinsic stress) applied during the deposition of the pad electrode 52 is accumulated.

However, as shown in FIG. 15, when the semiconductor substrate 50 is etched using the resist layer 60 as a mask to form a via hole 57 that penetrates the semiconductor substrate 50, the pad electrode 52 at the bottom is originally horizontal. Where the state should be kept, it may be pushed into the space of the via hole 57 and deformed to bend.

  The deformation of the pad electrode 52 is that the stress accumulated in the pad electrode 52 when the pad electrode 52 is formed in the previous process loses the previous balance due to a thermal load such as during a thermal cycle test. It is considered that this is caused by intensive release from the pad electrode 52 at the bottom of the via hole 57. Further, the pad electrode 52 may be curved even after the insulating film 51 is etched.

  Further, after a through electrode (not shown) made of, for example, copper (Cu) connected to the pad electrode 52 at the bottom of the via hole 57 is formed, the pad electrode 52 is pulled toward the back side of the semiconductor substrate 50 by the through electrode. To bend and deform. The deformation at this time is considered to occur due to the relationship between the residual stress accumulated in the through electrode and the stress accumulated in the pad electrode 12 when the through electrode is formed.

  Furthermore, the pad electrode 52 may be damaged or disconnected due to metal fatigue due to the deformation of the pad electrode 52 as described above. For this reason, after a through electrode (not shown) made of, for example, copper (Cu) is formed in the via hole 57 including the deformed pad electrode 52, it is between the through electrode and the pad electrode exposed in the via hole 57. In some cases, connection failure occurred. That is, the deformation of the pad electrode 52 causes a problem that the reliability of the semiconductor device having the through electrode is lowered. As a result, the reliability and yield of the semiconductor device having a through electrode have been reduced. Therefore, the present invention aims to improve the reliability and yield of a semiconductor device having a through electrode and a manufacturing method thereof.

The semiconductor device and the manufacturing method thereof according to the present invention have been made in view of the above problems, and have the following characteristics. That is, the semiconductor device of the present invention covers the semiconductor chip, the pad electrode formed on the surface of the semiconductor chip, the refractory metal layer formed on the pad electrode, and the pad electrode and the refractory metal layer. The passivation layer formed on the front surface of the semiconductor chip , the via hole reaching the pad electrode from the back surface of the semiconductor chip , and formed in the via hole and electrically connected to the pad electrode at the bottom of the via hole And a through electrode. Moreover, you may provide the support body adhere | attached through the resin layer on the passivation layer. Here, the refractory metal layer includes any one of titanium, a titanium alloy, tantalum, and a tantalum alloy.

In addition to the above configuration, the semiconductor device of the present invention includes a wiring layer electrically connected to the through electrode and extending on the back surface of the semiconductor chip, and a part of the wiring layer on the semiconductor chip including the wiring layer. And a protective layer formed to expose the top. Furthermore, the semiconductor device of the present invention may include a conductive terminal on a part of the wiring layer.

The method for manufacturing a semiconductor device of the present invention includes a step of forming a refractory metal layer on a pad electrode formed on the surface of a semiconductor substrate, and a surface of the semiconductor substrate including the pad electrode and the refractory metal layer. On top, a step of forming a passivation layer, a step of forming a via hole reaching the pad electrode from the back surface of the semiconductor substrate , and a through electrode electrically connected to the pad electrode at the bottom are formed in the via hole And a step of cutting and separating the semiconductor substrate into a plurality of semiconductor chips. Moreover, you may have the process of forming a support body through a resin layer on a passivation layer. Here, the refractory metal layer includes any one of titanium, a titanium alloy, tantalum, and a tantalum alloy.

In addition to the above steps, the method of manufacturing a semiconductor device of the present invention includes a step of forming a wiring layer that is electrically connected and extends on the back surface of the semiconductor substrate, and the wiring on the semiconductor substrate including the wiring layer. And a step of forming a protective layer so as to expose a part of the layer. Furthermore, the method for manufacturing a semiconductor device of the present invention may include a step of forming a conductive terminal on a part of the wiring layer.

According to the present invention, the refractory metal layer formed on the pad electrode has a function of bonding the passivation layer covering them and the pad electrode. Therefore, the pad electrode is less likely to be peeled off from the passivation layer through the refractory metal layer, and is more easily held in a horizontal state on the surface of the semiconductor chip (semiconductor substrate) as compared with the conventional example. That is, the deformation of the pad electrode exposed at the bottom of the via hole as seen in the conventional example can be suppressed as much as possible.

  In addition, since the deformation of the pad electrode exposed at the bottom of the via hole can be suppressed as much as possible, connection failure between the through electrode connected to the pad electrode is suppressed, and the reliability related to the connection between the through electrode and the pad electrode is suppressed. Will improve. As a result, the reliability and yield of a semiconductor device having a through electrode can be improved.

  Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. 1 to 12 are cross-sectional views showing a method for manufacturing a semiconductor device according to this embodiment. 1 to 12 show the vicinity of a dicing line (not shown) in the semiconductor substrate.

  First, as shown in FIG. 1, a semiconductor substrate 10 having an electronic device (not shown) formed on the surface is prepared. Here, it is assumed that an electronic device (not shown) is a light receiving element such as a CCD (Charge Coupled Device) or an infrared sensor, or a light emitting element. Alternatively, the electronic device (not shown) may be an electronic device other than the light receiving element and the light emitting element. The semiconductor substrate 10 is made of, for example, a silicon substrate, but may be a substrate made of other materials. The semiconductor substrate 10 preferably has a thickness of about 130 μm.

  Next, a first insulating film 11 is formed as an interlayer insulating film on the surface of the semiconductor substrate 10 including an electronic device (not shown). The first insulating film 11 is made of, for example, a P-TEOS film or a BPSG film. The first insulating film 11 is preferably formed with a film thickness of about 0.8 μm by CVD.

  Next, a pad electrode 12 that is an external connection electrode connected to an electronic device (not shown) is formed on the first insulating film 11 on the surface of the semiconductor substrate 10. The pad electrode 12 is made of, for example, aluminum (Al), and preferably has a film thickness of about 1 μm to 2 μm. At this time, the pad electrode 12 is formed in a horizontal state, but a predetermined amount of stress is accumulated in the pad electrode 12 according to the conditions during the film formation.

  Next, as shown in FIG. 2, a refractory metal layer 13 is formed on the pad electrode 12. The refractory metal layer 13 has a function of adhering a passivation layer 14 which is a first protective layer to be described later and the pad electrode 12.

  The refractory metal layer 13 is made of a metal containing any one of titanium (Ti), titanium alloy, tantalum (Ta), and tantalum alloy. The titanium alloy constituting the refractory metal layer 13 may be titanium nitride (TiN), titanium tungsten (TiW), or the like, for example. The tantalum alloy may be, for example, tantalum nitride (TaN) or tantalum tungsten (TaW). Alternatively, the refractory metal layer 13 has a laminated structure of the above metals. Alternatively, the refractory metal layer 13 may be made of a metal other than the above as long as it has a function of bonding a passivation layer 14 to be described later and the pad electrode 12.

  Here, when the refractory metal layer 13 is made of titanium (Ti), the film thickness is preferably about 10 nm to 15 nm. In addition, as a method of forming the refractory metal layer 13 at this time, it is preferable to use a sputtering method. When the refractory metal layer 13 is made of titanium nitride (TiN), the film thickness is preferably about 140 nm to 150 nm. In addition, as a method of forming the refractory metal layer 13 at this time, it is preferable to use a sputtering method.

Next, as shown in FIG. 3, on the surface of the semiconductor substrate 10, that is, on the pad electrode 12 and the refractory metal layer 13 and on the first insulating film 11, the first insulating film 11 is covered. A passivation layer 14 as a protective layer is formed. The passivation layer 14 is made of, for example, a silicon oxide film (SiO ₂ film) or a silicon nitride film (SiN film), and is formed by, for example, a plasma CVD method. The passivation layer 14 is preferably formed to have a thickness of about 1 μm to 2 μm.

  Here, the refractory metal layer 13 covered with the passivation layer 14 bonds the passivation layer 14 and the pad electrode 12 together. Therefore, the pad electrode 12 is less likely to be peeled off from the passivation layer 14 and is more easily held in a horizontal state on the surface of the semiconductor substrate 10 as compared with the conventional example.

  The refractory metal layer 13 described above preferably satisfies the relationship that the hardness is higher than the hardness of the passivation layer 14 and lower than the hardness of the pad electrode 12. Due to this hardness relationship, the adhesion between the pad electrode 12 and the passivation layer 14 through the refractory metal layer 13 can be enhanced.

  Next, as shown in FIG. 4, a support 16 is bonded to the surface of the semiconductor substrate 10 via a resin layer 15. Here, when the electronic device (not shown) is a light receiving element or a light emitting element, the support 16 is bonded by a material having a transparent or translucent property such as glass. When the electronic device (not shown) is not a light receiving element or a light emitting element, the support 16 may be formed of a material that does not have a transparent or translucent property. Further, the support 16 may be a tape. This support 16 may be removed in a later step. Alternatively, the support 16 may be left without being removed. Alternatively, the adhesion of the support 16 may be omitted.

  Next, as shown in FIG. 5, a first resist layer 41 is selectively formed on the back surface of the semiconductor substrate 10. That is, the first resist layer 41 has an opening at a position corresponding to the pad electrode 12 on the back surface of the semiconductor substrate 10.

Next, using the first resist layer 41 as a mask, the semiconductor substrate 10 is etched, preferably by a dry etching method. At this time, for example, a gas containing SF ₆ , O ₂ , C ₄ F ₈ or the like is used as the etching gas. When SF ₆ or O ₂ is used as the etching gas, the etching conditions are, for example, that the power is about 1.5 KW, the gas flow rate is 300/30 sccm, and the pressure is 25 Pa. preferable.

  Thus, a via hole penetrating from the back surface of the semiconductor substrate 10 to the front surface is formed on the pad electrode 12 by the etching. At the bottom of the via hole 17, the first insulating film 11 is exposed. At this time, the pad electrode 12 in contact with the first insulating film 11 at the bottom of the via hole 17 is bonded to the passivation layer 14 via the refractory metal layer 13 and held on the surface of the semiconductor substrate 10 in a horizontal state. Therefore, as seen in the conventional example, even when the pad electrode 52 faces the space of the via hole 1 through the first insulating film 11, the pad electrode 12 is curved so as to be pushed out into the space of the via hole 17. Deformation is suppressed as much as possible. For this reason, it is possible to prevent the pad electrode 12 from being damaged or broken due to metal fatigue as much as possible.

  Next, as shown in FIG. 6, a part of the first insulating film 11 exposed at the bottom of the via hole 17 is selectively removed using the first resist layer 41 as a mask. As a result, a part of the pad electrode 12 is exposed at the bottom of the via hole 17. Thereafter, the first resist layer 41 is removed.

Next, as shown in FIG. 7, a second insulating film 18 is formed on the back surface of the semiconductor substrate 10 including the inside of the via hole 17. The second insulating film 18 is made of, for example, a silicon oxide film (SiO ₂ film) or a silicon nitride film (SiN film), and is formed by, for example, a plasma CVD method. The second insulating film 18 is preferably formed to have a thickness of about 1 μm to 2 μm.

  Next, as shown in FIG. 8, the second insulating film 18 is etched from the back side of the semiconductor substrate 10, preferably by anisotropic dry etching. Here, the second insulating film 18 at the bottom of the via hole 17 is formed thinner than the second insulating film 18 on the back surface of the semiconductor substrate 10 according to the depth of the via hole 17. Therefore, the second insulating film 18 is removed at the bottom of the via hole 17 by the etching, and a part of the pad electrode 12 is exposed. However, the second insulating film 18 is exposed on the back surface of the semiconductor substrate 10 and the sidewall of the via hole 17. The insulating film 18 remains.

  Next, as shown in FIG. 9, a barrier metal layer 19 is formed in the via hole 17 and on the second insulating film 18 on the back surface of the semiconductor substrate 10. The barrier metal layer 19 is made of a metal layer such as a titanium tungsten (TiW) layer, a titanium nitride (TiN) layer, or a tantalum nitride (TaN) layer.

  The barrier seed layer 19 is formed by, for example, a sputtering method, a CVD method, an electroless plating method, or other film forming methods. A seed layer (not shown) is formed on the barrier metal layer 19. This seed layer serves as an electrode for plating the wiring layer 21 described later, and is made of a metal such as copper (Cu), for example.

  In the case where the second insulating film 18 on the side wall of the via hole 17 is formed of a silicon nitride film (SiN film), the silicon nitride film (SiN film) serves as a barrier against copper diffusion. 19 may be omitted.

  Next, a wiring formation layer 20A is formed so as to cover the barrier metal layer 19 and the seed layer formed on the back surface of the semiconductor substrate 10. Here, the wiring forming layer 20A is a metal layer made of, for example, copper (Cu) by, for example, electrolytic plating.

  Next, as shown in FIG. 10, a second resist layer 42 is formed in a predetermined region on the wiring formation layer 20A. Then, using the second resist layer 42 as a mask, the wiring forming layer 20A is patterned to form the through electrode 20 and the wiring layer 21 that is continuous with and electrically connected to the through electrode 20. The plating film thickness is adjusted to such a thickness that the through electrode 20 is imperfectly embedded in the via hole 16. Alternatively, the through electrode 20 may be formed so as to be completely embedded in the via hole 17. The predetermined region for forming the second resist layer 42 is a region excluding the formation region of the via hole 17 and the back surface of the semiconductor substrate 10 on which the wiring layer 21 having a predetermined pattern to be described later is not formed. This is the upper area.

  Here, the through electrode 20 is formed to be electrically connected to the pad electrode 12 exposed at the bottom of the via hole 17 through the seed layer and the barrier metal layer 19. Further, the wiring layer 21 continuous with the through electrode 20 is formed on the back surface of the semiconductor substrate 10 with a predetermined pattern via the seed layer and the barrier metal layer 19. Subsequently, after removing the second resist layer 42, the barrier metal layer 19 is patterned and removed using the wiring layer 21 and the seed layer as a mask.

  The through electrode 20 and the wiring layer 21 described above may be formed by separate processes. Further, the through electrode 20 and the wiring layer 21 may be formed by other metal and a film forming method instead of the electrolytic plating method using copper (Cu) as described above. For example, the through electrode 20 and the wiring layer 21 are made of aluminum (Al), an aluminum alloy, or the like, and may be formed by, for example, a sputtering method. In this case, after forming a barrier metal layer (not shown) on the back surface of the semiconductor substrate 10 including the via hole 17, a resist layer (not shown) is formed in a predetermined region on the barrier metal layer excluding the formation region of the via hole 17. . Then, the through electrode and the wiring layer made of the metal may be formed by sputtering using the resist layer as a mask. Alternatively, the through electrode 20 and the wiring layer 21 may be formed by a CVD method.

  Next, as shown in FIG. 11, on the back surface of the semiconductor substrate 10 including the inside of the via hole 17, that is, on the barrier seed layer 19, the through electrode 20, and the wiring layer 21 so as to cover them, the second A solder resist layer 22 is formed as a protective layer. The solder resist layer 22 is made of, for example, a resist material. An opening is provided at a position corresponding to the wiring layer 21 in the solder resist layer 22. Then, a ball-shaped conductive terminal 23 made of a metal such as solder is formed on the wiring layer 21 exposed at the opening.

  Next, as shown in FIG. 12, the semiconductor substrate 10 is diced along a dicing line (not shown). Thereby, a plurality of semiconductor devices including the semiconductor placement chip 10A having the through electrodes 20 are completed.

  As described above, according to the semiconductor device and the manufacturing method thereof of the present embodiment, the pad electrode 12 at the bottom of the via hole 17 is bonded to the passivation layer 14 by the refractory metal layer 13 and is horizontal to the surface of the semiconductor chip 10A. Is held in a stable state. Therefore, as seen in the conventional example, the pad electrode 12 is restrained from being bent and deformed so as to be pushed out into the space of the via hole 17, and the pad electrode 12 is damaged or disconnected due to metal fatigue. Can be suppressed as much as possible.

  Further, since the deformation of the pad electrode 12 at the bottom of the via hole 17 is suppressed as much as possible, connection failure with the through electrode 20 connected to the pad electrode 12 is suppressed, and the connection between the through electrode 20 and the pad electrode 12 is concerned. Reliability is improved. As a result, the reliability and yield of the semiconductor device having the through electrode 20 can be improved.

  The embodiment described above is not limited to the formation of the conductive terminal 23. That is, the conductive terminal 23 is not necessarily formed if the through electrode 20 and the wiring layer 21 can be electrically connected to a circuit board (not shown). For example, when the semiconductor device is an LGA (Land Group Array) type semiconductor device, it is not necessary to form the conductive terminal 23 on a part of the wiring layer 21 that is locally exposed from the solder resist layer 22.

  Further, the above-described embodiment is not limited to the formation of the wiring layer 21. That is, when the through electrode 20 is completely buried in the via hole 17, the wiring layer 21 is not necessarily formed. For example, the through electrode 20 may be directly connected to a circuit board (not shown) without using the wiring layer 21 and the conductive terminal 23. Alternatively, the through electrode 20 includes a conductive terminal 23 on the through electrode 20 exposed at the opening of the via hole 17 and is connected to a circuit board (not shown) via the conductive terminal 23 without using the wiring layer 21. May be.

  The above-described embodiment is also applied to a case where the opening diameter at the bottom of the via hole 17 is formed to be wider than the planar width of the pad electrode 12. FIG. 13 shows the semiconductor device according to this embodiment in this case.

  In the manufacturing process of such a semiconductor device, the formation process of the via hole 17A having the shape as described above is performed by over-etching the semiconductor substrate 1 under a predetermined condition. By this step, the entire surface of the pad electrode 12 adjacent to the first insulating film 11 at the bottom of the via hole 17A (the surface on the side facing the via hole 17A) passes through the first insulating film 11 and the space of the via hole 17A. Confront. Thus, the area of the via hole 17A facing the pad electrode 12 is larger than the area of the via hole 17 facing the pad electrode 12 of the semiconductor device shown in FIG. Therefore, the stress accumulated in the pad electrode 12 when the pad electrode 12 is formed is efficiently released at the bottom of the via hole 17A. Accordingly, the pad electrode 12 is more reliably prevented from being bent and deformed so as to be pushed out into the space of the via hole 17A.

  Furthermore, since the opening end portion of the via hole 17A is not on the pad electrode 12, deformation of the pad electrode 12 with the opening end portion as a fulcrum can be prevented. For this reason, it is possible to prevent the pad electrode 12 from being damaged or broken due to metal fatigue as much as possible.

It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on a prior art example. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on a prior art example.

Claims (16)

A semiconductor chip;
Pad electrodes formed on the surface of the semiconductor chip;
A refractory metal layer formed on the pad electrode;
A passivation layer formed on the surface of the semiconductor chip so as to cover the pad electrode and the refractory metal layer;
A via hole reaching the pad electrode from the back surface of the semiconductor chip;
A semiconductor device comprising: a through electrode formed in the via hole and electrically connected to a pad electrode at the bottom of the via hole. A semiconductor chip;
Pad electrodes formed on the surface of the semiconductor chip;
A refractory metal layer formed on the pad electrode;
A passivation layer formed on the surface of the semiconductor chip so as to cover the pad electrode and the refractory metal layer;
A support bonded on the semiconductor chip on which the passivation layer is formed;
A via hole reaching the pad electrode from the back surface of the semiconductor chip;
A semiconductor device comprising: a through electrode formed in the via hole and electrically connected to a pad electrode at the bottom of the via hole.   3. The semiconductor device according to claim 1, wherein an opening diameter of a bottom portion of the via hole is formed to be wider than a planar width of the pad electrode. It said refractory metal layer is titanium, a semiconductor device according to any one of claims 1 to 3, characterized in that it comprises titanium alloy, tantalum, any one of the tantalum alloy. The passivation layer is a semiconductor device according to any one of claims 1 to 4, characterized in that it consists of a silicon oxide film or a silicon nitride film. A wiring layer electrically connected to the through electrode and extending on the back surface of the semiconductor chip;
On a semiconductor chip comprising the wiring layer, a semiconductor according to any one of claims 1 to 5, characterized in that it comprises a protective layer formed so as to expose the on portion of the wiring layer apparatus. The semiconductor device according to claim 6 , further comprising a conductive terminal on a part of the wiring layer. Hardness of the refractory metal, the greater than the hardness of the passivation film, and a semiconductor according to any one of claims 1 to 7, characterized in that it satisfies the relationship of less than the hardness of the pad electrode apparatus. Forming a refractory metal layer on the pad electrode formed on the surface of the semiconductor substrate;
Forming a passivation layer on the surface of the semiconductor substrate including the pad electrode and the refractory metal layer;
Forming a via hole reaching the pad electrode from the back surface of the semiconductor substrate;
Forming a through electrode electrically connected to the pad electrode at the bottom in the via hole;
And a step of cutting and separating the semiconductor substrate into a plurality of semiconductor chips. Forming a refractory metal layer on the pad electrode formed on the surface of the semiconductor substrate;
Forming a passivation layer on the surface of the semiconductor substrate including the pad electrode and the refractory metal layer;
Bonding a support on the semiconductor substrate on which the passivation layer is formed;
Forming a via hole reaching the pad electrode from the back surface of the semiconductor substrate;
Forming a through electrode electrically connected to the pad electrode at the bottom in the via hole;
And a step of cutting and separating the semiconductor substrate into a plurality of semiconductor chips.   11. The method of manufacturing a semiconductor device according to claim 9, wherein an opening diameter of a bottom portion of the via hole is formed to be wider than a planar width of the pad electrode. The method for manufacturing a semiconductor device according to claim 9, wherein the refractory metal layer includes any one of titanium, a titanium alloy, tantalum, and a tantalum alloy. 13. The method of manufacturing a semiconductor device according to claim 9 , wherein the passivation layer is made of a silicon oxide film or a silicon nitride film. Forming a wiring layer electrically connected to the through electrode and extending on the back surface of the semiconductor substrate;
On the semiconductor substrate including the wiring layer, according to any one of claims 9 to 13, characterized in that it comprises a step of forming a protective layer so as to expose a portion on the wiring layer Semiconductor device manufacturing method. 15. The method of manufacturing a semiconductor device according to claim 14 , further comprising a step of forming a conductive terminal on a part of the wiring layer. The semiconductor according to claim 9 , wherein a hardness of the refractory metal is larger than a hardness of the passivation film and smaller than a hardness of the pad electrode. Device manufacturing method.

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