JP2000195861A - Semiconductor device and method of producing the same - Google Patents

Semiconductor device and method of producing the same

Info

Publication number
JP2000195861A
JP2000195861A JP10368958A JP36895898A JP2000195861A JP 2000195861 A JP2000195861 A JP 2000195861A JP 10368958 A JP10368958 A JP 10368958A JP 36895898 A JP36895898 A JP 36895898A JP 2000195861 A JP2000195861 A JP 2000195861A
Authority
JP
Japan
Prior art keywords
hole
metal
semiconductor substrate
semiconductor device
metal pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10368958A
Other languages
Japanese (ja)
Inventor
Akishi Kobayashi
昭志 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Japan Ltd
Original Assignee
Texas Instruments Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Japan Ltd filed Critical Texas Instruments Japan Ltd
Priority to JP10368958A priority Critical patent/JP2000195861A/en
Publication of JP2000195861A publication Critical patent/JP2000195861A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device suitable for an imaging device, such as a CCD and the like and a method of producing the same. SOLUTION: A semiconductor substrate 12 is etched on the rear surface opposite to the device forming surface, a through-hole 22 is formed opposite to a metal pad 20, a metal is deposited thereon by plating to form a bump 34. Since the bump 34 is formed on the rear surface of the substrate 12 and no obstacle is on the device forming surface, it is suitable for an imaging device. Instead of plating, a metal ball may be positioned and heat-treated on the through-hole 22, and the melt of the metal ball may be filled into the through- hole 22.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、特に、超小型化が
要求される医療用CCD(Charge Coupled Device)等の
撮像デバイスに有効な半導体装置およびその製造方法の
分野に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of a semiconductor device effective for an imaging device such as a medical CCD (Charge Coupled Device) which requires ultra-miniaturization and a method of manufacturing the same.

【0002】[0002]

【従来の技術】通常、半導体装置は、半導体基板の素子
形成面に金属パッド(ボンディングパッド)が形成されて
おり、その半導体基板を分割し、チップ状にした後、例
えばワイヤーボンド法やバンプ法等の技術を用いて、リ
ードフレームのリードや導体パターンと金属パッドとを
電気的に接続し、プラスチックやセラミック等のパッケ
ージに封止し、完成品として出荷している。
2. Description of the Related Art Generally, in a semiconductor device, a metal pad (bonding pad) is formed on an element formation surface of a semiconductor substrate, and the semiconductor substrate is divided into chips, and then, for example, a wire bonding method or a bump method. Using such techniques, the leads or conductor patterns of the lead frame and the metal pads are electrically connected, sealed in a plastic or ceramic package, and shipped as a finished product.

【0003】ここで、図4に、従来の半導体装置の構造
の一例の概略図を示す。同図(a)は、ワイヤーボンドを
用いた場合の構造を示すものであり、半導体基板100
は、素子形成面を上側にしてリードフレーム103上に
固定されている。
FIG. 4 is a schematic view showing an example of the structure of a conventional semiconductor device. FIG. 1A shows a structure using a wire bond.
Are fixed on the lead frame 103 with the element formation surface facing upward.

【0004】この半導体基板100の周囲には、リード
102が配置されており、半導体基板100上に設けら
れたボンディングパッド120は、ボンディングワイヤ
ー121によってリード102に接続されている。
[0004] A lead 102 is arranged around the semiconductor substrate 100, and a bonding pad 120 provided on the semiconductor substrate 100 is connected to the lead 102 by a bonding wire 121.

【0005】これに対し、同図(b)は、バンプを用いた
場合の構造を示しており、ボンディングパッド130上
に形成されたバンプ131を、回路基板上に形成された
導体パターン104に当接させ、熱処理によってバンプ
131を溶融させることで、バンプ131を導体パター
ン104に電気的、機械的に接続している。
On the other hand, FIG. 1B shows a structure using a bump, in which a bump 131 formed on a bonding pad 130 is applied to a conductor pattern 104 formed on a circuit board. The bumps 131 are electrically and mechanically connected to the conductive pattern 104 by being brought into contact with each other and melting the bumps 131 by heat treatment.

【0006】しかしながら、上記バンプ130を用いた
接続方法では、半導体基板101の素子形成面を上側に
できないため、CCD等の撮像デバイスを組み立てるこ
とができない。
However, according to the connection method using the bumps 130, since the element formation surface of the semiconductor substrate 101 cannot be turned upward, an imaging device such as a CCD cannot be assembled.

【0007】他方、ボンディングワイヤー121を用い
た場合、半導体基板100の素子形成面を上方に向けら
れるが、半導体装置全体が大型になってしまう。また、
半導体基板100上にボンディングワイヤー121が存
在するため、ボンディングワイヤー121が光を乱反射
させ、半導体基板100の受光特性を悪化させてしまう
と言う問題がある。
On the other hand, when the bonding wires 121 are used, the element forming surface of the semiconductor substrate 100 can be directed upward, but the entire semiconductor device becomes large. Also,
Since the bonding wires 121 exist on the semiconductor substrate 100, there is a problem that the bonding wires 121 diffusely reflect light and deteriorate light receiving characteristics of the semiconductor substrate 100.

【0008】特に、近年では内視鏡等の医療用のCCD
には、一層の小型化と高性能化が求められているが、上
記従来技術の接続技術では、対応することが困難であ
る。
Particularly, in recent years, medical CCDs such as endoscopes have been used.
Are required to be further reduced in size and higher in performance, but it is difficult to cope with the above-mentioned conventional connection technology.

【0009】[0009]

【発明が解決しようとする課題】本発明は、上記従来技
術の不都合を解決するために創作されたものであり、そ
の目的は、装置を超小型化することができ、光の乱反射
が生じない半導体装置およびその製造方法を提供するこ
とにある。
SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned disadvantages of the prior art, and has as its object to make the apparatus ultra-small and not to cause irregular reflection of light. A semiconductor device and a method for manufacturing the same are provided.

【0010】[0010]

【課題を解決するための手段】上記課題を解決するため
に、請求項1記載の発明は、半導体基板と、前記半導体
基板の第1の面側に形成された金属パッドとを有する半
導体装置であって、前記半導体基板の前記金属パッド底
面下には、前記第1の面とは反対側の第2の面に開口す
るスルーホールが設けられて構成されている。
According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor substrate and a metal pad formed on a first surface side of the semiconductor substrate. In addition, a through hole is provided below the bottom surface of the metal pad of the semiconductor substrate on a second surface opposite to the first surface.

【0011】請求項2記載の発明は、請求項1記載の半
導体装置であって、前記スルーホール内には、前記金属
パッド底面と電気的に接続された導電性物質が充填され
て構成されている。
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the through hole is filled with a conductive material electrically connected to the bottom surface of the metal pad. I have.

【0012】請求項3記載の発明は、請求項2記載の半
導体装置であって、前記スルーホール側壁には絶縁膜が
形成され、前記導電性物質と前記半導体基板とは電気的
に絶縁されて構成されている。
According to a third aspect of the present invention, in the semiconductor device according to the second aspect, an insulating film is formed on the side wall of the through hole, and the conductive material is electrically insulated from the semiconductor substrate. It is configured.

【0013】請求項4記載の発明は、請求項2又は請求
項3のいずれか1項記載の半導体装置であって、前記ス
ルーホール内に充填された導電性物質により、前記第2
の面側に突出するバンプが形成されている。
According to a fourth aspect of the present invention, in the semiconductor device according to any one of the second and third aspects, the second conductive material is filled in the through hole.
Are formed on the surface side of.

【0014】請求項5記載の発明は、第1、第2の面を
有する半導体基板の、前記第1の面側に金属パッドを形
成し、 前記半導体基板の前記第2の面側から該半導体
基板を部分的にエッチングし、前記金属パット底面位置
にスルーホールが形成する半導体装置製造方法である。
According to a fifth aspect of the present invention, a metal pad is formed on the first surface side of a semiconductor substrate having first and second surfaces, and the semiconductor substrate is formed from the second surface side of the semiconductor substrate. A method of manufacturing a semiconductor device, wherein a substrate is partially etched to form a through hole at a position of a bottom surface of the metal pad.

【0015】請求項6記載の発明は、請求項5記載の半
導体装置製造方法であって、少なくとも前記スルーホー
ル側壁に絶縁膜を形成する工程を有している。
According to a sixth aspect of the present invention, there is provided the semiconductor device manufacturing method according to the fifth aspect, further comprising a step of forming an insulating film on at least the side wall of the through hole.

【0016】請求項7記載の発明は、請求項5又は請求
項6記載の半導体装置製造方法であって、前記スルーホ
ール内に前記金属パッド底面を露出させた後、金属を析
出させ、前記スルーホールを充填する工程を有してい
る。
According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifth or sixth aspect, after exposing the bottom surface of the metal pad in the through hole, depositing a metal, There is a step of filling the holes.

【0017】請求項8記載の発明は、請求項7記載の半
導体装置製造方法であって、前記スルーホール内に露出
する前記金属パッド底面上に金属膜を形成した後、該金
属膜表面に前記金属を析出させる工程を有している。
The invention according to claim 8 is the method of manufacturing a semiconductor device according to claim 7, wherein a metal film is formed on the bottom surface of the metal pad exposed in the through hole, and the metal film is formed on the surface of the metal film. And a step of depositing a metal.

【0018】請求項9記載の発明は、請求項5又は請求
項6記載の半導体装置製造方法であって、前記スルーホ
ール内に溶融した低融点の金属を流し込み、該スルーホ
ール内を前記低融点の金属で充填する工程を有してい
る。
According to a ninth aspect of the present invention, there is provided the method of manufacturing a semiconductor device according to the fifth or sixth aspect, wherein a molten metal having a low melting point is poured into the through hole, and the low melting point metal is filled in the through hole. And a step of filling with a metal.

【0019】本発明の半導体装置は半導体基板の第1面
側に金属パッドが形成されており、その半導体基板の金
属パッド底面下にはスルーホールが設けられている。こ
のスルーホールは、半導体基板の第1の面とは反対側の
第2の面で開口している。
In the semiconductor device of the present invention, a metal pad is formed on the first surface side of the semiconductor substrate, and a through hole is provided below the bottom surface of the metal pad of the semiconductor substrate. This through hole is open on the second surface of the semiconductor substrate opposite to the first surface.

【0020】金属パッド底面を、スルーホール内に露出
させ、又は、露出した表面に更に金属膜を形成した後、
スルーホール内に金属等の導電性物質を充填すると、充
填された導電性物質と、金属パッドとが電気的に接続さ
れる。
After exposing the bottom surface of the metal pad in the through hole or forming a metal film on the exposed surface,
When the through hole is filled with a conductive material such as a metal, the filled conductive material is electrically connected to the metal pad.

【0021】そして、充填された導電性物質を外部リー
ドや導体パターンに接続すると、ボンディングパッドを
外部回路に電気的に接続させることができる。スルーホ
ール内に絶縁膜を形成しておくと、充填された導電性物
質と半導体基板とを電気的に絶縁させることができる。
半導体基板の第2の面上にも絶縁膜を形成しておくと、
第2の面側で、導電性物質と半導体基板とが短絡するこ
とが無くなる。
When the filled conductive material is connected to an external lead or a conductive pattern, the bonding pad can be electrically connected to an external circuit. If an insulating film is formed in the through hole, the filled conductive material and the semiconductor substrate can be electrically insulated.
If an insulating film is also formed on the second surface of the semiconductor substrate,
A short circuit between the conductive substance and the semiconductor substrate on the second surface side is eliminated.

【0022】また、スルーホール内に充填する導電性物
質を第2の面上に盛り上げ、第2の面から突出したバン
プを形成しておくと、リードや導体パターンとの接続が
容易になる。
Further, when the conductive material filling the through holes is raised on the second surface and bumps protruding from the second surface are formed, connection with the leads and the conductor pattern becomes easy.

【0023】上記のようにスルーホールを導電性物質で
充填するためには、メッキ法によって金属を析出させた
り、半導体基板の第2の面を上方に向け、スルーホール
開口部上に低融点金属のボールを配置し、熱処理によっ
て溶融させ、スルーホール内に流し込むことができる。
In order to fill the through hole with a conductive material as described above, a metal is deposited by a plating method, or the second surface of the semiconductor substrate is directed upward, and a low melting point metal is placed on the through hole opening. Can be arranged, melted by heat treatment, and poured into through holes.

【0024】いずれの場合も、スルーホール内に露出す
る金属パッド上に、メッキの下地層となる金属膜や、低
融点金属との密着性がよい金属膜を形成しておくことが
できる。
In any case, a metal film serving as a base layer for plating or a metal film having good adhesion to a low melting point metal can be formed on the metal pad exposed in the through hole.

【0025】[0025]

【発明の実施の形態】以下に、添付の図面に示す実施形
態に基づいて、本発明の半導体装置をその製造方法と共
に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described below with reference to an embodiment shown in the accompanying drawings, together with a method for manufacturing the same.

【0026】図1(a)〜(f)、図2(g)〜(k)は、本発
明の製造方法を示す工程図であり、図1(a)〜(c)に示
される半導体基板12から形成される本発明の半導体装
置は、図1(d)〜(f)及び図2(g)〜(h)に示されてい
る。
FIGS. 1 (a) to 1 (f) and 2 (g) to 2 (k) are process diagrams showing the manufacturing method of the present invention, and show the semiconductor substrate shown in FIGS. The semiconductor device of the present invention formed from 12 is shown in FIGS. 1 (d) to 1 (f) and 2 (g) to 2 (h).

【0027】以下、図1および図2に示す断面工程図を
参照しながら、上述する本発明の半導体装置製造方法を
説明する。
Hereinafter, the above-described method of manufacturing a semiconductor device according to the present invention will be described with reference to sectional process diagrams shown in FIGS.

【0028】図1(a)を参照し、符号12は、ウェハー
状態のシリコン基板等の半導体基板を示しており、図中
上側の面にトランジスタ等の電気素子(図示せず)が多数
形成されている。その電気素子が形成された面を第1の
面とすると、該第1の面上には、絶縁膜14が形成され
ており、絶縁膜14上には、アルミニウム薄膜が全面成
膜された後、パターニングされ、幅狭の内部配線16
と、大面積の金属パッド20が形成されている。
Referring to FIG. 1A, reference numeral 12 denotes a semiconductor substrate such as a silicon substrate in a wafer state, and a large number of electric elements (not shown) such as transistors are formed on the upper surface in the figure. ing. Assuming that the surface on which the electric element is formed is a first surface, an insulating film 14 is formed on the first surface, and an aluminum thin film is entirely formed on the insulating film 14. , Patterned, narrow internal wiring 16
, A large area metal pad 20 is formed.

【0029】更に、絶縁膜14、内部配線16及び金属
パッド20表面には、絶縁膜(パッシベーション膜)18
が形成されている。
Further, an insulating film (passivation film) 18 is formed on the surface of the insulating film 14, the internal wiring 16 and the metal pad 20.
Are formed.

【0030】ここでは、内部配線16及び金属パッド2
0は1層のアルミニウム薄膜から形成される。尚、この
配線16及び金属パッド20は、アルミニウム1層のも
のに限定されず、アルミニウムの下層にポリ・シリコ
ン、タングステン、チタン等の膜のうち1種または複数
が形成された多層構造、あるいはアルミニウムにかえて
銅を用いて形成することもできる。さらに、最上層の絶
縁膜を層間絶縁膜とし、その表面に更に内部配線を積層
させ、多層構造の内部配線を形成してもよい。
Here, the internal wiring 16 and the metal pad 2
0 is formed from a single-layer aluminum thin film. The wiring 16 and the metal pad 20 are not limited to those having a single layer of aluminum. A multilayer structure in which one or a plurality of films of polysilicon, tungsten, titanium, or the like is formed under aluminum, or aluminum. Instead, it can be formed using copper. Further, the uppermost insulating film may be used as an interlayer insulating film, and an internal wiring may be further laminated on the surface thereof to form an internal wiring having a multilayer structure.

【0031】そのような内部配線16により、半導体基
板12に形成された電気素子は相互に接続されており、
それらが形成する電気回路は、同様に、内部配線16に
よって金属パッド20に接続されている。
The electric elements formed on the semiconductor substrate 12 are connected to each other by such an internal wiring 16,
The electric circuits formed by them are likewise connected to the metal pads 20 by the internal wiring 16.

【0032】この半導体基板12の第1の面とは反対側
の第2の面側(裏面側)に、CVD法(Chemical Vapor De
position:化学気相成長法)等により、シリコン酸化膜
等の絶縁膜24を全面成膜し(図1(b))、続いて、フォ
トリソグラフィー工程により、その絶縁膜24の上に所
定パターンのレジスト膜32を形成する(図1(c))。
On the second surface (back surface) of the semiconductor substrate 12 opposite to the first surface, a CVD (Chemical Vapor Deposition) method is used.
position: a chemical vapor deposition method) or the like, an insulating film 24 such as a silicon oxide film is formed on the entire surface (FIG. 1B), and then a predetermined pattern is formed on the insulating film 24 by a photolithography process. A resist film 32 is formed (FIG. 1C).

【0033】このレジスト膜32は、金属パッド32の
裏面直下位置に、金属パッド32よりも小径の開口部が
形成されており、その開口部底面に露出する絶縁膜24
を、湿式もしくはプラズマ等によりエッチング除去し、
続けて、半導体基板12をエッチングし、スルーホール
22を開孔させる(図1(d))。
The resist film 32 has an opening having a diameter smaller than that of the metal pad 32 at a position directly below the rear surface of the metal pad 32, and the insulating film 24 exposed at the bottom of the opening.
Is removed by wet or plasma etching,
Subsequently, the semiconductor substrate 12 is etched to form a through hole 22 (FIG. 1D).

【0034】なお、そのエッチングは、プラズマによる
異方性ドライエッチングが、最も精度良くスルーホール
22を形成することができ、また、半導体基板12をエ
ッチングする際に、絶縁膜14がストッパーとなって、
エッチングの縦方向の進行がを自動的に停止させること
ができるので好ましい。
In the etching, anisotropic dry etching using plasma can form the through-hole 22 with the highest accuracy. When the semiconductor substrate 12 is etched, the insulating film 14 serves as a stopper. ,
This is preferable because the vertical progress of the etching can be automatically stopped.

【0035】この場合、スルーホール22底面の金属パ
ッド20上では、絶縁膜14表面が露出されているが、
スルーホール22の側壁には、半導体基板12が露出し
ている。
In this case, the surface of the insulating film 14 is exposed on the metal pad 20 on the bottom surface of the through hole 22.
The semiconductor substrate 12 is exposed on the side wall of the through hole 22.

【0036】次いで、感光性レジスト32を剥離除去し
(図1(e))、CVD法等により、半導体基板12の第2
の面側にシリコン酸化膜等の絶縁膜26を形成すると、
スルーホール22の側壁が絶縁膜26によって覆われる
(図1(f))。
Next, the photosensitive resist 32 is peeled and removed.
(FIG. 1E), the second semiconductor substrate 12 is formed by a CVD method or the like.
When an insulating film 26 such as a silicon oxide film is formed on the surface side of
The side wall of the through hole 22 is covered with the insulating film 26
(FIG. 1 (f)).

【0037】このとき、第2の面及び金属パッド20上
では、2層の絶縁膜14、26によって覆われるこの状
態では、スルーホール22底面の金属パッド20上に
は、2層の絶縁膜14、26が積層された状態になって
おり、また、シリコン基板12の第2の面側でも、2層
の絶縁膜24、26が積層された状態になっている。
At this time, the second surface and the metal pad 20 are covered by the two layers of insulating films 14 and 26. In this state, the two layers of the insulating film 14 , 26 are stacked, and also on the second surface side of the silicon substrate 12, two layers of insulating films 24, 26 are stacked.

【0038】なお、スルーホール22の内径にもよる
が、内径が小さくなるにしたがって、スルーホール22
の底部(絶縁膜14の下)に堆積される絶縁膜26の厚さ
は、半導体基板12の第2の面やスルーホール22の側
壁面と比べて薄くなるのが一般的である。
Although depending on the inner diameter of the through hole 22, the smaller the inner diameter, the smaller the through hole 22.
Is generally thinner than the second surface of the semiconductor substrate 12 or the side wall surface of the through hole 22.

【0039】続いて、プラズマエッチングにより、スル
ーホール22の側壁面に形成された絶縁膜26を残るよ
うに、絶縁膜26を異方性エッチングし、スルーホール
22底面の2層の絶縁膜26、14を除去すると、金属
パッド20底面が露出される(図2(g))。
Subsequently, the insulating film 26 is anisotropically etched by plasma etching so that the insulating film 26 formed on the side wall surface of the through hole 22 is left. When the 14 is removed, the bottom surface of the metal pad 20 is exposed (FIG. 2G).

【0040】半導体基板12の第2の面上に積層された
絶縁膜24、26の膜厚は、金属パッド20底面上に積
層された絶縁膜26、14よりも厚いので、スルーホー
ル22側壁の絶縁膜26ばかりでなく、第2の面上のス
ルーホール22を除いた部分にも絶縁膜24、26は残
る。特に、スルーホール22が小径の場合、スルーホー
ル22の開口後、形成される絶縁膜26は、スルーホー
ル22底面で薄いので、金属パッド20底面が露出する
程度のエッチングでは、第2の面上に形成された絶縁膜
26は残る。
The thickness of the insulating films 24 and 26 stacked on the second surface of the semiconductor substrate 12 is larger than the thickness of the insulating films 26 and 14 stacked on the bottom surface of the metal pad 20. The insulating films 24 and 26 remain not only in the insulating film 26 but also in a portion other than the through hole 22 on the second surface. In particular, when the through hole 22 has a small diameter, the insulating film 26 formed after the opening of the through hole 22 is thin on the bottom surface of the through hole 22. The insulating film 26 formed on the substrate remains.

【0041】なお、本発明においては、半導体基板12
の裏面に堆積した絶縁膜24,26のうち、第2の面側
では、少なくともスルーホール22開口前に形成された
絶縁膜24が残ればよく、開口後に形成された絶縁膜2
6は除去されても差し支えはない。
In the present invention, the semiconductor substrate 12
Of the insulating films 24 and 26 deposited on the back surface of the second surface, at least the insulating film 24 formed before the opening of the through hole 22 should remain on the second surface side.
6 can be removed.

【0042】絶縁膜を確実に残す場合には、図1(f)に
示す半導体装置において、パターニングしたレジスト膜
を形成し、スルーホール22開口後に形成した絶縁膜2
6の第2の面上の部分を保護した状態で、スルーホール
22内の異方性エッチングを行うとよい。
To ensure that the insulating film remains, in the semiconductor device shown in FIG. 1F, a patterned resist film is formed, and the insulating film 2 formed after the opening of the through hole 22 is formed.
It is preferable to perform anisotropic etching in the through hole 22 while protecting the portion on the second surface of No. 6.

【0043】このように、金属パッド20底面を露出さ
せた後、スパッタリング法や蒸着法により、半導体基板
12の第2の面側に金属膜28を全面成膜する(図2
(h))。
After the bottom surface of the metal pad 20 is exposed, a metal film 28 is entirely formed on the second surface side of the semiconductor substrate 12 by a sputtering method or a vapor deposition method (FIG. 2).
(h)).

【0044】次に、その金属膜28上にパターニングし
たレジスト膜34を形成する(図2(i))。このレジスト
膜34のスルーホール22上には開口部が設けられてお
り、従って、スルーホール22底面の金属膜28だけが
露出している。
Next, a patterned resist film 34 is formed on the metal film 28 (FIG. 2 (i)). An opening is provided on the through hole 22 of the resist film 34, so that only the metal film 28 on the bottom surface of the through hole 22 is exposed.

【0045】次に、必要に応じ、半導体基板12の第1
の面側に、ワックス膜等の保護膜を形成した後(ここで
は保護膜は形成しない。)、メッキ液に浸漬すると、ス
ルーホール22の底面に露出する金属膜28表面に金属
(導電性物質)が析出し、その金属によってスルーホール
22内が充填される。メッキ時間の管理により、スルー
ホール22充填後も析出を続行させると、析出金属が第
2の面から突出し、バンプ30が形成される(図2
(j))。
Next, if necessary, the first
After a protective film such as a wax film is formed on the surface of the metal film 28 (a protective film is not formed here), when immersed in a plating solution, the surface of the metal film 28
(Conductive substance) is deposited, and the inside of the through hole 22 is filled with the metal. If the deposition is continued after filling the through holes 22 by controlling the plating time, the deposited metal protrudes from the second surface, and the bumps 30 are formed (FIG. 2).
(j)).

【0046】次いで、レジスト膜34と金属膜28とを
この順に除去すると、半導体装置10が得られる(図2
(k))。なお、半導体基板12表面にワックス等の保護
膜が形成されている場合には、そのワックスも溶剤等を
用いて除去する。
Next, when the resist film 34 and the metal film 28 are removed in this order, the semiconductor device 10 is obtained.
(k)). When a protective film such as wax is formed on the surface of the semiconductor substrate 12, the wax is also removed using a solvent or the like.

【0047】そして、チップに分割すると、半導体装置
10のバンプ30をリードや導電パターンに接続させる
ことができるようになる。
When the semiconductor device 10 is divided into chips, the bumps 30 of the semiconductor device 10 can be connected to leads or conductive patterns.

【0048】以上説明したように、本発明の半導体装置
製造方法を用いれば、金属パッド20底面下にバンプ3
0を形成できるので、第2の面側をリードや導体パター
ン向け、バンプを接続させることで、内部回路を外部回
路に接続させることができる。その場合、第1の面側に
は遮蔽物がないので、CCD等の受光素子に適してい
る。
As described above, according to the semiconductor device manufacturing method of the present invention, the bump 3
Since 0 can be formed, the internal circuit can be connected to an external circuit by connecting the second surface side to a lead or a conductor pattern and connecting a bump. In that case, since there is no shield on the first surface side, it is suitable for a light receiving element such as a CCD.

【0049】また、上記メッキにより、半田等の低融点
金属を析出させると、熱処理によりバンプ30が溶解
し、リードや導体パターンに接続される。析出金属が銅
であり、バンプ30が銅で構成されている場合には、異
方導電性フィルムを用いて導体パターンやリードに接続
させることもできる。
When a low-melting-point metal such as solder is deposited by the above plating, the bump 30 is melted by heat treatment, and the bump 30 is connected to a lead or a conductor pattern. When the deposited metal is copper and the bump 30 is made of copper, the bump 30 can be connected to a conductor pattern or a lead using an anisotropic conductive film.

【0050】なお、メッキ法は、電解メッキ、無電解メ
ッキ等の湿式メッキを用いることができ、その他、スル
ーホール内を導電性物質で充填できる方法であれば、本
発明に用いることができる。
As the plating method, wet plating such as electrolytic plating and electroless plating can be used, and any other method that can fill the inside of the through hole with a conductive substance can be used in the present invention.

【0051】例えば導電性物質から成るボールをスルー
ホール22開口部に配置し、溶融させて、スルーホール
22内を導電性物質で充填してもよい。
For example, a ball made of a conductive material may be arranged in the opening of the through hole 22, melted, and the inside of the through hole 22 may be filled with the conductive material.

【0052】そのような半導体装置製造方法を、図3
(g)、(l)、(m)に示す断面工程図を用いて説明する。
FIG. 3 shows a method of manufacturing such a semiconductor device.
This will be described with reference to cross-sectional process diagrams shown in (g), (l), and (m).

【0053】図3(g)は、図2(g)と同じ状態、すなわ
ち、図1(a)の状態から、図1(f)及び図2(g)までの
各工程を経た半導体基板12を示しており、この半導体
基板12は、スルーホール22の底部の絶縁膜14がエ
ッチング除去され、スルーホール22底面に、金属パッ
ド20の底面が露出されている。
FIG. 3 (g) shows the same state as that of FIG. 2 (g), that is, the state of FIG. In the semiconductor substrate 12, the insulating film 14 at the bottom of the through hole 22 is removed by etching, and the bottom of the metal pad 20 is exposed at the bottom of the through hole 22.

【0054】この状態から、半導体基板12の第2の面
側を上方に向け、半田等の低融点金属で構成されたボー
ル36をスルーホール22の開口部上に配置する(図3
(h))。
In this state, the ball 36 made of a low melting point metal such as solder is placed on the opening of the through hole 22 with the second surface side of the semiconductor substrate 12 facing upward (FIG. 3).
(h)).

【0055】その状態でボール36を比較的低温で熱処
理し、ボール36を溶融させると、その溶融物がスルー
ホール22の内部に流れ込む。次いで、冷却すると、ス
ルーホール22内は、ボール36を構成する低融点金属
によって充填される。
In this state, when the ball 36 is heat-treated at a relatively low temperature to melt the ball 36, the melt flows into the through hole 22. Next, upon cooling, the inside of the through hole 22 is filled with the low melting point metal constituting the ball 36.

【0056】ボール36の体積を、スルーホール22の
体積よりも大きくしておくと、第2の面上に溶融物が盛
り上がり、冷却すると低融点金属から成るバンプ30'
が形成された半導体装置11が得られる(図3(i))。
If the volume of the ball 36 is larger than the volume of the through hole 22, the melt rises on the second surface, and when cooled, the bump 30 'made of a low melting point metal.
Is obtained (FIG. 3 (i)).

【0057】この半導体装置11をチップに分割する
と、バンプ30'をリードや導電パターンに接続させる
ことができるようになる。
When the semiconductor device 11 is divided into chips, the bumps 30 'can be connected to leads and conductive patterns.

【0058】なお、露出した金属パッド20底面に、半
田等との密着性がよい金属膜を形成し、半導体基板12
の第2面上の不要部分を除去した後、ボール36の溶融
物を流し込むと、電気的、機械的な接続が確実になって
都合がよい。
A metal film having good adhesion to solder or the like is formed on the exposed bottom surface of the metal pad 20 so that the semiconductor substrate 12
After the unnecessary portion on the second surface is removed, if the melt of the ball 36 is poured, electrical and mechanical connection is ensured, which is convenient.

【0059】以上説明したように、本発明の半導体装置
では、半導体基板の素子形成面側には遮蔽物が無いた
め、例えば医療用のCCD等の撮像デバイスにおいて有
効面積を広くでき、光の乱反射の無い高性能の素子を製
造することができる。
As described above, in the semiconductor device of the present invention, since there is no shield on the element forming surface side of the semiconductor substrate, for example, an effective area can be increased in an imaging device such as a CCD for medical use, and irregular reflection of light can be achieved. It is possible to manufacture a high-performance device without any problem.

【0060】また、本発明の半導体装置およびその製造
方法によれば、半導体基板の素子形成面の全面を表面保
護膜で覆うことができるため、半導体装置の信頼性を向
上させることができる。
Further, according to the semiconductor device and the method for manufacturing the same of the present invention, the entire surface of the element formation surface of the semiconductor substrate can be covered with the surface protective film, so that the reliability of the semiconductor device can be improved.

【0061】更にまた、半導体基板の裏面側に外部との
接続端子となるバンプを設けているため、組立工程でワ
イヤーボンドが不要であり、チップに分割された半導体
基板と同等のサイズでパッケージに封止することもでき
る。従って、本発明の半導体装置は極めて小型である。
Further, since bumps serving as connection terminals with the outside are provided on the back side of the semiconductor substrate, wire bonding is not required in the assembling process, and a package having the same size as the semiconductor substrate divided into chips is formed in a package. It can also be sealed. Therefore, the semiconductor device of the present invention is extremely small.

【0062】また、半導体基板の裏面側にバンプを形成
し、封止するため組み立てが容易である。
Further, bumps are formed on the back surface of the semiconductor substrate and sealed, so that assembly is easy.

【0063】なお、本発明のいう半導体装置とは、ウェ
ハー状態のものはもちろん、チップ状に分割したもの、
更にそれをパッケージに封止したものも含まれる。他の
種類の半導体基板と一緒に封止されていてもよい。
The semiconductor device according to the present invention includes not only a semiconductor device in a wafer state but also a semiconductor device divided into chips.
In addition, those in which it is sealed in a package are also included. It may be sealed together with another type of semiconductor substrate.

【0064】また、上記はメッキ法により金属を析出さ
せ、また、ボール34を用いてスルーホール22を充填
させていたが、他の方法によってスルーホール22内を
金属又は導電性物質で充填する半導体装置製造方法、及
び半導体装置も本発明に含まれる。
In the above, the metal is deposited by the plating method, and the through hole 22 is filled with the ball 34. However, the semiconductor in which the inside of the through hole 22 is filled with the metal or the conductive material by another method. A device manufacturing method and a semiconductor device are also included in the present invention.

【0065】[0065]

【発明の効果】半導体基板の裏面側をバンプ法によりリ
ードや導電パターンに接続できるため、半導体基板と同
程度の大きさでパッケージに封止することができる。ま
た、素子形成面上にボンディングワイヤー等の遮蔽物が
ないので、医療用のCCD等の撮像デバイスに特に有効
である。
According to the present invention, the back side of the semiconductor substrate can be connected to leads or conductive patterns by a bump method, so that it can be sealed in a package with a size similar to the semiconductor substrate. Further, since there is no shield such as a bonding wire on the element forming surface, it is particularly effective for an imaging device such as a medical CCD.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(f):本発明の一例の半導体装置製造方
法の工程図の前半
1 (a) to 1 (f): First half of a process chart of a semiconductor device manufacturing method according to an example of the present invention.

【図2】(g)〜(k):その工程図の後半FIG. 2 (g) to (k): latter half of the process diagram

【図3】(g)、(l)、(m):本発明の他の半導体装置製
造方法の工程図
FIGS. 3 (g), (l), and (m): process diagrams of another method for manufacturing a semiconductor device of the present invention.

【図4】(a)、(b):従来の半導体装置の一例4A and 4B are examples of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

10……半導体装置 12……半導体基板 20…
…金属パッド 22……スルーホール 26……絶
縁膜 28……金属膜 30,30’……バンプ
10 semiconductor device 12 semiconductor substrate 20
... Metal pad 22 ... Through hole 26 ... Insulating film 28 ... Metal film 30, 30 '... Bump

フロントページの続き Fターム(参考) 4M118 AA05 AA10 AB01 BA10 HA31 HA33 5F033 JJ07 JJ11 KK04 KK08 KK18 KK19 NN06 PP15 PP19 PP27 PP28 QQ07 QQ10 QQ12 QQ16 QQ21 QQ25 QQ30 QQ35 QQ37 QQ73 RR04 SS11 TT02 TT07 XX00 Continued on front page F-term (reference) 4M118 AA05 AA10 AB01 BA10 HA31 HA33 5F033 JJ07 JJ11 KK04 KK08 KK18 KK19 NN06 PP15 PP19 PP27 PP28 QQ07 QQ10 QQ12 QQ16 QQ21 QQ25 QQ30 QQ35 QQ37 QQ73 RR04 TT04

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】半導体基板と、 前記半導体基板の第1の面側に形成された金属パッドと
を有する半導体装置であって、 前記半導体基板の前記金属パッド底面下には、前記第1
の面とは反対側の第2の面に開口するスルーホールが設
けられた半導体装置。
1. A semiconductor device comprising: a semiconductor substrate; and a metal pad formed on a first surface side of the semiconductor substrate, wherein the semiconductor substrate has a first surface under a bottom surface of the metal pad.
A semiconductor device provided with a through-hole opening on a second surface opposite to the surface.
【請求項2】前記スルーホール内には、前記金属パッド
底面と電気的に接続された導電性物質が充填された請求
項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein said through hole is filled with a conductive material electrically connected to a bottom surface of said metal pad.
【請求項3】少なくとも前記スルーホール側壁には絶縁
膜が形成され、 前記導電性物質と前記半導体基板とは電気的に絶縁され
た請求項2記載の半導体装置。
3. The semiconductor device according to claim 2, wherein an insulating film is formed on at least the side wall of the through hole, and the conductive material is electrically insulated from the semiconductor substrate.
【請求項4】前記スルーホール内に充填された導電性物
質により、前記第2の面側に突出するバンプが形成され
た請求項2又は請求項3のいずれか1項記載の半導体装
置。
4. The semiconductor device according to claim 2, wherein a bump protruding toward said second surface is formed by a conductive substance filled in said through hole.
【請求項5】第1、第2の面を有する半導体基板の、前
記第1の面側に金属パッドを形成し、 前記半導体基板の前記第2の面側から該半導体基板を部
分的にエッチングし、前記金属パット底面位置にスルー
ホールを形成する半導体装置製造方法。
5. A semiconductor substrate having first and second surfaces, a metal pad is formed on the first surface side of the semiconductor substrate, and the semiconductor substrate is partially etched from the second surface side of the semiconductor substrate. And forming a through hole at the bottom of the metal pad.
【請求項6】少なくとも前記スルーホール側壁に絶縁膜
を形成する請求項5記載の半導体装置製造方法。
6. The method according to claim 5, wherein an insulating film is formed on at least the side wall of the through hole.
【請求項7】前記スルーホール内に前記金属パッド底面
を露出させた後、金属を析出させ、前記スルーホールを
充填する請求項5又は請求項6記載の半導体装置製造方
法。
7. The method according to claim 5, wherein after exposing the bottom surface of the metal pad in the through hole, a metal is deposited to fill the through hole.
【請求項8】前記スルーホール内に前記金属パッド底面
を露出させた後、金属膜を形成し、前記金属膜表面に前
記金属を析出させる請求項7記載の半導体装置製造方
法。
8. The method of manufacturing a semiconductor device according to claim 7, wherein after exposing the bottom surface of the metal pad in the through hole, a metal film is formed, and the metal is deposited on the surface of the metal film.
【請求項9】前記スルーホール内に溶融した低融点の金
属を流し込み、該スルーホール内を前記低融点の金属で
充填する請求項5又は請求項6記載の半導体装置製造方
法。
9. The method of manufacturing a semiconductor device according to claim 5, wherein a molten metal having a low melting point is poured into said through-hole, and said through-hole is filled with said metal having a low melting point.
JP10368958A 1998-12-25 1998-12-25 Semiconductor device and method of producing the same Withdrawn JP2000195861A (en)

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Country Link
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