JP3648585B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP3648585B2
JP3648585B2 JP15168997A JP15168997A JP3648585B2 JP 3648585 B2 JP3648585 B2 JP 3648585B2 JP 15168997 A JP15168997 A JP 15168997A JP 15168997 A JP15168997 A JP 15168997A JP 3648585 B2 JP3648585 B2 JP 3648585B2
Authority
JP
Japan
Prior art keywords
semiconductor device
connection pad
connection pads
semiconductor substrate
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP15168997A
Other languages
Japanese (ja)
Other versions
JPH10335337A (en
Inventor
充彦 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP15168997A priority Critical patent/JP3648585B2/en
Publication of JPH10335337A publication Critical patent/JPH10335337A/en
Application granted granted Critical
Publication of JP3648585B2 publication Critical patent/JP3648585B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
この発明は半導体装置及びその製造方法に関する。
【０００２】
【従来の技術】
例えば、ＣＣＤ(charge coupled device)等の半導体装置は回路基板上に搭載される場合が多い。図１２は従来のこのような半導体装置を回路基板上に搭載したものの一例を示したものである。この場合の半導体装置１はＣＣＤであり、上面中央部に光センサ機能部２が突出した状態で形成されたシリコン基板３を備えている。光センサ機能部２を除くシリコン基板３の上面には初期酸化膜４が形成されている。初期酸化膜４の上面周辺部には複数の接続パッド５が光センサ機能部２の複数の入出力部（図示せず）に引き回し線６を介して接続されて形成されている。接続パッド５及び引き回し線６を含む初期酸化膜４の上面及び光センサ機能部２の上面には保護膜７が形成されている。この場合、保護膜７の接続パッド５の中央部に対応する部分には開口部８が形成され、接続パッド５の中央部が開口部８を介して露出されている。一方、回路基板９の上面の所定の箇所は半導体装置搭載エリア１０となっている。回路基板９の上面において半導体装置搭載エリア１０の外周部には複数の接続端子１１が設けられている。そして、半導体装置１のシリコン基板３は回路基板９の半導体装置搭載エリア１０に接着剤１２を介して接着され、半導体装置１の接続パッド５と回路基板９の接続端子１１とがボンディングワイヤ１３によって接続されている。
【０００３】
ところで、半導体装置１を回路基板９上に搭載する場合、例えばフリップチップボンディング方式によって搭載する方法もあるが、上述したように、半導体装置１の接続パッド５を上面側に露出させ、ボンディングワイヤ１３を用いたワイヤボンディング方式によって搭載している。この理由は、半導体装置１の光センサ機能部２を上面側に露出させるためである。
【０００４】
【発明が解決しようとする課題】
このように、半導体装置１を回路基板９上にボンディングワイヤ１３を用いたワイヤボンディング方式によって搭載しているので、回路基板９上において半導体装置１を実質的に搭載するためのエリアが図１２において符号１４で示すように接続端子１１を含むエリアとなり、すなわち実質的な半導体装置搭載エリア１４の平面サイズが半導体装置１自体の平面サイズよりも大きくなり、これに応じて回路基板９の平面サイズも大きくなり、全体的に大型化するという問題があった。
この発明の課題は、半導体装置の実質的な搭載エリアを小さくすることである。
【０００５】
【課題を解決するための手段】
請求項１記載の発明に係る半導体装置は、一の面に複数の第１の接続パッドを備えた半導体基板と、該半導体基板の他の面からその内部に前記第１の接続パッドに達するように形成された複数の開口部と、該開口部内に前記第１の接続パッドと接続された状態で形成され、メッキによって形成された少なくとも２種類の金属層からなる複数の内部導通部と、前記半導体基板の他の面に前記内部導通部と接続された状態で形成された複数の第２の接続パッドとを具備するものである。請求項６記載の発明に係る半導体装置の製造方法は、一の面に複数の第１の接続パッドを備えた半導体基板の他の面に、前記第１の接続パッドに対応する箇所に開口部を有する、少なくとも２層構造を有する多層金属膜を形成し、該多層金属膜の前記開口部を介して前記半導体基板をエッチングして、前記半導体基板の他の面からその内部に複数の開口部を前記第１の接続パッドに達するように形成し、前記多層金属膜を剥離した後、メッキにより、少なくとも２種類の金属層を前記開口部内のみに形成して、前記開口部内に複数の内部導通部を前記第１の接続パッドに接続させて形成し、前記半導体基板の他の面に複数の第２の接続パッドを前記内部導通部に接続させて形成するようにしたものである。
【０００６】
この発明によれば、一の面に複数の第１の接続パッドを備えた半導体基板の他の面に複数の第２の接続パッドが第１の接続パッドに内部導通部を介して接続されて形成されているので、半導体装置の一の面を上面側に露出させた状態で半導体装置を回路基板上に搭載する場合、半導体装置の他の面の第２の接続パッドを回路基板の接続端子に対向させることができ、この結果半導体装置を回路基板上にフリップチップボンディング方式と同じような方式によって搭載することができ、したがって半導体装置の実質的な搭載エリアの平面サイズを半導体装置自体の平面サイズとほぼ同じにすることができ、すなわち半導体装置の実質的な搭載エリアを小さくすることができる。
【０００７】
【発明の実施の形態】
図１〜図１１はそれぞれこの発明の一実施形態における半導体装置の各製造工程を示したものである。そこで、これらの図を順に参照しながら、この実施形態の半導体装置の構造についてその製造方法と併せて説明する。
【０００８】
まず、図１に示すように、シリコン基板（半導体基板）２１の上面中央部に光センサ機能部２２が突出した状態で形成され、光センサ機能部２２を除くシリコン基板２１の上面に酸化シリコンからなる初期酸化膜２３が形成され、初期酸化膜２３の上面の所定の複数箇所にアルミニウム等からなる接続パッド（第１の接続パッド）２４が光センサ機能部２２の複数の入出力部（図示せず）に引き回し線２５を介して接続されて形成され、接続パッド２４及び引き回し線２５を含む初期酸化膜２３の上面及び光センサ機能部２２の上面に酸化シリコン等からなる保護膜２６が形成され、その上面に金属多層膜２７が形成され、シリコン基板２１の下面に酸化シリコンからなる初期酸化膜２８が形成され、その下面に金属多層膜２９が形成されたものを用意する。この場合、両金属多層膜２７、２９は、後で説明するように、シリコン基板２１をエッチングする際のマスク等を形成するためのものであり、クロム、チタン、タングステン等からなる内層と金等からなる外層との２層構造となっているが３層以上であってもよい。
【０００９】
次に、図２に示すように、上側の金属多層膜２７の上面に保護膜３０を形成し、下側の金属多層膜２９の下面に、接続パッド２３に対応する部分に開口部３１ａを有するレジストパターン３１を形成する。この場合、保護膜３０はレジストパターン３１と同一の材料からなっているが、ワニス等であってもよい。
【００１０】
次に、図３に示すように、レジストパターン３１をマスクとして、下側の金属多層膜２９をエッチングし、次いでフッ化水素系のエッチング液を用いて下側の初期酸化膜２８をエッチングする。すると、レジストパターン３１の開口部３１ａに対応する部分における下側の金属多層膜２９及び下側の初期酸化膜２８に開口部２９ａ、２８ａが形成される。この場合、上側の金属多層膜２７は、保護膜３０によって覆われているので、エッチングされない。この後、保護膜３０及びレジストパターン３１を剥離する。
【００１１】
次に、図４に示すように、下側の金属多層膜２９をマスクとして水酸化カリウム系のエッチング液を用いてシリコン基板２１をエッチングすると、下側の金属多層膜２９の開口部２９ａに対応する部分におけるシリコン基板２１に開口部２１ａが形成される。
【００１２】
次に、図５に示すように、下側の金属多層膜２９をマスクとして上側の初期酸化膜２３をエッチングすると、下側の金属多層膜２９の開口部２９ａに対応する部分における上側の初期酸化膜２３に開口部２３ａが形成される。この場合、保護膜２６は上側の金属多層膜２７によって覆われているので、エッチングされない。そして、この状態では、開口部２９ａ、２８ａ、２１ａ、２３ａを介して上側の接続パッド２４が下面側に露出される。この後、上側及び下側の金属多層膜２７、２９を剥離する。
【００１３】
次に、図６に示すように、ジンケート処理を施すことにより、開口部２８ａ、２１ａ、２３ａを介して露出された上側の接続パッド２４の下面に形成された図示しない自然酸化膜をエッチングして除去するとともに、アルミニウムと亜鉛とを置換させて、上側の接続パッド２４の下面に亜鉛核３２を形成する。
【００１４】
次に、図７に示すように、開口部２８ａ、２１ａ、２３ａを介して露出された亜鉛核３２の下面に無電解メッキによりニッケルメッキ層３３を膜厚数μｍ程度に形成する。
【００１５】
次に、図８に示すように、開口部２８ａ、２１ａを介して露出されたニッケルメッキ層３３の下面に無電解メッキにより銅メッキ層３４を下側の初期酸化膜２８の下面まで形成する。これにより、開口部２８ａ、２１ａ、２３ａ内には亜鉛核３２とニッケルメッキ層３３と銅メッキ層３４とからなる内部導通部が形成される。
【００１６】
次に、図９に示すように、銅メッキ層３４及び下側の初期酸化膜２８の下面にスパッタ法あるいは真空蒸着法等によって接続パッド形成用層３５を形成する。この場合、接続パッド形成用層３５は、クロム、チタン、チタン−タングステン合金、モリブデン、タングステン等からなる接着層と、銅、ニッケル、白金、パラジウム等からなるバリア層と、金等からなる表面保護層との３層構造となっている。次に、接続パッド形成用層３５の下面にレジストパターン３６を所定のパターンに形成する。
【００１７】
次に、図１０に示すように、レジストパターン３６をマスクとして接続パッド形成用層３５の不要な部分をエッチングする。すると、レジストパターン３６下に下側の接続パッド（第２の接続パッド）３７がマトリックス状に形成されるとともに、図示していないが、この下側の接続パッド３７と銅メッキ層３４とを適宜に接続する引き回し線が形成される。この後、レジストパターン３６を剥離する。
【００１８】
次に、図１１に示すように、下側の初期酸化膜２８の下面において下側の接続パッド３７の中央部を除く部分に保護膜３８を形成する。この状態では、下側の接続パッド３７の中央部が保護膜３８に形成された開口部３８ａを介して露出される。次に、開口部３８ａを介して露出された下側の接続パッド３７の下面にはんだからなる突起電極３９を形成する。かくして、半導体装置が製造される。
【００１９】
このようにして製造された半導体装置では、上面に複数の上側の接続パッド２４を備えたシリコン基板２１の下面に複数の下側の接続パッド３７が上側の接続パッド２４に亜鉛核３２、ニッケルメッキ層３３及び銅メッキ層３４からなる内部導通部を介して接続されて形成された構造となっている。このため、この半導体装置の上面を上面側に露出させた状態でこの半導体装置を回路基板（図示せず）上に搭載する場合、この半導体装置の下面の下側の接続パッド３７を回路基板の接続端子に対向させることができる。この結果、この半導体装置を回路基板上にフリップチップボンディング方式と同じような方式によって搭載することができる。したがって、この半導体装置の実質的な搭載エリアの平面サイズをこの半導体装置自体の平面サイズとほぼ同じにすることができ、すなわちこの半導体装置の実質的な搭載エリアを小さくすることができ、ひいては回路基板の平面サイズを小さくすることができる。また、上側の接続パッド２４を保護膜２６で覆っているので、上側の接続パッド２４を保護することができる。
【００２０】
なお、上記実施形態では、開口部２８ａ、２１ａ、２３ａを介して露出された上側の接続パッド２４の下面にジンケート処理を施して、アルミニウムと亜鉛とを置換させた後、無電解メッキによりニッケルメッキ層３３を形成した場合について説明したが、これに限らず、ジンケート処理を行わずに、上側の接続パッド２４の下面に無電解メッキにより直接ニッケルメッキ層３３を形成するようにしてもよい。
また、上記実施形態では、内部導通部をジンケート処理及び無電解メッキにより形成した場合について説明したが、これに限らず、内部導通部全体をスパッタ法等によって形成するようにしてもよい。
また、上記実施形態では、開口部２８ａ、２１ａ、２３ａをウエットエッチングによって形成した場合について説明したが、これに限らず、ドライエッチングによって形成するようにしてもよく、さらにエキシマレーザ等の照射によって形成するようにしてもよい。
【００２１】
【発明の効果】
以上説明したように、この発明によれば、一の面に複数の第１の接続パッドを備えた半導体基板の他の面に複数の第２の接続パッドが第１の接続パッドに内部導通部を介して接続されて形成されているので、半導体装置の一の面を上面側に露出させた状態で半導体装置を回路基板上に搭載する場合、半導体装置の他の面の第２の接続パッドを回路基板の接続端子に対向させることができ、この結果半導体装置を回路基板上にフリップチップボンディング方式と同じような方式によって搭載することができ、したがって半導体装置の実質的な搭載エリアの平面サイズを半導体装置自体の平面サイズとほぼ同じにすることができ、すなわち半導体装置の実質的な搭載エリアを小さくすることができ、ひいては回路基板の平面サイズを小さくすることができる。
【図面の簡単な説明】
【図１】この発明の一実施形態における半導体装置の製造に際し、シリコン基板上に初期酸化膜、接続パッド、保護膜及び金属多層膜を形成し、シリコン基板下に初期酸化膜及び金属多層膜を形成した状態の断面図。
【図２】同半導体装置の製造に際し、上側の金属多層膜の上面に保護膜を形成し、下側の金属多層膜の下面にレジストパターンを形成した状態の断面図。
【図３】同半導体装置の製造に際し、下側の初期酸化膜及び下側の金属多層膜に開口部を形成した状態の断面図。
【図４】同半導体装置の製造に際し、シリコン基板に開口部を形成した状態の断面図。
【図５】同半導体装置の製造に際し、上側の初期酸化膜に開口部を形成した状態の断面図。
【図６】同半導体装置の製造に際し、開口部内に亜鉛核を形成した状態の断面図。
【図７】同半導体装置の製造に際し、開口部内にニッケルメッキ層を形成した状態の断面図。
【図８】同半導体装置の製造に際し、開口部内に銅メッキ層を形成した状態の断面図。
【図９】同半導体装置の製造に際し、シリコン基板下に接続パッド形成用層及びレジストパターンを形成した状態の断面図。
【図１０】同半導体装置の製造に際し、シリコン基板下に下側の接続パッドを形成した状態の断面図。
【図１１】同半導体装置の製造に際し、下側の接続パッド下に突起電極を形成した状態の断面図。
【図１２】従来の半導体装置を回路基板上に搭載した状態の断面図。
【符号の説明】
２１ シリコン基板
２２ 光センサ機能部
２４ 上側の接続パッド
２１ａ、２３ａ、２８ａ 開口部
３２ 亜鉛核
３３ ニッケルメッキ層
３４ 銅メッキ層
３７ 下側の接続パッド[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof.
[0002]
[Prior art]
For example, a semiconductor device such as a CCD (charge coupled device) is often mounted on a circuit board. FIG. 12 shows an example in which such a conventional semiconductor device is mounted on a circuit board. The semiconductor device 1 in this case is a CCD, and includes a silicon substrate 3 formed in a state where the optical sensor function unit 2 protrudes at the center of the upper surface. An initial oxide film 4 is formed on the upper surface of the silicon substrate 3 excluding the optical sensor function unit 2. A plurality of connection pads 5 are formed on the periphery of the upper surface of the initial oxide film 4 to be connected to a plurality of input / output units (not shown) of the optical sensor function unit 2 through lead lines 6. A protective film 7 is formed on the upper surface of the initial oxide film 4 including the connection pads 5 and the lead wires 6 and the upper surface of the optical sensor function unit 2. In this case, an opening 8 is formed in a portion of the protective film 7 corresponding to the center of the connection pad 5, and the center of the connection pad 5 is exposed through the opening 8. On the other hand, a predetermined portion of the upper surface of the circuit board 9 is a semiconductor device mounting area 10. A plurality of connection terminals 11 are provided on the outer periphery of the semiconductor device mounting area 10 on the upper surface of the circuit board 9. The silicon substrate 3 of the semiconductor device 1 is bonded to the semiconductor device mounting area 10 of the circuit board 9 via an adhesive 12, and the connection pads 5 of the semiconductor device 1 and the connection terminals 11 of the circuit board 9 are bonded by bonding wires 13. It is connected.
[0003]
By the way, when the semiconductor device 1 is mounted on the circuit board 9, for example, there is a method of mounting by a flip chip bonding method. However, as described above, the connection pads 5 of the semiconductor device 1 are exposed to the upper surface side and the bonding wires 13 are exposed. It is mounted by wire bonding method using The reason for this is to expose the optical sensor function unit 2 of the semiconductor device 1 to the upper surface side.
[0004]
[Problems to be solved by the invention]
Thus, since the semiconductor device 1 is mounted on the circuit board 9 by the wire bonding method using the bonding wires 13, the area for mounting the semiconductor device 1 on the circuit board 9 is substantially the same as that shown in FIG. As shown by the reference numeral 14, the area including the connection terminal 11, that is, the substantial planar size of the semiconductor device mounting area 14 is larger than the planar size of the semiconductor device 1 itself, and the planar size of the circuit board 9 is accordingly increased. There was a problem that the size was increased and the overall size was increased.
An object of the present invention is to reduce a substantial mounting area of a semiconductor device.
[0005]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor device having a plurality of first connection pads on one surface and the first connection pads reaching from the other surface of the semiconductor substrate to the inside thereof. A plurality of openings formed in the plurality of openings, and a plurality of internal conductive portions formed of at least two types of metal layers formed by plating and connected to the first connection pads in the openings, A plurality of second connection pads formed in a state of being connected to the internal conductive portion on the other surface of the semiconductor substrate. According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device , wherein an opening is formed at a position corresponding to the first connection pad on the other surface of the semiconductor substrate having a plurality of first connection pads on one surface. A multilayer metal film having at least a two-layer structure is formed, the semiconductor substrate is etched through the openings of the multilayer metal film, and a plurality of openings are formed in the inside from the other surface of the semiconductor substrate. Is formed so as to reach the first connection pad, and after the multilayer metal film is peeled off, at least two kinds of metal layers are formed only in the opening by plating , and a plurality of internal continuity is formed in the opening. And a plurality of second connection pads are connected to the internal conductive portion on the other surface of the semiconductor substrate.
[0006]
According to the present invention, the plurality of second connection pads are connected to the first connection pad via the internal conductive portion on the other surface of the semiconductor substrate having the plurality of first connection pads on one surface. When the semiconductor device is mounted on the circuit board with one surface of the semiconductor device exposed to the upper surface side, the second connection pads on the other surface of the semiconductor device are connected to the connection terminals of the circuit board. As a result, the semiconductor device can be mounted on the circuit board by a method similar to the flip-chip bonding method, and therefore, the plane size of the substantial mounting area of the semiconductor device is set to the plane of the semiconductor device itself. The size can be made substantially the same, that is, the substantial mounting area of the semiconductor device can be reduced.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
1 to 11 show respective manufacturing steps of a semiconductor device according to an embodiment of the present invention. Therefore, the structure of the semiconductor device of this embodiment will be described together with its manufacturing method with reference to these drawings in order.
[0008]
First, as shown in FIG. 1, the optical sensor function part 22 is formed in a state where the optical sensor function part 22 protrudes from the center part of the upper surface of the silicon substrate (semiconductor substrate) 21, and the upper surface of the silicon substrate 21 excluding the optical sensor function part 22 The initial oxide film 23 is formed, and connection pads (first connection pads) 24 made of aluminum or the like are provided at a plurality of predetermined positions on the upper surface of the initial oxide film 23. And a protective film 26 made of silicon oxide or the like is formed on the upper surface of the initial oxide film 23 including the connection pad 24 and the routing line 25 and the upper surface of the optical sensor function unit 22. A metal multilayer film 27 is formed on the upper surface, an initial oxide film 28 made of silicon oxide is formed on the lower surface of the silicon substrate 21, and a metal multilayer film 29 is formed on the lower surface thereof. To prepare for. In this case, as will be described later, the two metal multilayer films 27 and 29 are for forming a mask or the like for etching the silicon substrate 21, and an inner layer made of chromium, titanium, tungsten or the like and gold or the like. Although it has a two-layer structure with an outer layer made of, it may be three or more layers.
[0009]
Next, as shown in FIG. 2, a protective film 30 is formed on the upper surface of the upper metal multilayer film 27, and an opening 31 a is formed on the lower surface of the lower metal multilayer film 29 in a portion corresponding to the connection pad 23. A resist pattern 31 is formed. In this case, the protective film 30 is made of the same material as the resist pattern 31, but may be varnish or the like.
[0010]
Next, as shown in FIG. 3, the lower metal multilayer film 29 is etched using the resist pattern 31 as a mask, and then the lower initial oxide film 28 is etched using a hydrogen fluoride-based etchant. As a result, openings 29 a and 28 a are formed in the lower metal multilayer film 29 and the lower initial oxide film 28 in the portion corresponding to the opening 31 a of the resist pattern 31. In this case, the upper metal multilayer film 27 is not etched because it is covered with the protective film 30. Thereafter, the protective film 30 and the resist pattern 31 are peeled off.
[0011]
Next, as shown in FIG. 4, when the silicon substrate 21 is etched using a potassium hydroxide-based etchant using the lower metal multilayer film 29 as a mask, it corresponds to the opening 29 a of the lower metal multilayer film 29. An opening 21a is formed in the silicon substrate 21 in the portion to be formed.
[0012]
Next, as shown in FIG. 5, when the upper initial oxide film 23 is etched using the lower metal multilayer film 29 as a mask, the upper initial oxidation in the portion corresponding to the opening 29a of the lower metal multilayer film 29 is performed. An opening 23 a is formed in the film 23. In this case, since the protective film 26 is covered with the upper metal multilayer film 27, it is not etched. In this state, the upper connection pad 24 is exposed to the lower surface side through the openings 29a, 28a, 21a, and 23a. Thereafter, the upper and lower metal multilayer films 27 and 29 are peeled off.
[0013]
Next, as shown in FIG. 6, a natural oxide film (not shown) formed on the lower surface of the upper connection pad 24 exposed through the openings 28a, 21a, 23a is etched by performing a zincate process. While removing, aluminum and zinc are replaced to form a zinc nucleus 32 on the lower surface of the upper connection pad 24.
[0014]
Next, as shown in FIG. 7, a nickel plating layer 33 is formed on the lower surface of the zinc nucleus 32 exposed through the openings 28a, 21a, 23a by electroless plating to a film thickness of about several μm.
[0015]
Next, as shown in FIG. 8, a copper plating layer 34 is formed up to the lower surface of the lower initial oxide film 28 by electroless plating on the lower surface of the nickel plating layer 33 exposed through the openings 28a and 21a. As a result, an internal conduction portion including the zinc nucleus 32, the nickel plating layer 33, and the copper plating layer 34 is formed in the openings 28a, 21a, and 23a.
[0016]
Next, as shown in FIG. 9, a connection pad forming layer 35 is formed on the lower surface of the copper plating layer 34 and the lower initial oxide film 28 by sputtering or vacuum deposition. In this case, the connection pad forming layer 35 includes an adhesive layer made of chromium, titanium, titanium-tungsten alloy, molybdenum, tungsten, etc., a barrier layer made of copper, nickel, platinum, palladium, etc., and a surface protection made of gold or the like. It has a three-layer structure with layers. Next, a resist pattern 36 is formed in a predetermined pattern on the lower surface of the connection pad forming layer 35.
[0017]
Next, as shown in FIG. 10, unnecessary portions of the connection pad forming layer 35 are etched using the resist pattern 36 as a mask. Then, lower connection pads (second connection pads) 37 are formed in a matrix under the resist pattern 36. Although not shown, the lower connection pads 37 and the copper plating layer 34 are appropriately connected. A lead wire connecting to is formed. Thereafter, the resist pattern 36 is peeled off.
[0018]
Next, as shown in FIG. 11, a protective film 38 is formed on the lower surface of the lower initial oxide film 28 except for the central portion of the lower connection pad 37. In this state, the central portion of the lower connection pad 37 is exposed through the opening 38 a formed in the protective film 38. Next, a bump electrode 39 made of solder is formed on the lower surface of the lower connection pad 37 exposed through the opening 38a. Thus, a semiconductor device is manufactured.
[0019]
In the semiconductor device thus manufactured, a plurality of lower connection pads 37 are formed on the lower surface of the silicon substrate 21 having a plurality of upper connection pads 24 on the upper surface, and zinc nuclei 32 and nickel plating are formed on the upper connection pads 24. In this structure, the layers 33 and the copper plating layer 34 are connected via an internal conduction portion. Therefore, when the semiconductor device is mounted on a circuit board (not shown) with the upper surface of the semiconductor device exposed to the upper surface side, the connection pads 37 on the lower surface of the semiconductor device are connected to the circuit board. It can be made to oppose a connection terminal. As a result, the semiconductor device can be mounted on the circuit board by a method similar to the flip chip bonding method. Therefore, the planar size of the substantial mounting area of the semiconductor device can be made substantially the same as the planar size of the semiconductor device itself, that is, the substantial mounting area of the semiconductor device can be reduced, and thus the circuit. The planar size of the substrate can be reduced. Further, since the upper connection pad 24 is covered with the protective film 26, the upper connection pad 24 can be protected.
[0020]
In the above embodiment, the lower surface of the upper connection pad 24 exposed through the openings 28a, 21a and 23a is subjected to a zincate treatment to replace aluminum and zinc, and then nickel plating is performed by electroless plating. Although the case where the layer 33 is formed has been described, the present invention is not limited thereto, and the nickel plating layer 33 may be directly formed on the lower surface of the upper connection pad 24 by electroless plating without performing the zincate process.
In the above embodiment, the case where the internal conductive portion is formed by zincate treatment and electroless plating has been described. However, the present invention is not limited thereto, and the entire internal conductive portion may be formed by sputtering or the like.
In the above-described embodiment, the case where the openings 28a, 21a, and 23a are formed by wet etching has been described. However, the present invention is not limited to this, and the openings 28a, 21a, and 23a may be formed by dry etching. You may make it do.
[0021]
【The invention's effect】
As described above, according to the present invention, a plurality of second connection pads are connected to the first connection pad on the other surface of the semiconductor substrate having a plurality of first connection pads on one surface. When the semiconductor device is mounted on the circuit board with one surface of the semiconductor device exposed to the upper surface side, the second connection pad on the other surface of the semiconductor device is formed. As a result, the semiconductor device can be mounted on the circuit board by a method similar to the flip chip bonding method, and thus the plane size of the substantial mounting area of the semiconductor device. Can be made substantially the same as the planar size of the semiconductor device itself, that is, the substantial mounting area of the semiconductor device can be reduced, and consequently the planar size of the circuit board can be reduced. Can.
[Brief description of the drawings]
FIG. 1 shows an initial oxide film, a connection pad, a protective film, and a metal multilayer film formed on a silicon substrate, and an initial oxide film and a metal multilayer film are formed under the silicon substrate in manufacturing a semiconductor device according to an embodiment of the present invention; Sectional drawing of the formed state.
FIG. 2 is a cross-sectional view showing a state in which a protective film is formed on the upper surface of the upper metal multilayer film and a resist pattern is formed on the lower surface of the lower metal multilayer film in manufacturing the semiconductor device.
FIG. 3 is a cross-sectional view showing a state in which an opening is formed in the lower initial oxide film and the lower metal multilayer film when the semiconductor device is manufactured;
FIG. 4 is a cross-sectional view showing a state in which an opening is formed in a silicon substrate when the semiconductor device is manufactured.
FIG. 5 is a cross-sectional view showing a state in which an opening is formed in the upper initial oxide film in manufacturing the semiconductor device;
FIG. 6 is a cross-sectional view showing a state where zinc nuclei are formed in the opening when the semiconductor device is manufactured.
FIG. 7 is a cross-sectional view showing a state in which a nickel plating layer is formed in the opening when the semiconductor device is manufactured.
FIG. 8 is a cross-sectional view showing a state in which a copper plating layer is formed in the opening when the semiconductor device is manufactured.
FIG. 9 is a cross-sectional view showing a state in which a connection pad forming layer and a resist pattern are formed under the silicon substrate when the semiconductor device is manufactured;
FIG. 10 is a cross-sectional view showing a state where a lower connection pad is formed under the silicon substrate when the semiconductor device is manufactured;
FIG. 11 is a cross-sectional view showing a state in which a protruding electrode is formed under a lower connection pad when the semiconductor device is manufactured.
FIG. 12 is a cross-sectional view of a state in which a conventional semiconductor device is mounted on a circuit board.
[Explanation of symbols]
21 Silicon substrate 22 Optical sensor functional part 24 Upper connection pads 21a, 23a, 28a Opening 32 Zinc nucleus 33 Nickel plating layer 34 Copper plating layer 37 Lower connection pads

Claims (7)

一の面に複数の第１の接続パッドを備えた半導体基板と、
該半導体基板の他の面からその内部に前記第１の接続パッドに達するように形成された複数の開口部と、
該開口部内に前記第１の接続パッドと接続された状態で形成され、メッキによって形成された少なくとも２種類の金属層からなる複数の内部導通部と、
前記半導体基板の他の面に前記内部導通部と接続された状態で形成された複数の第２の接続パッドと、
を具備することを特徴とする半導体装置。A semiconductor substrate having a plurality of first connection pads on one surface;
A plurality of openings formed to reach the first connection pad from the other surface of the semiconductor substrate to the inside thereof;
A plurality of internal conductive portions formed of at least two kinds of metal layers formed by plating formed in a state connected to the first connection pads in the opening;
A plurality of second connection pads formed in a state of being connected to the internal conductive portion on the other surface of the semiconductor substrate;
A semiconductor device comprising: 前記第２の接続パッドはマトリックス状に配置されていることを特徴とする請求項１記載の半導体装置。  The semiconductor device according to claim 1, wherein the second connection pads are arranged in a matrix. 前記第２の接続パッド上に突起電極が形成されていることを特徴とする請求項１または２記載の半導体装置。  3. The semiconductor device according to claim 1, wherein a protruding electrode is formed on the second connection pad. 前記第１の接続パッドは保護膜で覆われていることを特徴とする請求項１〜３のいずれかに記載の半導体装置。  The semiconductor device according to claim 1, wherein the first connection pad is covered with a protective film. 前記半導体基板の一の面に光センサ機能部が前記第１の接続パッドと接続された状態で形成されていることを特徴とする請求項１〜４のいずれかに記載の半導体装置。  5. The semiconductor device according to claim 1, wherein an optical sensor function unit is formed on one surface of the semiconductor substrate in a state of being connected to the first connection pad. 6. 一の面に複数の第１の接続パッドを備えた半導体基板の他の面に、前記第１の接続パッドに対応する箇所に開口部を有する、少なくとも２層構造を有する多層金属膜を形成し、
該多層金属膜の前記開口部を介して前記半導体基板をエッチングして、前記半導体基板の他の面からその内部に複数の開口部を前記第１の接続パッドに達するように形成し、
前記多層金属膜を剥離した後、メッキにより、少なくとも２種類の金属層を前記開口部内のみに形成して、前記開口部内に複数の内部導通部を前記第１の接続パッドに接続させて形成し、
前記半導体基板の他の面に複数の第２の接続パッドを前記内部導通部に接続させて形成することを特徴とする半導体装置の製造方法。 A multilayer metal film having an at least two-layer structure having an opening at a location corresponding to the first connection pad is formed on the other surface of the semiconductor substrate having a plurality of first connection pads on one surface. ,
Etching the semiconductor substrate through the openings of the multilayer metal film, and forming a plurality of openings in the semiconductor substrate from the other surface to reach the first connection pads;
After peeling off the multilayer metal film, at least two types of metal layers are formed only in the opening by plating , and a plurality of internal conductive parts are formed in the opening by connecting to the first connection pad. ,
A method of manufacturing a semiconductor device, comprising: forming a plurality of second connection pads on the other surface of the semiconductor substrate by connecting to the internal conductive portion. 前記半導体基板はその一の面に前記第１の接続パッドに接続された光センサ機能部を備えていることを特徴とする請求項６記載の半導体装置の製造方法。  The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor substrate includes an optical sensor function unit connected to the first connection pad on one surface thereof.
JP15168997A 1997-05-27 1997-05-27 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3648585B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15168997A JP3648585B2 (en) 1997-05-27 1997-05-27 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15168997A JP3648585B2 (en) 1997-05-27 1997-05-27 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH10335337A JPH10335337A (en) 1998-12-18
JP3648585B2 true JP3648585B2 (en) 2005-05-18

Family

ID=15524120

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15168997A Expired - Fee Related JP3648585B2 (en) 1997-05-27 1997-05-27 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3648585B2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6468889B1 (en) * 2000-08-08 2002-10-22 Advanced Micro Devices, Inc. Backside contact for integrated circuit and method of forming same
WO2003019653A2 (en) * 2001-08-24 2003-03-06 Schott Glas Method for producing contacts and printed circuit packages
JP4534484B2 (en) * 2003-12-26 2010-09-01 ソニー株式会社 Solid-state imaging device and manufacturing method thereof
JP2005303258A (en) * 2004-03-16 2005-10-27 Fujikura Ltd Device and method for manufacturing the same
JP4845368B2 (en) * 2004-10-28 2011-12-28 オンセミコンダクター・トレーディング・リミテッド Semiconductor device and manufacturing method thereof
DE102005039068A1 (en) * 2005-08-11 2007-02-15 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Semiconductor substrate and method of manufacture
JP5231733B2 (en) * 2006-11-27 2013-07-10 パナソニック株式会社 Through-hole wiring structure and method for forming the same
US7576425B2 (en) 2007-01-25 2009-08-18 Xintec, Inc. Conducting layer in chip package module
TWI353667B (en) 2007-07-13 2011-12-01 Xintec Inc Image sensor package and fabrication method thereo
US8772919B2 (en) 2007-08-08 2014-07-08 Wen-Cheng Chien Image sensor package with trench insulator and fabrication method thereof
JP5237607B2 (en) * 2007-10-25 2013-07-17 新光電気工業株式会社 Substrate manufacturing method
KR101998340B1 (en) * 2012-07-18 2019-07-09 삼성전자주식회사 Power Device Module and Method of fabricating the same

Also Published As

Publication number Publication date
JPH10335337A (en) 1998-12-18

Similar Documents

Publication Publication Date Title
US6144100A (en) Integrated circuit with bonding layer over active circuitry
JP2817717B2 (en) Semiconductor device and manufacturing method thereof
JP4400802B2 (en) Lead frame, manufacturing method thereof, and semiconductor device
JP3888854B2 (en) Manufacturing method of semiconductor integrated circuit
JPH0145976B2 (en)
EP1228530A1 (en) Metal redistribution layer having solderable pads and wire bondable pads
US6784557B2 (en) Semiconductor device including a diffusion layer formed between electrode portions
JP3648585B2 (en) Semiconductor device and manufacturing method thereof
JP2000299337A (en) Semiconductor device and manufacture thereof
JP2622156B2 (en) Contact method and structure for integrated circuit pads
JP2001053075A (en) Wiring structure and method of forming wiring
EP1003209A1 (en) Process for manufacturing semiconductor device
JPH11204560A (en) Semiconductor device and manufacture thereof
JP3957928B2 (en) Semiconductor device and manufacturing method thereof
JP3877700B2 (en) Semiconductor device and manufacturing method thereof
JP3259562B2 (en) Manufacturing method of semiconductor device with bump
JP3087819B2 (en) Terminal electrode formation method for solder bump mounting
KR100629467B1 (en) Package for image sensor
JP3573894B2 (en) Semiconductor device and manufacturing method thereof
JP2002313930A (en) Semiconductor device and its manufacturing method
JPH03268385A (en) Solder bump and manufacture thereof
JP2001118957A (en) Semiconductor device
US20220139815A1 (en) Semiconductor device and method manufacturing thereof
JP2001077229A (en) Semiconductor device and manufacture thereof
JP3548814B2 (en) Structure of protruding electrode and method for forming the same

Legal Events

Date Code Title Description
TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050118

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050131

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090225

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090225

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100225

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110225

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110225

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120225

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120225

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130225

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130225

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140225

Year of fee payment: 9

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees