JPH03268385A - Solder bump and manufacture thereof - Google Patents

Solder bump and manufacture thereof

Info

Publication number
JPH03268385A
JPH03268385A JP2065556A JP6555690A JPH03268385A JP H03268385 A JPH03268385 A JP H03268385A JP 2065556 A JP2065556 A JP 2065556A JP 6555690 A JP6555690 A JP 6555690A JP H03268385 A JPH03268385 A JP H03268385A
Authority
JP
Japan
Prior art keywords
layer
solder
adhesive layer
main conductor
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2065556A
Other languages
Japanese (ja)
Other versions
JP2760360B2 (en
Inventor
Haruo Tanmachi
東夫 反町
Takumi Suzuki
工 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2065556A priority Critical patent/JP2760360B2/en
Publication of JPH03268385A publication Critical patent/JPH03268385A/en
Application granted granted Critical
Publication of JP2760360B2 publication Critical patent/JP2760360B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps

Abstract

PURPOSE:To prevent a bump from being stripped off and to prevent a main conductor from being disconnected by a method wherein a metal whose solderability is poor as compared with that of a solderadhesion part is formed around the solder-adhesion part. CONSTITUTION:In order to prevent a solder 17 from coming into contact with a main conductor 8 of Cu, a metal 23 whose solderability is poor as compared with that of a solder-adhesion part is formed around the solder-adhesion part at the outer circumference part of the solder-adhesion part. When the outer circumference part of the solder-adhesion part is surrounded by the metal 23 whose solderability is poor, the solder 17 for bump use does not flow out from the solder-adhesion part. Consequently, the solder does not come into contact with the main conductor 8 and is not alloyed. Thereby, it is possible to prevent a bump from being stripped off and to prevent the main conductor from being disconnected.

Description

【発明の詳細な説明】 〔概 要〕 高密度表面実装を行う電子回路用基板の部品実装用はん
だバンプ及びその製造方法に関し、バっド又は主導体の
銅がはんだと合金化し機械的強度が低下してバンプの剥
離、主導体の断線等が生ずるのを防止することを目的と
し、はんだ付着部の外周部分に、はんだがCuの主導体
と接触することを防止するため、はんだ付着部に比しは
んだ濡れ性の悪い金属をはんだ付着部の周囲に設けるよ
うに構成する。
[Detailed Description of the Invention] [Summary] Regarding a solder bump for mounting components on an electronic circuit board that performs high-density surface mounting and a method for manufacturing the same, the copper of the pad or the main conductor is alloyed with the solder and the mechanical strength is increased. In order to prevent the solder from coming into contact with the Cu main conductor, the outer circumferential part of the solder joint is coated to prevent the solder from coming into contact with the Cu main conductor. In comparison, a metal having poor solder wettability is provided around the solder attachment part.

〔産業上の利用分野〕[Industrial application field]

本発明は高密度表面実装を行う電子回路用基板の部品実
装用はんだバンプ及びその製造方法に関する。
The present invention relates to a solder bump for mounting components on an electronic circuit board that performs high-density surface mounting, and a method for manufacturing the same.

[従来の技術] 最近の電子計算機の電子回路はIC,LSI等の半導体
部品の高集積化に伴い、回路基板への部品実装密度も高
密度化が進んでいる。このため回路基板への部品実装に
ははんだバンプを用いた表面実装が用いられるようにな
って来ている。第7図はこの表面実装の1例を示す図で
ある。これは、セラミック回路基板1の導体に設けられ
たバっドにはんだバンプ2が形成され、他方、ICチッ
プ3はセラミックキャリア4に搭載され、その電極が内
部導体5にワイヤ6で接続されている。さらにセラミッ
クキャリア4の下面には内部導体5に接続した多数のリ
ードピン7が植設されており、該リードビン7がはんだ
バンプ2により回路基板1にはんだ付けされている。
[Prior Art] In recent electronic circuits of electronic computers, as semiconductor components such as ICs and LSIs have become highly integrated, the density of component mounting on circuit boards has also increased. For this reason, surface mounting using solder bumps has come to be used for mounting components on circuit boards. FIG. 7 is a diagram showing an example of this surface mounting. In this case, solder bumps 2 are formed on the conductors of a ceramic circuit board 1, while an IC chip 3 is mounted on a ceramic carrier 4, and its electrodes are connected to an internal conductor 5 with wires 6. There is. Further, a large number of lead pins 7 connected to the internal conductor 5 are implanted on the lower surface of the ceramic carrier 4, and the lead pins 7 are soldered to the circuit board 1 by solder bumps 2.

はんだバンプは第8図(a)又は(b)に示すように、
セラミック回路基板1の上に、Cuを主導体8とし、そ
の上下にCrからなる密着層9,10を有する配線パタ
ーン11とポリイミド等からなる樹脂絶縁層12が設け
られており、(a)図の場合は樹脂絶縁層12に窓あけ
したところにCr層13、Cu層14、Ni層15、A
u層16からなるパッドを形成し、そのAu層16の上
にはんだ17を搭載している。(b)図の場合はa図に
おける密着層10とその上のCr層13及びCu層14
を欠いている。
The solder bumps are as shown in FIG. 8(a) or (b).
On the ceramic circuit board 1, a wiring pattern 11 having a main conductor 8 made of Cu, adhesive layers 9 and 10 made of Cr above and below, and a resin insulating layer 12 made of polyimide or the like are provided. In the case of Cr layer 13, Cu layer 14, Ni layer 15, A
A pad made of a U layer 16 is formed, and a solder 17 is mounted on the Au layer 16. (b) In the case of the figure, the adhesion layer 10 and the Cr layer 13 and Cu layer 14 thereon are shown in figure a.
is lacking.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来のはんだバンプにおいて、はんだがSn/Pb
共晶はんだの如く銅への侵食の小さなはんだの場合は異
状はないが、In/Snはんだのような銅を著しく侵食
するはんだに対しては、第9図(a)に示すようにはん
だ17がバッドの側面からCu層14(第8図すの場合
は主導体8)中に侵入し、合金層19を形成する。この
合金層19は機械的強度及び密着性に劣るため、バンプ
の剥離や、主導体の断線等を起こし、信頼性を著しく低
下させるという問題がある。
In the above conventional solder bump, the solder is Sn/Pb
There is no problem with solder that corrodes copper only slightly, such as eutectic solder. penetrates into the Cu layer 14 (the main conductor 8 in the case of FIG. 8) from the side surface of the pad, forming an alloy layer 19. Since this alloy layer 19 has poor mechanical strength and adhesion, there is a problem in that bumps may peel off, main conductors may break, etc., and reliability may be significantly reduced.

またバッド中のNi層15はスパッタで形成されたとき
の残留応力が大きいため、第9図(b)に示すように、
そのエツジ部から樹脂絶縁層12にクラック20を発生
させるという問題もある。
Furthermore, since the Ni layer 15 in the pad has a large residual stress when formed by sputtering, as shown in FIG. 9(b),
There is also the problem that cracks 20 are generated in the resin insulating layer 12 from the edge portions.

本発明は、上記従来の問題点に鑑み、バッド又は主導体
の銅がはんだと合金化し機械的強度が低下してバンプの
剥離、主導体の断線等が生ずるのを防止可能としたはん
だバンプを提供することを目的とする。
In view of the above-mentioned conventional problems, the present invention provides a solder bump that can prevent the copper of the pad or the main conductor from becoming alloyed with the solder, resulting in a decrease in mechanical strength, resulting in peeling of the bump, disconnection of the main conductor, etc. The purpose is to provide.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、本発明のはんだバンプでは
、はんだ付着部の外周部分に、はんだ17がCuの主導
体8と接触するのを防止するため、はんだ付着部に比し
はんだ濡れ性の悪い金属をはんだ付着部の周囲に設けた
ことを特徴とする。
To achieve the above object, in the solder bump of the present invention, in order to prevent the solder 17 from coming into contact with the Cu main conductor 8 on the outer peripheral part of the solder attachment part, the solder bump has a higher solder wettability than the solder attachment part. It is characterized by providing a bad metal around the solder attachment part.

また、基板1上に樹脂絶縁層12と導体8を用いた多層
配線が(まれでいる上に、密着層21、Ni層22、密
着層23の各層が順次設けられ、その最上層の密着層2
3に穴が設けられて該穴にNi層24及びAu又はPt
層25が設けられ、該Au又はPt層25の上にはんだ
17が搭載されていることを特徴とする。
In addition, a multilayer wiring using a resin insulating layer 12 and a conductor 8 is formed on the substrate 1 (in addition, each layer of an adhesion layer 21, a Ni layer 22, and an adhesion layer 23 are sequentially provided, and the uppermost adhesion layer 2
3 is provided with a hole, and the Ni layer 24 and Au or Pt are formed in the hole.
It is characterized in that a layer 25 is provided, and a solder 17 is mounted on the Au or Pt layer 25.

また、基板1上に密着層9、主導体8、密着層10及び
樹脂絶縁]1i12を順次形成する工程と、上記樹脂絶
縁層12のバンプ形成領域にエツチングにより密着層1
0が露出するように窓あけする工程と、上記露出した密
着層10上に密着層21、Ni層22及び密着層23を
順次形成する工程と、上記最上層の密着層23のバンプ
形成領域をエツチングして除去する工程と、上記密着層
23を除去した部分のNi層22上にNi層24及びA
u又はpt層25を形成する工程と、上記密着層23が
リング状に残るように該密着層23及びその下のNi層
22及び密着層21をエツチング除去する工程と、上記
Au又はPt層25上にはんだ17を搭載する工程、と
より成ることを特徴とする。
Further, a step of sequentially forming an adhesive layer 9, a main conductor 8, an adhesive layer 10, and a resin insulating layer 1i12 on the substrate 1, and etching the adhesive layer 11 in the bump forming area of the resin insulating layer 12 are performed.
a step of opening a window so that 0 is exposed; a step of sequentially forming an adhesion layer 21, a Ni layer 22, and an adhesion layer 23 on the exposed adhesion layer 10; and a step of forming a bump forming area of the uppermost adhesion layer 23. The process of etching and removing, and the Ni layer 24 and A
a step of forming the u or pt layer 25; a step of etching away the adhesion layer 23 and the underlying nickel layer 22 and adhesion layer 21 so that the adhesion layer 23 remains in a ring shape; It is characterized by comprising a step of mounting solder 17 on top.

また、基板1上に樹脂絶縁層重2と、上下に密着層9.
10を有する主導体8により多層配線がくまれている多
層配線基板において、上記上層の密着層10に穴が設け
られ、且つ該大の周囲の密着層10上にリング状のCu
層27が設けられ、さらに該Cu層27を含んで主導体
8上にNi層28とAu層29が設けられ、さらに該A
u層29上にはんだ17が搭載されていることを特徴と
する。
Further, a resin insulating layer 2 is placed on the substrate 1, and an adhesive layer 9 is placed on the top and bottom.
10, a hole is provided in the upper adhesion layer 10, and a ring-shaped Cu
A layer 27 is provided, and further a Ni layer 28 and an Au layer 29 are provided on the main conductor 8 including the Cu layer 27, further including the Cu layer 27.
It is characterized in that the solder 17 is mounted on the U layer 29.

また、基板1上に密着層9、主導体8、密着層10及び
Cu層27を順次形成する工程と、上記Cu層27と密
着層10のバンプ形成領域をエツチングにより除去する
工程と、上記Cu層27を除去した部分よりやや太き(
Ni層28とAu層29とを形成する工程と、上記Au
層29をマスクにしてCu層27をエツチング除去して
該Cu層27をNi層28の下にリング状に残す工程と
、上記リング状のCu層27の周囲に樹脂絶縁層12を
形成する工程と、前記Au層29上にはんだ17を搭載
する工程とより成ることを特徴とする。
Further, a step of sequentially forming the adhesion layer 9, the main conductor 8, the adhesion layer 10, and the Cu layer 27 on the substrate 1, a step of removing the bump forming regions of the Cu layer 27 and the adhesion layer 10 by etching, and It is slightly thicker than the part where layer 27 was removed (
The step of forming the Ni layer 28 and the Au layer 29, and the step of forming the Au layer 29,
A step of etching away the Cu layer 27 using the layer 29 as a mask to leave the Cu layer 27 in a ring shape under the Ni layer 28, and a step of forming the resin insulating layer 12 around the ring-shaped Cu layer 27. and mounting the solder 17 on the Au layer 29.

また、Cuよりなる主導体8の上のバンプ形成領域に、
はんだ濡れ性の悪い金属が設けられ、その上にはんだ濡
れ性の良い金属が前記はんだ濡れ性の悪い金属の外周を
リング状に残して設けられ、該はんだ濡れ性の良い金属
の上にはんだ17が搭載されていることを特徴とする。
In addition, in the bump formation region on the main conductor 8 made of Cu,
A metal with poor solder wettability is provided, a metal with good solder wettability is provided on top of the metal with a ring shape remaining around the outer periphery of the metal with good solder wettability, and a solder 17 is provided on the metal with good solder wettability. It is characterized by being equipped with.

また、基板1上に密着層9、主導体8、密着層10及び
Cu層27とを形成する工程と、上記Cu層27をホト
リソ法によりエツチングして該Cu層27をリング状に
残す工程と、上記リング状のCu層27の下の密着層1
0を前記Cu層27の内周よりやや小さい範囲でエツチ
ング除去する工程と、上記密着層10の除去により露出
した主導体8上と、前記リング状のCu層27上にNi
層28及びAu層29を形成する工程と、上記Au層2
9上にはんだ17を搭載する工程とより成ることを特徴
とする。
Further, a step of forming an adhesion layer 9, a main conductor 8, an adhesion layer 10, and a Cu layer 27 on the substrate 1, and a step of etching the Cu layer 27 by photolithography to leave the Cu layer 27 in a ring shape. , the adhesive layer 1 under the ring-shaped Cu layer 27
Ni is removed by etching in an area slightly smaller than the inner circumference of the Cu layer 27, and Ni is removed on the main conductor 8 exposed by the removal of the adhesive layer 10 and on the ring-shaped Cu layer 27.
The process of forming the layer 28 and the Au layer 29, and the step of forming the Au layer 2
The method is characterized by comprising a step of mounting a solder 17 on the solder 9.

〔作 用〕[For production]

はんだ付着部の外周部分をはんだ濡れ性の悪い金属で囲
んだことにより、バンプ用はんだがはんだ付着部から流
れ出すことがなく、従って主導体の銅と接触することが
なく、合金化もしない。従ってバンプの剥離、主導体の
断線等は防止される。
By surrounding the outer periphery of the solder attachment part with a metal that has poor solder wettability, the bump solder does not flow out from the solder attachment area, and therefore does not come into contact with the copper of the main conductor and is not alloyed. Therefore, peeling off of bumps, disconnection of main conductors, etc. are prevented.

〔実施例〕〔Example〕

第1図は本発明の第1の実施例を示す図である。 FIG. 1 is a diagram showing a first embodiment of the present invention.

本実施例は同図に示すように、セラミック基板1の上に
Cuを主導体としてその上下にCrからなる密着層9及
びlOが配置された導体パターン11が設けられ、その
上にバンプ形成領域が窓あけされた樹脂絶縁層12が設
けられており、該窓部に露出した導体パターン11の上
にCr層21、Ni層22、が設けられ、さらに該Ni
層22の上にリング状のCrN23及びその内側に形成
されたNi層24及びAu(又はPt)層25が設けら
れ、該Au層25の上にはんだ17が搭載されている。
In this embodiment, as shown in the figure, a conductor pattern 11 is provided on a ceramic substrate 1, with Cu as the main conductor and adhesion layers 9 made of Cr and lO arranged above and below the conductor pattern 11. A resin insulating layer 12 is provided with a window formed therein, and a Cr layer 21 and a Ni layer 22 are provided on the conductor pattern 11 exposed in the window.
A ring-shaped CrN 23 and a Ni layer 24 and an Au (or Pt) layer 25 formed inside the ring-shaped CrN 23 are provided on the layer 22, and the solder 17 is mounted on the Au layer 25.

このように構成された本実施例は、リング状に形成され
たCr層23のCr金属がはんだに対して濡れ性の悪い
金属であるため、はんだ17のバリアとなり、はんだ1
7の流れ出しを防止することができる。またNi層22
と24はCr層23によって段差を生じているので、そ
のエツジ部の応力は分散され、第9図(ハ)に示したよ
うな欠陥を生ずることは防止される。
In this embodiment configured in this way, since the Cr metal of the ring-shaped Cr layer 23 is a metal with poor wettability to solder, it acts as a barrier to the solder 17 and
7 can be prevented from flowing out. Also, the Ni layer 22
Since the edges 24 and 24 are stepped by the Cr layer 23, the stress at the edges is dispersed, and defects as shown in FIG. 9(c) are prevented from occurring.

第2図は本発明の第1の実施例の製造方法を説明するた
めの図であり、(a)〜(e)はその工程を示す。
FIG. 2 is a diagram for explaining the manufacturing method of the first embodiment of the present invention, and (a) to (e) show the steps.

本実施例は、先ず第2図(a)に示すように、セラミッ
ク基板1の上に密着層9、主導体8、密着層10よりな
る導体パターン11及びポリイミド樹脂絶縁Jii12
を形成した後、該樹脂絶縁層12のバンプ形成領域にエ
ツチングにより導体パターン12が露出するように窓あ
けし、その露出した導体パターン12に接してCr層2
1(厚さ約1000人)を形成し、その上にNi層22
(厚さ約1μm)と、Cr層23(厚さ約1000人)
を形成する。以上のCr層21.23及びNi層22は
スパッタ又は蒸着により形成する。次に第2図ら)に示
すように最上層のCr層23をレジスト26でマスクし
た後エツチングしてバンプ形成領域のCrを除去する。
In this embodiment, first, as shown in FIG. 2(a), a conductor pattern 11 consisting of an adhesive layer 9, a main conductor 8, an adhesive layer 10 and a polyimide resin insulating layer 12 are placed on a ceramic substrate 1.
After forming the bump formation area of the resin insulating layer 12, a window is formed by etching to expose the conductive pattern 12, and a Cr layer 2 is formed in contact with the exposed conductive pattern 12.
1 (approximately 1,000 layers thick), and a Ni layer 22 is formed on it.
(thickness approx. 1μm) and Cr layer 23 (thickness approx. 1000 people)
form. The above Cr layers 21, 23 and Ni layer 22 are formed by sputtering or vapor deposition. Next, as shown in FIG. 2 et al., the uppermost Cr layer 23 is masked with a resist 26 and etched to remove the Cr in the bump forming area.

次に第2図(C)に示すようにCr層23を除去した部
分にNi層24及びA u (又はPt)li25をめ
っきにより形成した後レジスト26を除去する。次に第
2図(d)に示すようにAu層25とCr層23の上に
該Cr層23がリング状に残るようにレジスト26でマ
スクし、Cr層23、Ni層22及びCr層21をエツ
チングし不要部分を除去する。最後に第2図(e)に示
すようにAu層25上のレジスト26′を除去し、そこ
にはんだ17を搭載するのである。
Next, as shown in FIG. 2C, a Ni layer 24 and an Au (or Pt)li layer 25 are formed by plating on the portion where the Cr layer 23 has been removed, and then the resist 26 is removed. Next, as shown in FIG. 2(d), the Cr layer 23 is masked with a resist 26 so that it remains in a ring shape on the Au layer 25 and the Cr layer 23, and the Cr layer 23, the Ni layer 22 and the Cr layer 23 are masked with a resist 26. Etch and remove unnecessary parts. Finally, as shown in FIG. 2(e), the resist 26' on the Au layer 25 is removed, and the solder 17 is mounted thereon.

なお第1図及び第2図(e)においてはAu層25が図
示されているが、実際はばんだ17を搭載したときに、
該はんだに溶は込んで見えなくなる。
Although the Au layer 25 is shown in FIG. 1 and FIG. 2(e), in reality, when the solder 17 is mounted,
The melt penetrates into the solder and becomes invisible.

(以下の各実施例においても同様である。)第3図は本
発明の第2の実施例を示す図である。
(The same applies to each of the following embodiments.) FIG. 3 is a diagram showing a second embodiment of the present invention.

同図において、1はセラミック基板であり、その上にC
uを主導体8としその上下にCrからなる密着層9及び
10が配置された導体パターン11が形成されている。
In the figure, 1 is a ceramic substrate, and C
A conductor pattern 11 is formed in which u is a main conductor 8 and adhesion layers 9 and 10 made of Cr are arranged above and below it.

そして該導体パターン11の上層の密着層10のバンプ
形成部分は除去され、その周囲の密着層10上にはリン
グ状のCu層27が設けられ、該Cu層27と導体パタ
ーンの露出している主導体8の上にNi層28とAu層
29が設けられ、そのAu層29の上にはんだ17が搭
載され、さらにCu層27の周囲に樹脂絶縁層12が形
成されている。
Then, the bump forming portion of the adhesive layer 10 on the upper layer of the conductor pattern 11 is removed, and a ring-shaped Cu layer 27 is provided on the adhesive layer 10 around it, and the Cu layer 27 and the conductor pattern are exposed. A Ni layer 28 and an Au layer 29 are provided on the main conductor 8, a solder 17 is mounted on the Au layer 29, and a resin insulating layer 12 is further formed around the Cu layer 27.

本実施例の製造方法は、先ず第4図(a)に示すように
基板1上に密着層9(厚さ500人)、主導体8(厚さ
5μm)、密着層10(厚さ1500人)、Cu層27
(厚さ5000人)をスパッタにて形成し、その上にフ
ォトレジスト30を塗布し、フォトリソ法とエツチング
によりバンプ形成領域のCu層27と密着層10を除去
する。次に第4図(b)に示すようにCu層27と密着
層10を除去したパターンより5〜10μm大きいレジ
スト31を設け、Ni層28とAu層29をめっきにて
形成する。
In the manufacturing method of this embodiment, first, as shown in FIG. ), Cu layer 27
(thickness: 5000 mm) is formed by sputtering, a photoresist 30 is applied thereon, and the Cu layer 27 and adhesive layer 10 in the bump formation area are removed by photolithography and etching. Next, as shown in FIG. 4(b), a resist 31 that is 5 to 10 μm larger than the pattern obtained by removing the Cu layer 27 and the adhesive layer 10 is provided, and a Ni layer 28 and an Au layer 29 are formed by plating.

次に第4図(C)に示すようにAu層29をマスクにし
てCu層27をエツチング除去してNi層28の下にの
みリング状に残す。次いでこのリング状のCu層27の
周囲に樹脂絶縁層12を形成し、さらにAu層29の上
にはんだ17を搭載して完成する。
Next, as shown in FIG. 4C, the Cu layer 27 is etched away using the Au layer 29 as a mask, leaving only a ring shape under the Ni layer 28. Next, a resin insulating layer 12 is formed around this ring-shaped Cu layer 27, and a solder 17 is further mounted on the Au layer 29 to complete the process.

このように構成された本実施例において、Cu層27は
Ni層28をめっきするときに、密着層10であるCr
には直接にはめっきできないための中間層として設けた
ものであり、たとえはんだと合金化してもそのはんだは
Nt層28と密着層10との境界で阻止することができ
る。従って主導体8がはんだに侵されることはない。
In this embodiment configured in this way, when plating the Ni layer 28, the Cu layer 27 is replaced with Cr, which is the adhesion layer 10.
It is provided as an intermediate layer since it cannot be plated directly on the Nt layer 28, and even if it is alloyed with solder, the solder can be blocked at the boundary between the Nt layer 28 and the adhesive layer 10. Therefore, the main conductor 8 is not attacked by the solder.

第5図は本発明の第3の実施例を示す図である。FIG. 5 is a diagram showing a third embodiment of the present invention.

同図において第3図と同一部分は同一符号を付して示し
た。
In this figure, the same parts as in FIG. 3 are designated by the same reference numerals.

本実施例は第3図の第2の実施例とほぼ同様の構成であ
り、異なるところは、リング状のCu層27を密着層1
0上に大きく形成し、Ni層28との間に空間32を設
けたことである。なおこの空間の密着層10にはNi層
28をめっきにより形成するとき極り薄<めっきされる
This embodiment has almost the same structure as the second embodiment shown in FIG. 3, and the difference is that the ring-shaped Cu layer 27 is
0, and a space 32 is provided between the Ni layer 28 and the Ni layer 28. Note that when the Ni layer 28 is formed by plating on the adhesion layer 10 in this space, it is plated very thinly.

このように構成された本実施例は、前実施例よりはんだ
17から主導体8までの距離が大となり、前実施例より
さらにはんだの拡散の危険性が少なくなり、信軌性は向
上する。
In this embodiment configured as described above, the distance from the solder 17 to the main conductor 8 is larger than in the previous embodiment, and the risk of solder diffusion is further reduced than in the previous embodiment, and the reliability is improved.

第6図は本発明の第3の実施例の製造方法を説明するた
めの図であり、(a)〜(d)はその工程を示す。
FIG. 6 is a diagram for explaining the manufacturing method of the third embodiment of the present invention, and (a) to (d) show the steps.

本実施例は先ず第6図(a)に示すように、基板1上に
密着層9と主導体8と、密着層10と、Cu層27とを
スパッタリングにより順次形成し、次いでフォトリソ法
を用いてCu層27をリング状に残るようにエツチング
する。次に第6図Φ)に示すようにリング状に形成され
たCu層27の内周及び外周にレジスト26を形成した
のち第6図(C)に示すように密着層10を溶かす液体
に浸漬して密着層10を除去し、その密着層10が除去
された部分及びリング状のCu層27の上にNi層28
及びAu層29を順次めっき形成する。次いで第6図(
d)に示すようにAu層29の上にはんだ17を搭載す
るのである。
In this example, first, as shown in FIG. 6(a), an adhesive layer 9, a main conductor 8, an adhesive layer 10, and a Cu layer 27 are sequentially formed on a substrate 1 by sputtering, and then a photolithography method is used. Then, the Cu layer 27 is etched so that it remains in a ring shape. Next, as shown in FIG. 6 Φ), a resist 26 is formed on the inner and outer peripheries of the ring-shaped Cu layer 27, and then, as shown in FIG. The adhesion layer 10 is removed, and a Ni layer 28 is formed on the portion where the adhesion layer 10 has been removed and on the ring-shaped Cu layer 27.
and an Au layer 29 are sequentially formed by plating. Next, Figure 6 (
As shown in d), the solder 17 is mounted on the Au layer 29.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に、本発明によれば、はんだ付着部の外
周にはんだ濡れ性の悪い金属を設けたことにより、はん
だが主導体に接触することを防止でき、バンプの剥離や
、主導体の断線を防止して信転性の向上に寄与すること
ができる。
As explained above, according to the present invention, by providing a metal with poor solder wettability on the outer periphery of the solder attachment part, it is possible to prevent the solder from coming into contact with the main conductor, thereby preventing the peeling of bumps and the contact of the main conductor. This can contribute to improving reliability by preventing wire breakage.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例を示す図、第2図は本発
明の第1の実施例の製造方法を説明するための図、 第3図は本発明の第2の実施例を示す図、第4図は本発
明の第2の実施例の製造方法を説明するための図、 第5図は本発明の第3の実施例を示す図、第6図は本発
明の第3の実施例の製造方法を説明するための図、 第7図は従来のはんだバンプを用いた表面実装の一例を
示す図、 第8図は従来のはんだバンプを示す図、第9図は発明が
解決しようとする課題を説明するための図である。 図において、 1はセラミック基板、 8は主導体、 9、lOは密着層、 11は導体パターン、 12は樹脂絶縁層、 17ははんだ、 21 、23はCr層、 22.24.28はNi層、 25.29はAu層、 27はCu層、 26.30.31はレジスト を示す。 本発明の第2の実施例を示す図 本発明の第1の実施例を示す図 1・・・基板 8・・・主導体 17・・・はんだ 27・・・Cu層 28・・・回層 29・・・Au層 25・・・Au層 (d) (b) (e) 本発明の第1の実施例の製造方居を説明するための図(
b) \ (C) 本発明の第2の実施例の製造方法を説明するだめの2第
4図 (b) (d) 本発明の第3の実施例の製造方法を 説明するための図 第6図 本発明の第3の実施例を示す図 第5図 1・・・基板 8・・・主導体 9.10・・・密着層 11・・・配線パターン 12・・樹脂絶縁層 17・・・はんだ 27・・・Cu層 28・・N1層 29・・・Au層 32・・・空間 従来のはんだバンプを用しまた表面実装の一例を示す図
第7図 (0) 17 従来のはんだバンプを示す図 第 コ (0) 発明が解決しようとする課題を説明するだめの9第 図
FIG. 1 is a diagram showing a first embodiment of the present invention, FIG. 2 is a diagram for explaining the manufacturing method of the first embodiment of the present invention, and FIG. 3 is a diagram showing a second embodiment of the present invention. FIG. 4 is a diagram for explaining the manufacturing method of the second embodiment of the present invention, FIG. 5 is a diagram showing the third embodiment of the present invention, and FIG. 6 is a diagram for explaining the manufacturing method of the second embodiment of the present invention. FIG. 7 is a diagram showing an example of surface mounting using conventional solder bumps. FIG. 8 is a diagram showing conventional solder bumps. FIG. 9 is a diagram showing the method of manufacturing the invention. FIG. In the figure, 1 is a ceramic substrate, 8 is a main conductor, 9, IO is an adhesion layer, 11 is a conductor pattern, 12 is a resin insulation layer, 17 is a solder, 21, 23 are Cr layers, 22, 24, and 28 are Ni layers. , 25.29 is an Au layer, 27 is a Cu layer, and 26.30.31 is a resist. Figure showing the second embodiment of the present invention Figure 1 showing the first embodiment of the present invention Substrate 8 Main conductor 17 Solder 27 Cu layer 28 Circuit layer 29...Au layer 25...Au layer (d) (b) (e) Diagram for explaining the manufacturing method of the first embodiment of the present invention (
b) \ (C) Figure 2 for explaining the manufacturing method of the second embodiment of the present invention (b) (d) Figure 4 for explaining the manufacturing method of the third embodiment of the present invention Figure 6 shows the third embodiment of the present invention Figure 5 1...Substrate 8...Main conductor 9.10...Adhesion layer 11...Wiring pattern 12...Resin insulating layer 17...・Solder 27...Cu layer 28...N1 layer 29...Au layer 32...Space Figure 7 (0) showing an example of surface mounting using conventional solder bumps 17 Conventional solder bumps Figure 9 (0) showing the problem to be solved by the invention Figure 9

Claims (1)

【特許請求の範囲】 1、はんだ付着部の外周部分にはんだ(17)がCuの
主導体(8)と接触することを防止するため、はんだ付
着部に比しはんだ濡れ性の悪い金属をはんだ付着部の周
囲に設けたことを特徴とするはんだバンプ。 2、基板(1)上に樹脂絶縁層(12)と導体(8)を
用いた多層配線がくまれている上に、密着層(21)、
Ni層(22)、密着層(23)の各層が順次設けられ
、その最上層の密着層(23)に穴が設けられて該穴に
Ni層(24)及びAu又はPt層(25)が設けられ
、該Au又はPt層(25)の上にはんだ(17)が搭
載されて成ることを特徴とするはんだバンプ。 3、基板(1)上に密着層(9)、主導体(8)、密着
層(10)及び樹脂絶縁層(12)を順次形成する工程
と、上記樹脂絶縁層(12)のバンプ形成領域にエッチ
ングにより密着層(10)が露出するように窓あけする
工程と、 上記露出した密着層(10)上に密着層(21)、Ni
層(22)及び密着層(23)を順次形成する工程と、
上記最上層の密着層(23)のバンプ形成領域をエッチ
ングして除去する工程と、 上記密着層(23)を除去した部分のNi層(22)上
にNi層(24)及びAu又はPt層(25)を形成す
る工程と、 上記密着層(23)がリング状に残るように該密着層(
23)及びその下のNi層(22)及び密着層(21)
をエッチング除去する工程と、 上記Au又はPt層(25)上にはんだ(17)を搭載
する工程、 とより成ることを特徴とするはんだバンプの製造方法。 4、基板(1)上に樹脂絶縁層(12)と、上下に密着
層(9、10)を有する主導体(8)により多層配線が
くまれている多層配線基板において、 上記上層の密着層(10)に穴が設けられ、且つ該穴の
周囲の密着層(10)上にリング状のCu層(27)が
設けられ、さらに該Cu層(27)を含んで主導体(8
)上にNi層(28)とAu層(29)が設けられ、さ
らに該Au層(29)上にはんだ(17)が搭載されて
成ることを特徴とするはんだバンプ。 5、基板(1)上に密着層(9)、主導体(8)、密着
層(10)及びCu層(27)を順次形成する工程と、
上記Cu層(27)と密着層(10)のバンプ形成領域
をエッチングにより除去する工程と、 上記Cu層(27)を除去した部分よりやや大きくNi
層(28)とAu層(29)とを形成する工程と、上記
Au層(29)をマスクにしてCu層(27)をエッチ
ング除去して該Cu層(27)をNi層(28)の下に
リング状に残す工程と、 上記リング状のCu層(27)の周囲に樹脂絶縁層(1
2)を形成する工程と、 前記Au層(29)上にはんだ(17)を搭載する工程
、とより成ることを特徴とするはんだバンプの製造方法
。 6、Cuよりなる主導体(8)の上のバンプ形成領域に
、はんだ濡れ性の悪い金属が設けられ、その上にはんだ
濡れ性の良い金属が前記はんだ濡れ性の悪い金属の外周
をリング状に残して設けられ、該はんだ濡れ性の良い金
属の上にはんだ(17)が設けられて成ることを特徴と
するはんだバンプ。 7、基板(1)上に密着層(9)、主導体(8)、密着
層(10)及びCu層(27)とを形成する工程と、上
記Cu層(27)をホトリソ法によりエッチングして該
Cu層(27)をリング状に残す工程と、上記リング状
のCu層(27)の下の密着層(10)を、前記Cu層
(27)の内周よりやや小さい範囲でエッチング除去す
る工程と、 上記密着層(10)の除去により露出した主導体(8)
上と、前記リング状のCu層(27)上にNi層(28
)及びAu層(29)を形成する工程と、 上記Au層(29)上にはんだ(17)を搭載する工程
、とより成ることを特徴とするはんだバンプの製造方法
[Claims] 1. In order to prevent the solder (17) from coming into contact with the Cu main conductor (8) on the outer periphery of the solder joint, a metal with poor solder wettability compared to the solder joint is soldered. A solder bump characterized by being provided around a bonding part. 2. A multilayer wiring using a resin insulating layer (12) and a conductor (8) is wrapped on the substrate (1), and an adhesive layer (21),
A Ni layer (22) and an adhesion layer (23) are sequentially provided, and a hole is provided in the uppermost adhesion layer (23), and a Ni layer (24) and an Au or Pt layer (25) are formed in the hole. 1. A solder bump, characterized in that the Au or Pt layer (25) is provided with a solder (17) mounted thereon. 3. Step of sequentially forming an adhesive layer (9), a main conductor (8), an adhesive layer (10) and a resin insulating layer (12) on the substrate (1), and a bump forming area of the resin insulating layer (12). a step of opening a window to expose the adhesive layer (10) by etching; and forming an adhesive layer (21) on the exposed adhesive layer (10);
a step of sequentially forming a layer (22) and an adhesive layer (23);
A step of etching and removing the bump forming area of the uppermost adhesive layer (23), and a Ni layer (24) and an Au or Pt layer on the Ni layer (22) in the portion where the adhesive layer (23) has been removed. (25) forming the adhesive layer (23) so that the adhesive layer (23) remains in a ring shape;
23) and the underlying Ni layer (22) and adhesion layer (21)
A method for manufacturing a solder bump, comprising: a step of etching away the Au or Pt layer (25); and a step of mounting a solder (17) on the Au or Pt layer (25). 4. In a multilayer wiring board in which multilayer wiring is enclosed by a resin insulating layer (12) on a substrate (1) and a main conductor (8) having adhesive layers (9, 10) above and below, the upper adhesive layer ( 10) is provided with a hole, and a ring-shaped Cu layer (27) is provided on the adhesive layer (10) around the hole, and further includes the Cu layer (27) to form a main conductor (8).
) A solder bump characterized in that a Ni layer (28) and an Au layer (29) are provided on the solder bump, and a solder (17) is further mounted on the Au layer (29). 5. Step of sequentially forming an adhesive layer (9), a main conductor (8), an adhesive layer (10) and a Cu layer (27) on the substrate (1);
A step of removing the bump forming regions of the Cu layer (27) and the adhesion layer (10) by etching;
A step of forming a layer (28) and an Au layer (29), etching and removing the Cu layer (27) using the Au layer (29) as a mask, and replacing the Cu layer (27) with the Ni layer (28). A process of leaving a ring-shaped layer underneath, and a step of leaving a resin insulating layer (1 layer) around the ring-shaped Cu layer (27).
2); and mounting a solder (17) on the Au layer (29). 6. A metal with poor solder wettability is provided on the bump forming region on the main conductor (8) made of Cu, and a metal with good solder wettability is formed on the outer circumference of the metal with poor solder wettability in a ring shape. A solder bump characterized in that the solder bump (17) is provided on the metal with good solder wettability. 7. Forming an adhesive layer (9), a main conductor (8), an adhesive layer (10), and a Cu layer (27) on the substrate (1), and etching the Cu layer (27) by photolithography. a step of leaving the Cu layer (27) in a ring shape, and etching away the adhesive layer (10) under the ring-shaped Cu layer (27) in an area slightly smaller than the inner circumference of the Cu layer (27). a main conductor (8) exposed by removing the adhesive layer (10);
and a Ni layer (28) on the ring-shaped Cu layer (27).
) and an Au layer (29), and a step of mounting a solder (17) on the Au layer (29).
JP2065556A 1990-03-17 1990-03-17 Solder bump and its manufacturing method Expired - Lifetime JP2760360B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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Publication Number Publication Date
JPH03268385A true JPH03268385A (en) 1991-11-29
JP2760360B2 JP2760360B2 (en) 1998-05-28

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08321671A (en) * 1995-05-26 1996-12-03 Nec Corp Bump electrode structure and manufacture thereof
WO2010038532A1 (en) * 2008-09-30 2010-04-08 イビデン株式会社 Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
US8030576B2 (en) 2007-03-05 2011-10-04 Nitto Denko Corporation Wired circuit board with interposed metal thin film and producing method thereof
JP2012174870A (en) * 2011-02-21 2012-09-10 Ngk Spark Plug Co Ltd Multilayer wiring board

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JPS62226633A (en) * 1986-03-28 1987-10-05 Sumitomo Electric Ind Ltd Semiconductor device
JPS6421932A (en) * 1987-07-16 1989-01-25 Hitachi Metals Ltd Semiconductor substrate
JPH01115196A (en) * 1987-10-28 1989-05-08 Nec Corp Manufacture of wiring board
JPH01170041A (en) * 1987-12-25 1989-07-05 Hitachi Ltd Closely adhered line sensor
JPH01216594A (en) * 1988-02-25 1989-08-30 Ngk Spark Plug Co Ltd Manufacture of ceramic circuit board

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Publication number Priority date Publication date Assignee Title
JPS62226633A (en) * 1986-03-28 1987-10-05 Sumitomo Electric Ind Ltd Semiconductor device
JPS6421932A (en) * 1987-07-16 1989-01-25 Hitachi Metals Ltd Semiconductor substrate
JPH01115196A (en) * 1987-10-28 1989-05-08 Nec Corp Manufacture of wiring board
JPH01170041A (en) * 1987-12-25 1989-07-05 Hitachi Ltd Closely adhered line sensor
JPH01216594A (en) * 1988-02-25 1989-08-30 Ngk Spark Plug Co Ltd Manufacture of ceramic circuit board

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08321671A (en) * 1995-05-26 1996-12-03 Nec Corp Bump electrode structure and manufacture thereof
KR100336548B1 (en) * 1995-05-26 2002-10-25 닛본 덴기 가부시끼가이샤 Wiring board, connection electrode structure and formation method thereof
US8030576B2 (en) 2007-03-05 2011-10-04 Nitto Denko Corporation Wired circuit board with interposed metal thin film and producing method thereof
WO2010038532A1 (en) * 2008-09-30 2010-04-08 イビデン株式会社 Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
JP2012109631A (en) * 2008-09-30 2012-06-07 Ibiden Co Ltd Multilayer printed wiring board and method of manufacturing multilayer printed wiring board
JP4951674B2 (en) * 2008-09-30 2012-06-13 イビデン株式会社 Multilayer printed wiring board and method for producing multilayer printed wiring board
US8314340B2 (en) 2008-09-30 2012-11-20 Ibiden Co., Ltd. Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
US8661665B2 (en) 2008-09-30 2014-03-04 Ibiden Co., Ltd. Method for manufacturing multilayer printed wiring board
JP2012174870A (en) * 2011-02-21 2012-09-10 Ngk Spark Plug Co Ltd Multilayer wiring board
US9119333B2 (en) 2011-02-21 2015-08-25 Ngk Spark Plug Co., Ltd. Multilayer wiring board

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