JPH01115196A - Manufacture of wiring board - Google Patents
Manufacture of wiring boardInfo
- Publication number
- JPH01115196A JPH01115196A JP27380587A JP27380587A JPH01115196A JP H01115196 A JPH01115196 A JP H01115196A JP 27380587 A JP27380587 A JP 27380587A JP 27380587 A JP27380587 A JP 27380587A JP H01115196 A JPH01115196 A JP H01115196A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- copper
- conductor
- forming
- interconnections
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910052802 copper Inorganic materials 0.000 claims abstract description 29
- 239000010949 copper Substances 0.000 claims abstract description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000004020 conductor Substances 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 22
- 229910052759 nickel Inorganic materials 0.000 abstract description 11
- 229910000679 solder Inorganic materials 0.000 abstract description 11
- 239000000919 ceramic Substances 0.000 abstract description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 abstract description 4
- 238000010884 ion-beam technique Methods 0.000 abstract description 4
- 239000002253 acid Substances 0.000 abstract description 3
- 239000003513 alkali Substances 0.000 abstract description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052763 palladium Inorganic materials 0.000 abstract description 2
- 229910052719 titanium Inorganic materials 0.000 abstract description 2
- 239000010936 titanium Substances 0.000 abstract description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract 1
- 229910052804 chromium Inorganic materials 0.000 abstract 1
- 239000011651 chromium Substances 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は大形コンピュータなどの電子機器に使用するセ
ラミック多層配線基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a ceramic multilayer wiring board used in electronic equipment such as large-sized computers.
従来のこの種のセラミック多層配線基板は、その上に形
成する多層配線層における導体配線として、絶縁層形成
時には酸化せず、かつ電気抵抗が低いという特性を有す
る金が使用されているか、または電気抵抗を更に低くす
るため、銅が使用されているかいずれかである。Conventional ceramic multilayer wiring boards of this type use gold, which does not oxidize when forming an insulating layer and has low electrical resistance, as the conductor wiring in the multilayer wiring layer formed thereon, or Copper is either used to further lower the resistance.
第３図は従来の製造方法によって製造した配線基板の一
例を工程順に示す断面図である。FIG. 3 is a cross-sectional view showing an example of a wiring board manufactured by a conventional manufacturing method in the order of steps.
第３［Ｍ（ａ）に示すように、セラミック多層基板の絶
縁層２３の上に銅層２１を形成し、その上にニッケル層
２２を形成した導体配線は、最上層に金層２５を形成し
ている。これにチップ３０（第３図（ｄ）参照）を接続
するため、第３図（ｂ）に示すように導体配線間に絶縁
層２９を形成し、導体配線の上部において絶縁層２９の
間に形成されるヴイアホール２４にはんだ２９を注入し
く第３図（Ｃ）参照）、このはんだ２９にチップ３０の
端子を接続するという手段を用いている。As shown in 3rd [M(a), the conductor wiring has a copper layer 21 formed on the insulating layer 23 of the ceramic multilayer board and a nickel layer 22 formed thereon, and a gold layer 25 is formed on the top layer. are doing. In order to connect the chip 30 (see FIG. 3(d)) to this, an insulating layer 29 is formed between the conductor wirings as shown in FIG. Solder 29 is injected into the via hole 24 to be formed (see FIG. 3(C)), and the terminals of the chip 30 are connected to this solder 29.
上述のように、従来のセラミック多層配線基板上に形成
される多層配線層における導体配線は、金または銅が使
用されているが、銅の方が価格も安価な上に電気抵抗も
低いなめに望ましいが、銅は酸化されやすいという欠点
があり、またイオン結合性の感光基を導入した感光性の
絶縁樹脂を使用した場合、銅と錯体を作りやすく、この
ため銅の配線の上に薄いクロムの層を設けてこれの改善
を計る必要があるが、これはヴイア部の抵抗が高くなる
という欠点がある。また部品搭載のなめに基板の最上層
に銅の端子を形成し、その上に、上記の感光性材料によ
る絶縁層でソルダーダムを形成してはんだをリフローし
ようとするとき、はんだの塗布性が悪いという欠点もあ
る。−労金は、高価であり、従って配線基板のコストを
上昇させるという欠点を有している。As mentioned above, gold or copper is used for conductor wiring in multilayer wiring layers formed on conventional ceramic multilayer wiring boards, but copper is cheaper and has lower electrical resistance. Although copper is desirable, it has the disadvantage that it is easily oxidized, and when a photosensitive insulating resin containing an ionic bonding photosensitive group is used, it tends to form a complex with copper. It is necessary to improve this by providing a layer, but this has the disadvantage of increasing the resistance of the via section. Also, when trying to reflow solder by forming copper terminals on the top layer of the board to mount components and forming a solder dam on top of that with an insulating layer made of the photosensitive material, the solder spreadability is poor. There is also a drawback. - Laboring metals have the disadvantage of being expensive and thus increasing the cost of the wiring board.
本発明の配線基板の製造方法は、導体配線を形成すると
き、電気抵抗の低い銅層と、その銅層の表面に銅の酸化
を防ぐための薄い金属膜とを形成し、絶縁層を形成する
ときに、各層の導体配線間の相互の導通を確保するため
ヴイアホールを形成し、そのヴイアホールに現れている
導体配線の薄い金属膜を酸またはアルカリによるウェッ
トエッチ法またはイオンビーム等のドライエッチ法等で
除去して銅の表面を露出してから、次の層を形成するよ
うにしたものである。すなわち、本発明の配線基板の製
造方法は、配線基板の絶縁層上に銅層を形成し、前記銅
層の上に金属薄膜層を形成して導体配線を構成し、前記
導体配線間にイオン結合性の感光基を導入した感光性材
料による絶縁層を形成し、この絶縁層の間の開口部に露
出した前記導体配線の前記金属薄膜層をエツチング法に
よって除去して前記銅層を露出させることを含んで構成
される。In the wiring board manufacturing method of the present invention, when forming conductor wiring, a copper layer with low electrical resistance is formed, a thin metal film is formed on the surface of the copper layer to prevent oxidation of the copper, and an insulating layer is formed. When doing so, a via hole is formed to ensure mutual conduction between the conductor wiring in each layer, and the thin metal film of the conductor wiring appearing in the via hole is wet-etched using acid or alkali, or dry etched using ion beam, etc. After the copper surface is exposed, the next layer is formed. That is, in the method for manufacturing a wiring board of the present invention, a copper layer is formed on an insulating layer of a wiring board, a metal thin film layer is formed on the copper layer to form a conductor wiring, and ions are formed between the conductor wiring. An insulating layer made of a photosensitive material into which a bonding photosensitive group has been introduced is formed, and the metal thin film layer of the conductor wiring exposed in the opening between the insulating layers is removed by an etching method to expose the copper layer. It consists of:
次に本発明の実施例について説明する。 Next, examples of the present invention will be described.
第１図は、本発明の第一の実施例によって製造した配線
基板の一例を工程順に示す断面図である。FIG. 1 is a cross-sectional view showing an example of a wiring board manufactured according to a first embodiment of the present invention in the order of steps.
第１図（ａ）において、セラミック多層板の絶縁層３上
に銅層１を形成し、この銅層１の上にニッケル層２を形
成して構成した導体配線７の間を、第１図（ｂ〉に示す
ように、イオン結合性の感光基を導入した感光性ポリイ
ミドによる絶縁層３によって覆ってヴイアホール４を形
成する。次に第３図（Ｃ）に示すように、導体配線７上
の薄いニッケル層２を酸またはアルカリでエツチングし
た後、イオンビームなどのドライエツチングを行って銅
層１を露出させ、次に第１図（ｄ）に示すように、この
銅層１の上に銅層５とニッケル層８とを形成して上層導
体配線８を形成する。チップはこの上層導体配線８に接
続する。In FIG. 1(a), a copper layer 1 is formed on an insulating layer 3 of a ceramic multilayer board, and a nickel layer 2 is formed on this copper layer 1. As shown in (b), a via hole 4 is formed by covering it with an insulating layer 3 made of photosensitive polyimide into which an ionic bonding photosensitive group is introduced.Next, as shown in FIG. After etching the thin nickel layer 2 with an acid or alkali, dry etching such as an ion beam is performed to expose the copper layer 1, and then as shown in FIG. A copper layer 5 and a nickel layer 8 are formed to form an upper layer conductor wiring 8. The chip is connected to this upper layer conductor wiring 8.
第２図は、本発明の第二の実施例によって製造した配線
基板の一例を工程順に示す断面図である。FIG. 2 is a cross-sectional view showing an example of a wiring board manufactured according to a second embodiment of the present invention in the order of steps.
本実施例では、導体配線を電子部品（チップ）等を接続
のための端子として直接用いるようにしている°。すな
わち第２図（ａ、）に示すように、絶縁層１３の上に銅
層１１を形成し、その上にニッケル層１２を形成して導
体配線１７を構成する。In this embodiment, the conductor wiring is directly used as a terminal for connecting an electronic component (chip) or the like. That is, as shown in FIG. 2(a), a copper layer 11 is formed on an insulating layer 13, and a nickel layer 12 is formed thereon to form a conductor wiring 17.
次に第２図（ｂ）に示すように、導体配線１７の間を、
イオン結合性の感光基を導入した感光性材料による絶縁
層１つを形成し、導体配線１７の上部に開口部（ヴイア
ホール）１２を形成する。次に第３図（Ｃ）に示すよう
に導体配線１７上の薄いニッケル層１２をイオンビーム
等でドライエツチングして除去したのち、第３図（ｄ）
に示すように、その上にはんだ１８を供給し、次に第３
図（ｅ）に示すようにはんだ１８上にチップ３０の端子
を搭載して接続する９
上述の実施例ではいずれも薄い金属膜として、ニッケル
を用いた例を示したが、ニッケルの代りにクロムまたは
パラジウムまたはチタンまたはアルミニウムを用いるこ
とができる。Next, as shown in FIG. 2(b), between the conductor wirings 17,
One insulating layer made of a photosensitive material into which an ionic bonding photosensitive group is introduced is formed, and an opening (via hole) 12 is formed above the conductor wiring 17. Next, as shown in FIG. 3(C), the thin nickel layer 12 on the conductor wiring 17 is removed by dry etching with an ion beam or the like, and then as shown in FIG. 3(d).
As shown in FIG.
As shown in Figure (e), the terminals of the chip 30 are mounted on the solder 18 and connected. Alternatively, palladium or titanium or aluminum can be used.
以上説明したように、本発明の配線基板の製造方法は、
銅を主体とする導体配線とイオン結合性の感光基が導入
された感光性の絶縁材料とを組合せて使用でき、このと
きの銅表面の酸化を防止することができると共に、上層
に形成した場合でも絶縁材料でソルダーダムを形成した
後にはんだがのりやすい導体配線を形成することができ
るという効果がある。As explained above, the method for manufacturing a wiring board of the present invention includes:
It is possible to use a combination of a conductor wiring mainly made of copper and a photosensitive insulating material into which an ionic bonding photosensitive group has been introduced, and it is possible to prevent oxidation of the copper surface at this time, and when it is formed as an upper layer. However, after forming a solder dam with an insulating material, it is possible to form a conductor wiring to which solder easily adheres.
第１図は本発明の第一の実施例によって製造した配線基
板の一例を工程順に示す断面図、第２図は本発明の第二
の実施例によって製造した配線基板の一例を工程順に示
す断面図、第３図は従来の製造方法によって製造した配
線基板の一例を工程順に示す断面図である。
１・５・１１・２１・・・銅層、２・６・１２・２２・
・・ニッケル層、３・９・１３・１９・２３・２９・・
・絶縁層、４・１４・２４・・・ヴイアホール、７・１
７・・・導体配線、８・・・上層導体配線、１８・２８
・・・はんだ、２５・・・金層、３０・・・チップ。FIG. 1 is a cross-sectional view showing an example of a wiring board manufactured according to the first embodiment of the present invention in order of process, and FIG. 2 is a cross-sectional view showing an example of a wiring board manufactured according to the second embodiment of the present invention in order of process. 3 are cross-sectional views showing an example of a wiring board manufactured by a conventional manufacturing method in the order of steps. 1, 5, 11, 21... copper layer, 2, 6, 12, 22,
...Nickel layer, 3, 9, 13, 19, 23, 29...
・Insulating layer, 4, 14, 24... Via hole, 7, 1
7... Conductor wiring, 8... Upper layer conductor wiring, 18/28
...Solder, 25...Gold layer, 30...Chip.
Claims (1)
金属薄膜層を形成して導体配線を構成し、前記導体配線
間にイオン結合性の感光基を導入した感光性材料による
絶縁層を形成し、この絶縁層の間の開口部に露出した前
記導体配線の前記金属薄膜層をエッチング法によって除
去して前記銅層を露出させることを含むことを特徴とす
る配線基板の製造方法。A photosensitive material comprising a copper layer formed on an insulating layer of a wiring board, a metal thin film layer formed on the copper layer to form a conductor wiring, and an ionic bonding photosensitive group introduced between the conductor wirings. Manufacturing a wiring board, comprising forming an insulating layer, and removing the metal thin film layer of the conductor wiring exposed in an opening between the insulating layers by an etching method to expose the copper layer. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27380587A JPH0691310B2 (en) | 1987-10-28 | 1987-10-28 | Wiring board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27380587A JPH0691310B2 (en) | 1987-10-28 | 1987-10-28 | Wiring board manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01115196A true JPH01115196A (en) | 1989-05-08 |
| JPH0691310B2 JPH0691310B2 (en) | 1994-11-14 |
Family
ID=17532817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27380587A Expired - Lifetime JPH0691310B2 (en) | 1987-10-28 | 1987-10-28 | Wiring board manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691310B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03268385A (en) * | 1990-03-17 | 1991-11-29 | Fujitsu Ltd | Solder bump and manufacture thereof |
| JP2012212818A (en) * | 2011-03-31 | 2012-11-01 | Tdk Corp | Electronic component built-in substrate and manufacturing method thereof |
-
1987
- 1987-10-28 JP JP27380587A patent/JPH0691310B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03268385A (en) * | 1990-03-17 | 1991-11-29 | Fujitsu Ltd | Solder bump and manufacture thereof |
| JP2012212818A (en) * | 2011-03-31 | 2012-11-01 | Tdk Corp | Electronic component built-in substrate and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0691310B2 (en) | 1994-11-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5869899A (en) | High density interconnect substrate and method of manufacturing same | |
| US6472609B2 (en) | Printed-wiring substrate and method for fabricating the printed-wiring substrate | |
| US5965944A (en) | Printed circuit boards for mounting a semiconductor integrated circuit die | |
| US7163847B2 (en) | Method of making circuitized substrate | |
| JP2001156203A (en) | Printed wiring board for mounting semiconductor chip | |
| KR920007120B1 (en) | Manufacturing method of wiring substrate for surface mounting | |
| KR100671541B1 (en) | A manufacturing method of printed circuit embedded board | |
| JPH01115196A (en) | Manufacture of wiring board | |
| JP2005150417A (en) | Substrate for semiconductor device, its manufacturing method, and semiconductor device | |
| JP2717200B2 (en) | Method of forming overlay plating on electronic component mounting substrate | |
| JP3050253B2 (en) | Method of manufacturing multilayer electronic component mounting substrate | |
| JP3627635B2 (en) | Printed wiring board and electronic component case using the same | |
| JP2787230B2 (en) | Substrate for mounting electronic components | |
| JPS6141303B2 (en) | ||
| JP2652222B2 (en) | Substrate for mounting electronic components | |
| JP2795475B2 (en) | Printed wiring board and manufacturing method thereof | |
| JPH04242939A (en) | Packaging structure of semiconductor device and its manufacture | |
| JPH05235498A (en) | Printed circuit board having protruding electrode and bonding method therefor | |
| JPS63283051A (en) | Substrate for hybrid integrated circuit device | |
| JPH02178992A (en) | Manufacture of thick film circuit substrate | |
| JPH0426185A (en) | Printed wiring board provided with flexible part and manufacture thereof | |
| KR20020000499A (en) | Multi-layer wiring substrate and semiconductor device using the multi-layer wiring substrate | |
| JPH01128493A (en) | Manufacture of multilayer interconnection substrate | |
| JPH0795556B2 (en) | Tape carrier manufacturing method | |
| JPH098463A (en) | Multilayer printed-wiring board, manufacture thereof and semiconductor device using multilayer printed-wiring board |