JPH04242939A - Packaging structure of semiconductor device and its manufacture - Google Patents

Packaging structure of semiconductor device and its manufacture

Info

Publication number
JPH04242939A
JPH04242939A JP3137054A JP13705491A JPH04242939A JP H04242939 A JPH04242939 A JP H04242939A JP 3137054 A JP3137054 A JP 3137054A JP 13705491 A JP13705491 A JP 13705491A JP H04242939 A JPH04242939 A JP H04242939A
Authority
JP
Japan
Prior art keywords
forming
semiconductor device
electrode
protruding electrode
protruding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3137054A
Other languages
Japanese (ja)
Inventor
Kazuhiko Torii
和彦 鳥居
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP3137054A priority Critical patent/JPH04242939A/en
Publication of JPH04242939A publication Critical patent/JPH04242939A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/361Assembling flexible printed circuits with other printed circuits

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a flexibility which can respond to a composite substrate or a stepped substrate and to enable packaging of small size and high density by providing connection electrode pads of a semiconductor device with a plurality of bump electrodes different in height. CONSTITUTION:A connection electrode 12 is arranged on the surface of a substrate 11, and this connection electrode 12 is connected to a flexible printed circuit(FPC)13 as the input-output signal bus line by means of an anisotropic conductive film 14. The FPC 13 consists of an insulating layer 13b and connection wiring layers 13a, 13c formed on both faces of this insulating layer 13b. Further, solder on the tip 25b of a bump electrode 25 of a semiconductor device 2 of bump electrodes different in height is melted to connect a semiconductor chip 21 having bump electrodes 25 to the connection electrode 21 and the FPC 13 on the substrate 11. Therefore, this can respond to steps developed by mounting other components on the substrate and enables small-sized, high-density packaging. It is possible to make not only packaging on the substrate surface, but also further connection from above components packaged on the substrate.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、突起電極を有する半導
体装置と接続電極を配置した基板との電気的接続を行な
うための実装構造と、この実装構造を形成するための製
造方法とに関するものである。
[Field of Industrial Application] The present invention relates to a mounting structure for electrically connecting a semiconductor device having protruding electrodes to a substrate on which connection electrodes are arranged, and a manufacturing method for forming this mounting structure. It is.

【0002】0002

【従来技術】近年、半導体装置の実装に望まれている実
装面積が小さく、実装厚が薄い実装方法に対応するため
、半導体装置の素子形成面を下にして実装するフェイス
ダウンボンディングが広く採用されている。フェイスダ
ウンボンディングの一般的な方法は、フリップチップボ
ンディング(以下FCと称す)法や、ガラス基板上に半
導体装置を実装するチップオングラス(以下COGと称
す)法で、どちらも半導体装置に突起電極を備えている
ことが特徴である。
[Prior Art] In recent years, face-down bonding, in which semiconductor devices are mounted with the element forming side facing down, has been widely adopted in order to cope with the mounting method that requires a small mounting area and thin mounting thickness for mounting semiconductor devices. ing. Common face-down bonding methods include the flip-chip bonding (hereinafter referred to as FC) method and the chip-on-glass (hereinafter referred to as COG) method in which the semiconductor device is mounted on a glass substrate. It is characterized by having the following.

【0003】以下、図6、および図7に基づいてフェイ
スダウンボンディングを説明する。図6(a)はFC法
で実装する半導体装置の突起電極を示す断面図であり、
図6(b)はFC法で接続する実装構造を示す断面図で
あり、図7(a)はCOG法で実装する半導体装置の突
起電極を示す断面図であり、図7(b)は導電性接着剤
を用いたCOG法で接続する実装構造を示す断面図であ
り、図7(c)は異方性導電接着剤を用いたCOG法で
接続する実装構造を示す断面図である。以下、図6と図
7とを交互に用いて説明する。
Face-down bonding will be explained below based on FIGS. 6 and 7. FIG. 6(a) is a cross-sectional view showing a protruding electrode of a semiconductor device mounted by the FC method.
FIG. 6(b) is a cross-sectional view showing a mounting structure connected by the FC method, FIG. 7(a) is a cross-sectional view showing a protruding electrode of a semiconductor device mounted by the COG method, and FIG. 7(b) is a cross-sectional view showing a mounting structure connected by the FC method. FIG. 7C is a cross-sectional view showing a mounting structure connected by a COG method using an anisotropic conductive adhesive, and FIG. 7C is a cross-sectional view showing a mounting structure connected by a COG method using an anisotropic conductive adhesive. Hereinafter, the explanation will be made using FIG. 6 and FIG. 7 alternately.

【0004】まず突起電極の構造を説明する。図6(a
)と図7(a)とに示すように、半導体装置21の半導
体素子形成面に設けたアルミニウムからなる接続電極パ
ッド22を開口露出するように、保護膜23を形成する
。さらに接続電極パッド22上に、この接続電極パッド
22との接着や、拡散防止のために共通電極膜24を形
成する。さらに突起電極25をメッキ法や真空蒸着法で
形成する。図6(a)に示すFC法で実装する半導体装
置の突起電極25は、ハンダからなる突起電極を用いる
。また図7(a)に示すCOG法で実装する半導体装置
の突起電極25は、銅や金などの金属からなる突起電極
25を用いる。
First, the structure of the protruding electrode will be explained. Figure 6 (a
) and FIG. 7A, a protective film 23 is formed so that the connection electrode pad 22 made of aluminum provided on the semiconductor element forming surface of the semiconductor device 21 is exposed through the opening. Further, a common electrode film 24 is formed on the connection electrode pad 22 for adhesion to the connection electrode pad 22 and for prevention of diffusion. Further, a protruding electrode 25 is formed by a plating method or a vacuum evaporation method. The protruding electrode 25 of the semiconductor device mounted by the FC method shown in FIG. 6A uses a protruding electrode made of solder. Further, the protruding electrode 25 of the semiconductor device mounted by the COG method shown in FIG. 7A uses a protruding electrode 25 made of metal such as copper or gold.

【0005】次に図6(a)と図7(a)とで説明した
突起電極を用いて、半導体装置と基板との接続方法を説
明する。
Next, a method of connecting a semiconductor device and a substrate will be described using the protruding electrodes described with reference to FIGS. 6(a) and 7(a).

【0006】FC法を用いた接続方法を図6(b)を用
いて説明する。FC法の接続は、半導体装置21の外形
で位置合わせを行い、その後ハンダからなる突起電極2
5を熱で溶融させ、基板11に形成した接続電極12と
、突起電極25を形成した半導体基板21とを接続する
A connection method using the FC method will be explained using FIG. 6(b). In connection using the FC method, alignment is performed using the outer shape of the semiconductor device 21, and then the protruding electrodes 2 made of solder are connected.
5 is melted by heat, and the connecting electrode 12 formed on the substrate 11 is connected to the semiconductor substrate 21 on which the protruding electrode 25 is formed.

【0007】COG法を用いた接続方法を図7(b)を
用いて説明する。COG法における接続は、半導体装置
21の突起電極25の先端に、エポキシ系の接着剤に導
電粒を混入した導電性接着剤27を、ディップ法や印刷
法で塗布し、双眼顕微鏡などで半導体装置21と基板1
1との位置合わせを行い、ガラスからなる基板11に形
成した接続電極12に突起電極25を接続する。
A connection method using the COG method will be explained using FIG. 7(b). For connection in the COG method, conductive adhesive 27, which is an epoxy adhesive mixed with conductive particles, is applied to the tip of the protruding electrode 25 of the semiconductor device 21 by dipping or printing, and the semiconductor device is inspected using a binocular microscope or the like. 21 and board 1
1, and the protruding electrode 25 is connected to the connecting electrode 12 formed on the substrate 11 made of glass.

【0008】また、図7(a)に示した導電性接着剤2
7の代わりに、厚さ方向に導電性を有し、横方向に導電
性を持たない異方性導電接着剤28を使用する接続方法
がある。この異方性導電接着剤を用いた接続方法を図7
(c)に示す。異方性導電接着剤28は、絶縁材料から
なる主材28aと、弾性を有する導電粒28bと、この
導電粒28bよりも若干粒径が小さい非導電粒28cと
によって構成する。この異方性導電接着剤28を印刷法
で接続電極12を形成したガラスからなる基板11に塗
布し、図7(a)に示した、突起電極25を有する半導
体装置21を基板11に熱圧着する。
Furthermore, the conductive adhesive 2 shown in FIG. 7(a)
7, there is a connection method using an anisotropic conductive adhesive 28 which has conductivity in the thickness direction but not in the lateral direction. Figure 7 shows the connection method using this anisotropic conductive adhesive.
Shown in (c). The anisotropic conductive adhesive 28 is composed of a main material 28a made of an insulating material, conductive particles 28b having elasticity, and non-conductive particles 28c having a slightly smaller particle size than the conductive particles 28b. This anisotropic conductive adhesive 28 is applied to the substrate 11 made of glass on which the connection electrodes 12 are formed by a printing method, and the semiconductor device 21 having the protruding electrodes 25 shown in FIG. 7(a) is bonded to the substrate 11 by thermocompression. do.

【0009】[0009]

【発明が解決しようとする課題】図6と図7とを用いて
説明したしたフェイスダウンボンディング法では、平坦
な基板に半導体装置を実装することを前提とし、基板に
段差が発生しないように設計を行なっている。このよう
な状況で実装構造を小型高密度なものにするためには、
接続配線ピッチの微細化と、基板へ搭載する部品の削減
とで対応している。実装技術の進歩に伴い高密度化が着
実に進んではいるが、この手法には限界がある。
[Problems to be Solved by the Invention] The face-down bonding method explained using FIGS. 6 and 7 is based on the premise that a semiconductor device is mounted on a flat substrate, and is designed so that no steps are formed on the substrate. is being carried out. In order to make the mounting structure compact and high-density under these circumstances,
This has been addressed by miniaturizing the connection wiring pitch and reducing the number of parts mounted on the board. Although advances in packaging technology have led to steady increases in density, this method has its limits.

【0010】この課題を解決するため本発明の目的は、
複数の部品が搭載されている複合基板や段差のある基板
等に対応できる柔軟性があり、そのうえ小型でしかも高
密度な実装が可能な半導体装置の実装構造と、この構造
を形成するための製造方法とを提供することにある。
[0010] In order to solve this problem, the object of the present invention is to
A mounting structure for semiconductor devices that is flexible enough to accommodate composite boards with multiple components mounted, boards with steps, etc., and that also allows for compact and high-density mounting, as well as manufacturing to form this structure. The purpose is to provide a method.

【0011】[0011]

【課題を解決するための手段】上記目的を達成するため
に、本発明は下記記載の構成と、この構成を形成するた
めの製造方法とを採用する。
Means for Solving the Problems In order to achieve the above object, the present invention employs the structure described below and a manufacturing method for forming this structure.

【0012】半導体装置の接続電極パッド上に複数の高
さの異なる突起電極を設け、基板に他の部品を搭載した
ことにより発生する段差に対応する。
[0012] A plurality of protruding electrodes having different heights are provided on the connection electrode pads of the semiconductor device to cope with differences in level caused by mounting other components on the substrate.

【0013】半導体装置の半導体素子形成面上の全面に
保護膜を形成し、フォトリソグラフィーとエッチングに
より接続電極パッド上に開口部を形成し、全面に共通電
極膜を形成する工程と、全面にメッキレジストを形成し
高さの高い突起電極の形成領域に開口部を形成する工程
と、メッキにより突起電極の台座部分を形成し、メッキ
レジストを除去する工程と、メタルマスクを半導体装置
上に配置し、メタルマスク開口の突起電極の形成領域に
ハンダを形成し、熱処理を行いハンダを丸めて突起電極
の先端部を形成し、突起電極をマスクにして前記共通電
極膜をエッチングする工程とを有する。
A process of forming a protective film on the entire surface of the semiconductor element formation surface of the semiconductor device, forming an opening on the connection electrode pad by photolithography and etching, forming a common electrode film on the entire surface, and plating the entire surface. A process of forming a resist and forming an opening in the formation area of a tall protruding electrode, a process of forming a pedestal part of the protruding electrode by plating and removing the plating resist, and a process of placing a metal mask on the semiconductor device. , forming solder in the region where the protruding electrode is to be formed in the opening of the metal mask, performing heat treatment and rolling the solder to form a tip of the protruding electrode, and etching the common electrode film using the protruding electrode as a mask.

【0014】半導体装置の半導体素子形成面上の全面に
保護膜を形成し、フォトリソグラフィーとエッチングに
より接続電極パッド上に開口部を形成し、全面に共通電
極膜を形成する工程と、全面に第1のメッキレジストを
形成し高さの高い突起電極の形成領域に開口部を形成す
る工程と、メッキ法により突起電極の台座部分を形成し
、第1のメッキレジストを除去する工程と、全面に第2
のメッキレジストを形成し突起電極の形成領域に開口部
を形成し、メッキにより突起電極の先端部を形成し、第
2のメッキレジストを除去し、突起電極をマスクにして
共通電極膜をエッチングする工程を有する。
A process of forming a protective film on the entire surface of the semiconductor element formation surface of the semiconductor device, forming an opening on the connection electrode pad by photolithography and etching, and forming a common electrode film on the entire surface; A step of forming a first plating resist and forming an opening in the formation area of a tall protruding electrode, a step of forming a pedestal part of the protruding electrode by a plating method and removing the first plating resist, and a step of forming the first plating resist on the entire surface. Second
forming a plating resist, forming an opening in the region where the protruding electrode is to be formed, forming the tip of the protruding electrode by plating, removing the second plating resist, and etching the common electrode film using the protruding electrode as a mask. Has a process.

【0015】半導体装置の半導体素子形成面上の全面に
保護膜を形成し、フォトリソグラフィーとエッチングに
より接続電極パッド上に開口部を形成し、全面に共通電
極膜を形成し、さらに全面に感光性レジストを形成し、
フォトリソグラフィーにより高さの高い突起電極の形成
領域に開口部を形成する工程と、全面に突起電極の台座
部分となる金属膜を形成する工程と、感光性レジストを
除去することにより感光性レジスト上に形成した金属膜
を除去し、感光性レジストの開口部に突起電極の台座部
分を形成する工程と、メタルマスクを半導体装置上に配
置し、メタルマスク開口の突起電極の形成領域にハンダ
を形成し、熱処理を行いハンダを丸めて突起電極の先端
部を形成し、この突起電極をマスクにして共通電極膜を
エッチングする工程とを有する。
A protective film is formed on the entire surface of the semiconductor element forming surface of the semiconductor device, an opening is formed on the connection electrode pad by photolithography and etching, a common electrode film is formed on the entire surface, and a photosensitive film is further formed on the entire surface. form a resist,
A process of forming an opening in the formation area of a tall protruding electrode by photolithography, a process of forming a metal film that will become a pedestal part of the protruding electrode on the entire surface, and a process of removing the photosensitive resist to form an opening on the photosensitive resist. A process of removing the metal film formed in the photosensitive resist and forming a pedestal part of the protruding electrode in the opening of the photosensitive resist, placing a metal mask on the semiconductor device, and forming solder in the area where the protruding electrode is to be formed in the opening of the metal mask. The method also includes the steps of performing heat treatment and rolling the solder to form the tips of the protruding electrodes, and etching the common electrode film using the protruding electrodes as a mask.

【0016】半導体装置の半導体素子形成面上の全面に
保護膜を形成し、フォトリソグラフィーとエッチングに
より接続電極パッド上に開口部を形成し、全面に共通電
極膜を形成し、さらに全面に感光性レジストを形成し、
フォトリソグラフィーにより高さの高い突起電極の形成
領域に開口部を形成する工程と、全面に突起電極の台座
部分となる金属膜を形成する工程と、感光性レジストを
除去することによりこの感光性レジスト上に形成した金
属膜を除去して、感光性樹脂の開口部に突起電極の台座
部分を形成する工程と、全面にメッキレジストを形成し
、突起電極の形成領域に開口部を形成し、メッキにより
突起電極の先端部を形成し、メッキレジストを除去し、
この突起電極をマスクにして共通電極膜をエッチングす
る工程とを有する。
A protective film is formed on the entire surface of the semiconductor element forming surface of the semiconductor device, an opening is formed on the connection electrode pad by photolithography and etching, a common electrode film is formed on the entire surface, and a photosensitive film is further formed on the entire surface. form a resist,
The process of forming an opening in the formation area of a tall protruding electrode by photolithography, the process of forming a metal film that will become the pedestal part of the protruding electrode on the entire surface, and the process of removing the photosensitive resist. A process of removing the metal film formed above and forming a pedestal part of the protruding electrode in the opening of the photosensitive resin, forming a plating resist on the entire surface, forming an opening in the area where the protruding electrode is to be formed, and plating. to form the tip of the protruding electrode, remove the plating resist,
and etching the common electrode film using the protruding electrode as a mask.

【0017】[0017]

【実施例】以下、本発明による実施例を図面に基づいて
説明する。本発明における第1の実施例を図1と、図2
とを用いて説明する。図1は第1の実施例における半導
体装置の実装構造を示す断面図であり、図2は高さの異
なる突起電極の形成方法を説明するための断面図である
Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings. A first embodiment of the present invention is shown in FIGS. 1 and 2.
This will be explained using FIG. 1 is a cross-sectional view showing a mounting structure of a semiconductor device in a first embodiment, and FIG. 2 is a cross-sectional view for explaining a method of forming protruding electrodes having different heights.

【0018】まず本発明の実装構造を図1に示す。基板
11の表面に接続電極12を配置し、この接続電極12
と、入出力信号用バスラインとして、フレキシブル・プ
リント・サーキット(以下FPCと称す)13とを異方
性導電フィルム14を用いて接続する。FPC13は絶
縁層13bと、この絶縁層13bの両面に形成した接続
配線層13a,13cとで構成する。さらに高さの異な
る突起電極を有する半導体装置21の突起電極25の先
端部25bのハンダを溶融し、突起電極25を有する半
導体装置21を、基板11上の接続電極12とFPC1
3とに接続する。
First, a mounting structure of the present invention is shown in FIG. A connection electrode 12 is arranged on the surface of the substrate 11, and this connection electrode 12
and a flexible printed circuit (hereinafter referred to as FPC) 13 as an input/output signal bus line are connected using an anisotropic conductive film 14. The FPC 13 is composed of an insulating layer 13b and connection wiring layers 13a and 13c formed on both sides of the insulating layer 13b. Further, the solder on the tips 25b of the protruding electrodes 25 of the semiconductor device 21 having protruding electrodes of different heights is melted, and the semiconductor device 21 having the protruding electrodes 25 is connected to the connecting electrode 12 on the substrate 11 and the FPC1.
Connect to 3.

【0019】高さの異なる突起電極を形成した半導体装
置の構造を図2(d)に示す。高さの異なる突起電極を
有する半導体装置21は、半導体素子形成面にある接続
電極パッド22が開口露出するように保護膜23を設け
、接続電極パッド22表面に共通電極膜24を設ける。 さらに基板の段差に応じた高さの異なる突起電極25を
共通電極膜24上に設ける。高さの高い突起電極は、台
座部分25aと先端部25bとの二層構造で、高さの低
い突起電極は先端部25bのみで構成する。
FIG. 2(d) shows the structure of a semiconductor device in which protruding electrodes of different heights are formed. In the semiconductor device 21 having protruding electrodes of different heights, a protective film 23 is provided so that the connection electrode pad 22 on the semiconductor element forming surface is exposed through the opening, and a common electrode film 24 is provided on the surface of the connection electrode pad 22. Furthermore, protruding electrodes 25 having different heights depending on the height difference of the substrate are provided on the common electrode film 24. The tall protruding electrode has a two-layer structure including a pedestal portion 25a and a tip portion 25b, and the short protruding electrode has a tip portion 25b only.

【0020】次に図1を用いて説明した本発明における
半導体装置の実装構造を形成するための製造方法を、図
2を用いて説明する。高さの異なる突起電極の形成方法
は、まず図2(a)に示すように、半導体装置21の半
導体素子形成表面に設けたアルミニウムからなる接続電
極パッド22を含む全面に保護膜23を形成する。この
保護膜23は、一般的に燐を含有した二酸化シリコン膜
や、窒化シリコン膜等の無機質膜や、ポリイミド樹脂等
の有機質膜や、これら無機質膜と有機質膜との積層構造
を用いる。保護膜23の膜厚は1〜5μmである。その
後、所定のマスクを用いて露光、および現像処理を行な
うフォトソリグラフィーとエッチングにより、接続電極
パッド22が露出するように保護膜23を開口する。
Next, a manufacturing method for forming the mounting structure of the semiconductor device according to the present invention explained using FIG. 1 will be explained using FIG. 2. The method for forming protruding electrodes of different heights is to first form a protective film 23 on the entire surface of the semiconductor device 21 including the connecting electrode pads 22 made of aluminum provided on the semiconductor element forming surface of the semiconductor device 21, as shown in FIG. 2(a). . This protective film 23 generally uses an inorganic film such as a silicon dioxide film containing phosphorus, a silicon nitride film, an organic film such as a polyimide resin, or a laminated structure of these inorganic films and organic films. The thickness of the protective film 23 is 1 to 5 μm. Thereafter, the protective film 23 is opened so that the connection electrode pad 22 is exposed by photolithography and etching, which includes exposure and development using a predetermined mask.

【0021】さらに半導体装置21の全面にアルミニウ
ム,クロム,銅,ニッケル,チタン等の金属多層膜を共
通電極膜24として、それぞれ0.1〜10μmの厚さ
でスパッタリング法や真空蒸着法等の方法で形成する。
Furthermore, a multilayer film of metals such as aluminum, chromium, copper, nickel, titanium, etc. is formed as a common electrode film 24 on the entire surface of the semiconductor device 21 to a thickness of 0.1 to 10 μm using a method such as sputtering or vacuum evaporation. to form.

【0022】次に図2(b)に示すように、感光性樹脂
からなるメッキレジスト26を厚さ1〜10μm塗布し
、フォトリソグラフィーにより高さの高い突起電極を形
成したい接続電極パッド22上に開口部を設ける。
Next, as shown in FIG. 2(b), a plating resist 26 made of photosensitive resin is applied to a thickness of 1 to 10 μm, and is applied by photolithography onto the connection electrode pad 22 on which a high protruding electrode is to be formed. Provide an opening.

【0023】次に図2(c)に示すように、銅や金等の
金属からなる突起電極25の台座部分25aをメッキ法
にて形成する。この台座部分25aのメッキ層の膜厚は
、基板の段差厚と同一にする。その後、不用になったメ
ッキレジスト26を除去する。
Next, as shown in FIG. 2(c), a pedestal portion 25a of the protruding electrode 25 made of metal such as copper or gold is formed by plating. The thickness of the plating layer on this pedestal portion 25a is made the same as the step thickness of the substrate. Thereafter, the plating resist 26 that is no longer needed is removed.

【0024】次に図2(d)に示すように、メタルマス
クを使用して突起電極25の先端部25bとなる鉛とス
ズからなるハンダを、50〜100μmの厚さで真空蒸
着法により、台座部分25a上と、接続電極パッド22
の共通電極膜24上とに形成する。その後、フラックス
を塗布して、熱処理を行い突起電極25の先端部25b
を半円球状にする丸め処理を行なう。
Next, as shown in FIG. 2(d), using a metal mask, solder made of lead and tin, which will become the tip 25b of the protruding electrode 25, is applied to a thickness of 50 to 100 μm by vacuum evaporation. On the pedestal portion 25a and the connection electrode pad 22
It is formed on the common electrode film 24 of. After that, flux is applied and heat treatment is performed on the tip portion 25b of the protruding electrode 25.
Rounding is performed to make it into a semicircular sphere.

【0025】突起電極25の先端部25bの別の形成方
法を次に説明する。図2(c)に示す台座部分25aを
形成後、第2のメッキレジストを全面に塗布し、フォト
リソグラフィーにより接続電極パッド22上に開口部を
設け、共通電極膜24をメッキ電極として、メッキ法に
よりハンダからなる突起電極25の先端部25bを形成
する。その後、不用となった第2のメッキレジストを除
去する。さらにその後、突起電極25をエッチングのマ
スクとして共通電極膜24をエッチングすることにより
除去して、図2(d)に示す、高さの異なる突起電極2
5を有する半導体装置21を形成する。
Another method for forming the tip portion 25b of the protruding electrode 25 will be described next. After forming the pedestal portion 25a shown in FIG. 2(c), a second plating resist is applied to the entire surface, an opening is formed on the connection electrode pad 22 by photolithography, and the common electrode film 24 is used as the plating electrode. The tip portion 25b of the protruding electrode 25 made of solder is thus formed. After that, the second plating resist that is no longer needed is removed. Furthermore, after that, the common electrode film 24 is removed by etching using the protruding electrode 25 as an etching mask, and the protruding electrodes 2 with different heights shown in FIG. 2(d) are removed.
5 is formed.

【0026】以上の説明では突起電極の高さの種類とし
ては、高いものと低いものとの二種類であったが、三つ
以上の種類の高さの異なる突起電極を設けても良い。こ
の突起電極の形成方法を以下に記す。図2(c)に示す
、突起電極25の台座部分25aを形成後、台座部分2
5aの形成に用いたメッキレジスト26を除去せず、さ
らに新たにメッキレジストを半導体装置21の全面に塗
布する。その後、所定のマスクを用いて露光現像処理を
行なうフォトリソグラフィーによって、最も高さの高い
突起電極の形成領域を開口し、この最も高さの高い突起
電極の形成領域以外の突起電極の形成領域を覆うように
形成する。その後メッキ処理を行ない突起電極25の台
座部分25aを形成し、台座部分25aの厚さを厚くす
る。このように、メッキレジスト26の形成工程とメッ
キ工程とを繰り返すことにより、複数の高さの突起電極
25の台座部分25aを形成する。この後、図2(d)
を用いて説明したように、メタルマスクを用いた真空蒸
着法やメッキ法によって突起電極25の先端部分25b
を形成することにより、複数の高さの異なる突起電極を
形成することができる。
In the above explanation, there are two types of protruding electrodes, high and low, but three or more types of protruding electrodes with different heights may be provided. The method for forming this protruding electrode will be described below. After forming the pedestal portion 25a of the protruding electrode 25 shown in FIG. 2(c), the pedestal portion 2
The plating resist 26 used to form the semiconductor device 21 is not removed, and a new plating resist is applied to the entire surface of the semiconductor device 21. After that, by photolithography that performs exposure and development using a predetermined mask, the highest protrusion electrode formation region is opened, and the protrusion electrode formation regions other than the highest protrusion electrode formation region are opened. Form to cover. Thereafter, a plating process is performed to form a pedestal portion 25a of the protruding electrode 25, and the thickness of the pedestal portion 25a is increased. In this way, by repeating the process of forming the plating resist 26 and the plating process, the pedestal portions 25a of the protruding electrodes 25 having a plurality of heights are formed. After this, Figure 2(d)
As explained above, the tip portion 25b of the protruding electrode 25 is formed by vacuum evaporation or plating using a metal mask.
By forming a plurality of protruding electrodes having different heights, it is possible to form a plurality of protruding electrodes having different heights.

【0027】さらに図3に示すようにリフトオフ法を用
いて、高さの異なる突起電極を形成することが可能であ
る。まず図3(a)に示すように、半導体装置21の半
導体素子形成表面に設けたアルミニウムからなる接続電
極パッド22を含む全面に保護膜23を形成する。この
保護膜23は、一般的に燐を含有した二酸化シリコン膜
や、窒化シリコン膜等の無機質膜や、ポリイミド樹脂等
の有機質膜や、これら無機質膜と有機質膜との積層構造
を用いる。この保護膜23の膜厚は1〜5μmである。 その後、所定のマスクを用いて露光、および現像処理を
行なうフォトソリグラフィーと、エッチングにより、接
続電極パッド22が露出するように保護膜23を開口す
る。
Furthermore, as shown in FIG. 3, it is possible to form protruding electrodes of different heights using a lift-off method. First, as shown in FIG. 3A, a protective film 23 is formed on the entire surface of the semiconductor device 21 including the connection electrode pads 22 made of aluminum provided on the surface on which the semiconductor elements are formed. This protective film 23 generally uses an inorganic film such as a silicon dioxide film containing phosphorus, a silicon nitride film, an organic film such as a polyimide resin, or a laminated structure of these inorganic films and organic films. The thickness of this protective film 23 is 1 to 5 μm. Thereafter, the protective film 23 is opened so that the connection electrode pad 22 is exposed by photolithography using a predetermined mask to perform exposure and development processing, and by etching.

【0028】さらに半導体装置21の全面にアルミニウ
ム,クロム,銅,ニッケル,チタン等の金属多層膜を共
通電極膜24として、それぞれ0.1〜10μmの厚さ
で、スパッタリング法や真空蒸着法等の方法で形成する
Furthermore, a multilayer film of metals such as aluminum, chromium, copper, nickel, and titanium is formed as a common electrode film 24 on the entire surface of the semiconductor device 21, each having a thickness of 0.1 to 10 μm, using a sputtering method, a vacuum evaporation method, etc. Form by method.

【0029】その後、感光性樹脂からなる感光性レジス
ト33を全面に塗布し、フォトリソグラフィーにより高
さの高い突起電極を形成したい接続電極パッド22上に
開口部を設ける。感光性レジスト33の膜厚は基板の段
差厚と同一にする。
Thereafter, a photosensitive resist 33 made of a photosensitive resin is applied to the entire surface, and an opening is formed by photolithography on the connection electrode pad 22 where a high protruding electrode is to be formed. The film thickness of the photosensitive resist 33 is made the same as the step thickness of the substrate.

【0030】次に図3(b)に示すように、半導体装置
21上の全面に、高さの高い突起電極25の台座部分2
5aとなる銅等の金属膜19を感光性レジスト33とほ
ぼ同じ厚さに形成する。
Next, as shown in FIG. 3(b), the pedestal portion 2 of the protruding electrode 25 with a high height is formed on the entire surface of the semiconductor device 21.
A metal film 19 made of copper or the like to be 5a is formed to have approximately the same thickness as the photosensitive resist 33.

【0031】次に図3(c)に示すように、レジスト剥
離液によって金属膜19下層の感光性レジスト33を除
去するリフトオフにより、感光性レジスト33上に形成
した金属膜19を除去する。この感光性レジスト33の
除去により、感光性レジスト33の開口内の高さの高い
突起電極25の形成領域に、突起電極25の台座部分2
5aを形成する。
Next, as shown in FIG. 3C, the metal film 19 formed on the photosensitive resist 33 is removed by lift-off, which removes the photosensitive resist 33 below the metal film 19 using a resist stripping solution. By removing the photosensitive resist 33, the pedestal portion 2 of the protruding electrode 25 is formed in the formation region of the protruding electrode 25 with a high height inside the opening of the photosensitive resist 33.
5a is formed.

【0032】次に図3(d)に示すように、メタルマス
クを使用して、突起電極25の先端部25bとなる鉛と
スズからなるハンダを50〜100μmの厚さで真空蒸
着法によって、台座部分25aと接続電極パッド22の
共通電極膜24上とに形成する。その後フラックスを塗
布し、熱処理を行い突起電極25の先端部25bを半円
球状にする丸め処理を行なう。
Next, as shown in FIG. 3(d), using a metal mask, solder made of lead and tin, which will become the tip 25b of the protruding electrode 25, is applied to a thickness of 50 to 100 μm by vacuum evaporation. It is formed on the pedestal portion 25a and the common electrode film 24 of the connection electrode pad 22. Thereafter, flux is applied and heat treatment is performed to round the tip portion 25b of the protruding electrode 25 into a semicircular shape.

【0033】また突起電極25の先端部25bの別の形
成方法をつぎに説明する。図3(c)に示す突起電極2
5の台座部分25aを形成後、メッキレジストを塗布し
、フォトリソグラフィーにより接続電極パッド22上に
開口部を設ける。その後、共通電極膜24を電極として
メッキ法によりハンダからなる突起電極25の先端部2
5bを形成する。その後、不用となったメッキレジスト
26を除去する。さらにその後、突起電極25をエッチ
ングのマスクとして、共通電極膜24を除去して、図3
(d)に示す高さの異なる突起電極25を有する半導体
装置21を形成する。
Another method for forming the tip 25b of the protruding electrode 25 will now be described. Protruding electrode 2 shown in FIG. 3(c)
After forming the pedestal portion 25a of No. 5, a plating resist is applied, and an opening is provided on the connection electrode pad 22 by photolithography. Thereafter, using the common electrode film 24 as an electrode, the tip portion 2 of the protruding electrode 25 made of solder is formed by plating.
Form 5b. Thereafter, the plating resist 26 that is no longer needed is removed. Furthermore, after that, the common electrode film 24 is removed using the protruding electrode 25 as an etching mask, and as shown in FIG.
A semiconductor device 21 having protruding electrodes 25 of different heights as shown in FIG. 3(d) is formed.

【0034】図1に示す、基板11は紙フェノールや紙
エポキシ等の有機質材料、あるいはアルミナセラミック
や結晶化ガラス等の無機質材料、あるいはガラスエポキ
シ等の有機無機質材料からなる。この基板11の表面に
感光性樹脂からなるメッキレジストを形成し、フォトリ
ソグラフィーでパターニングする。その後、銅,銀,金
などの金属を無電解メッキ法で10〜200μmの厚さ
で形成し、不用になったメッキレジストを除去すること
により接続電極12を形成する。また金属材料を真空蒸
着法やスパッタリング法等で形成し、その後、感光性樹
脂を塗布し、フォトリソグラフィーとエッチングにより
接続電極12を形成することも可能である。
The substrate 11 shown in FIG. 1 is made of an organic material such as paper phenol or paper epoxy, an inorganic material such as alumina ceramic or crystallized glass, or an organic/inorganic material such as glass epoxy. A plating resist made of photosensitive resin is formed on the surface of this substrate 11, and patterned by photolithography. Thereafter, a metal such as copper, silver, or gold is formed by electroless plating to a thickness of 10 to 200 μm, and the unnecessary plating resist is removed to form the connection electrode 12. It is also possible to form the metal material by vacuum evaporation, sputtering, etc., then apply a photosensitive resin, and form the connection electrode 12 by photolithography and etching.

【0035】図1に示すFPC13は、ポリイミドある
いはポリエステルなどの有機質材料で構成する絶縁層1
3bの両面に、感光性樹脂からなるメッキレジストをフ
ォトリソグラフィーでパターニングして、銅,銀,金な
どの金属を無電解メッキ法で形成する。その後不用にな
ったメッキレジストを除去して、接続配線層13a,1
3cを形成する。FPC13の絶縁層13bの厚さは、
50〜100μm、接続配線層13a,13cの厚さは
、10〜50μmが一般的である。
The FPC 13 shown in FIG. 1 has an insulating layer 1 made of an organic material such as polyimide or polyester.
A plating resist made of a photosensitive resin is patterned by photolithography on both sides of 3b, and metals such as copper, silver, and gold are formed by electroless plating. After that, the unnecessary plating resist is removed and the connection wiring layers 13a, 1
Form 3c. The thickness of the insulating layer 13b of the FPC 13 is
The thickness of the connection wiring layers 13a and 13c is generally 10 to 50 μm.

【0036】次に図1に示す、異方性フィルム14を用
いた接続方法と、半導体装置21の接続方法とを説明す
る。異方性導電フィルム14を、FPC13の接続配線
層13cに固定し、仮焼成する。その後、基板11に配
置した接続電極12と、異方性導電フィルム14を仮固
定したFPC13とを熱圧着法により接続して、電気的
接続を行なう。さらにFPC13の厚さ分の高さが異な
る突起電極を備えた半導体装置21を加熱して、突起電
極25の先端部25bのハンダを溶融させ、高さの高い
突起電極は基板11に配置した接続電極12と、高さの
低い突起電極はFPC13の接続電極層13aと電気的
接続を行い、図1に示す構造になる。
Next, a connection method using the anisotropic film 14 and a connection method of the semiconductor device 21 shown in FIG. 1 will be explained. The anisotropic conductive film 14 is fixed to the connection wiring layer 13c of the FPC 13 and pre-baked. Thereafter, the connection electrode 12 disposed on the substrate 11 and the FPC 13 to which the anisotropic conductive film 14 is temporarily fixed are connected by thermocompression bonding to establish electrical connection. Further, the semiconductor device 21 equipped with protruding electrodes having different heights corresponding to the thickness of the FPC 13 is heated to melt the solder on the tips 25b of the protruding electrodes 25. The electrode 12 and the low protruding electrode are electrically connected to the connection electrode layer 13a of the FPC 13, resulting in the structure shown in FIG.

【0037】本発明の半導体装置の実装構造における第
2の実施例を、図4を用いて説明する。図4は本発明に
おける第2の実施例の半導体装置の実装構造を示す断面
図である。接続電極12を配置した基板11に、第2の
半導体装置31bが納まる大きさの凹部32を設け、接
着剤15を用いて第2の半導体装置31bを固定する。 基板11に設ける凹部32の深さは第2の半導体装置3
2bの厚さと同じにして、実装面を平坦にするのが理想
である。
A second embodiment of the semiconductor device mounting structure of the present invention will be described with reference to FIG. FIG. 4 is a sectional view showing a mounting structure of a semiconductor device according to a second embodiment of the present invention. A recess 32 large enough to accommodate the second semiconductor device 31b is provided in the substrate 11 on which the connection electrode 12 is disposed, and the second semiconductor device 31b is fixed using an adhesive 15. The depth of the recess 32 provided in the substrate 11 is the same as that of the second semiconductor device 3.
Ideally, the thickness should be the same as that of 2b, and the mounting surface should be flat.

【0038】しかし、実装厚を薄くするためにできるだ
け薄い基板11を用いるので、基板強度の関係により凹
部32の深さには制限がある。そのために完全に実装面
を平坦化するのは難しく、基板11表面には段差が発生
する。
However, since the thinnest substrate 11 is used to reduce the mounting thickness, there is a limit to the depth of the recess 32 due to the strength of the substrate. Therefore, it is difficult to completely flatten the mounting surface, and a step is generated on the surface of the substrate 11.

【0039】凹部32に納める第2の半導体装置31b
は、半導体素子形成面にある接続電極パッド22が開口
露出するように保護膜23を設け、接続電極パッド22
表面に共通電極膜24と、さらに外部接続用電極29と
を有する。高さの異なる突起電極を有する第1の半導体
装置31aに形成する、突起電極25の先端部25bの
ハンダを溶融し、基板11上の接続電極12と、基板1
1の凹部32に収納した第2の半導体装置31bの外部
接続用電極29とに接続する。さらに基板11の凹部3
2に納めた第2の半導体装置31bの外部接続用電極2
9と、基板11に配置した接続電極12とを金属ワイヤ
ー16でボンディング接続する。
Second semiconductor device 31b housed in recess 32
In this method, a protective film 23 is provided so that the connection electrode pad 22 on the semiconductor element forming surface is exposed through the opening, and the connection electrode pad 22
It has a common electrode film 24 and an external connection electrode 29 on its surface. The solder on the tips 25b of the protruding electrodes 25 formed on the first semiconductor device 31a having protruding electrodes of different heights is melted, and the connecting electrodes 12 on the substrate 11 are bonded to the connecting electrodes 12 on the substrate 11.
It is connected to the external connection electrode 29 of the second semiconductor device 31b housed in the first recess 32. Furthermore, the recess 3 of the substrate 11
External connection electrode 2 of the second semiconductor device 31b housed in
9 and a connection electrode 12 disposed on the substrate 11 are bonded together using a metal wire 16.

【0040】次に図4に示す半導体装置の実装構造を形
成するための製造方法を説明する。基板11の形成方法
と、この基板11に接続電極12を製造する方法とは、
第1の実施例と同様である。第2の半導体装置31bを
収納する凹部32は、エッチングや機械的な加工等の方
法によって形成する。基板11に設けた凹部32に第2
の半導体装置31bを固定する方法は、銀等の導電粒を
エポキシ系の接着剤に混入した導電性接着剤や、エポキ
シ等の絶縁性接着剤からなる接着剤15をディスペンス
法によって、凹部32の底面に塗布し、その後第2の半
導体装置31bを搭載し、接着剤15を硬化させること
により行なう。
Next, a manufacturing method for forming the semiconductor device mounting structure shown in FIG. 4 will be described. The method for forming the substrate 11 and the method for manufacturing the connection electrode 12 on this substrate 11 are as follows:
This is similar to the first embodiment. The recess 32 that accommodates the second semiconductor device 31b is formed by a method such as etching or mechanical processing. The second recess 32 provided in the substrate 11 is
The semiconductor device 31b is fixed by dispensing an adhesive 15 made of a conductive adhesive in which conductive particles such as silver are mixed into an epoxy adhesive or an insulating adhesive such as epoxy. This is done by applying the adhesive to the bottom surface, then mounting the second semiconductor device 31b, and curing the adhesive 15.

【0041】基板11の凹部32に収納する第2の半導
体装置31bは、第1の実施例で説明した高さの異なる
突起電極を有する半導体装置と同じ方法で、接続電極パ
ッド22と、保護膜23と、共通電極膜24とをそれぞ
れ形成する。さらにメッキレジストを接続電極バッド2
2上に開口するように設け、金や銅などの金属からなる
外部接続用電極29を、メッキ法で1〜20μmの厚さ
で形成する。
The second semiconductor device 31b to be accommodated in the recess 32 of the substrate 11 is constructed by connecting the connecting electrode pad 22 and the protective film in the same way as the semiconductor device having protruding electrodes of different heights as described in the first embodiment. 23 and a common electrode film 24 are respectively formed. Furthermore, connect the plating resist to electrode pad 2
An external connection electrode 29 made of metal such as gold or copper is formed with a thickness of 1 to 20 μm by plating.

【0042】高さの異なる突起電極を有する第1の半導
体装置31aの形成方法は、第1の実施例と同様で、第
1の半導体装置31aを加熱して突起電極の先端部25
bのハンダを溶融させる。この結果、高さの高い突起電
極は基板11に配置した接続電極12と接続し、高さの
低い突起電極は基板11に設けた凹部32に納めた第2
の半導体装置31bの外部接続用電極29と接続して、
それぞれ電気的接続を行なう。
The method for forming the first semiconductor device 31a having protruding electrodes of different heights is the same as in the first embodiment, in which the first semiconductor device 31a is heated to form the tips 25 of the protruding electrodes.
Melt the solder in b. As a result, the taller protruding electrodes are connected to the connection electrodes 12 arranged on the substrate 11, and the lower protruding electrodes are connected to the second electrodes placed in the recesses 32 provided on the substrate 11.
connected to the external connection electrode 29 of the semiconductor device 31b,
Make electrical connections to each.

【0043】さらに高さの異なる突起電極を有する第1
の半導体装置31aと接続しない基板11の凹部32に
収納した第2の半導体装置31bの外部接続用電極29
は、基板11に配置した接続電極12と、金,銀,銅な
どの金属を用いた金属ワイヤー16でボンディング接続
を行い、図4に示す実装構造を形成する。
[0043] Further, a first electrode having protruding electrodes of different heights
External connection electrode 29 of the second semiconductor device 31b housed in the recess 32 of the substrate 11 that is not connected to the semiconductor device 31a.
The mounting structure shown in FIG. 4 is formed by bonding a connection electrode 12 disposed on a substrate 11 and a metal wire 16 made of metal such as gold, silver, or copper.

【0044】本発明における高さの異なる突起電極を備
えた半導体装置の第3の実施例を図5を用いて説明する
。図5は本発明の第3の実施例における半導体装置の実
装構造を示す断面図である。基板11に配置した接続電
極12と半導体装置21とを異方性導電接着剤28を用
いて接続した構造を図5に示す。半導体装置21は、半
導体素子形成領域に形成する抵抗素子30を備え、かつ
複数の高さの異なる突起電極25を有するものである。 異方性導電接着剤28は主材28a,導電粒28b,非
導電粒28cとで構成する。
A third embodiment of a semiconductor device having protruding electrodes of different heights according to the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view showing a mounting structure of a semiconductor device according to a third embodiment of the present invention. FIG. 5 shows a structure in which the connection electrode 12 disposed on the substrate 11 and the semiconductor device 21 are connected using an anisotropic conductive adhesive 28. The semiconductor device 21 includes a resistance element 30 formed in a semiconductor element formation region, and has a plurality of protruding electrodes 25 having different heights. The anisotropic conductive adhesive 28 is composed of a main material 28a, conductive particles 28b, and non-conductive particles 28c.

【0045】図5(a)に示す実装構造は、半導体装置
21に形成した突起電極25のうち高さの高い突起電極
だけが基板11に配置した接続電極12と接続するよう
、異方性導電接着剤28の導電粒28bの大きさを選択
する。また図5(b)に示す実装構造は、半導体装置2
1に形成した突起電極25のうち高さの低い突起電極と
、高さの高い突起電極との両方を基板11に配置した接
続電極12と接続するように、図5(a)で使用する、
異方性導電接着剤28の導電粒28bよりも大きい導電
粒28bを選択する。
The mounting structure shown in FIG. 5A uses anisotropic conductivity so that only the taller protruding electrodes of the protruding electrodes 25 formed on the semiconductor device 21 are connected to the connecting electrodes 12 disposed on the substrate 11. The size of the conductive particles 28b of the adhesive 28 is selected. Furthermore, the mounting structure shown in FIG. 5(b) has the semiconductor device 2
5(a) so that both of the protruding electrodes 25 formed in FIG.
Conductive particles 28b larger than the conductive particles 28b of the anisotropic conductive adhesive 28 are selected.

【0046】次に、図5を用いて説明した異方性導電接
着剤28を用いた半導体装置21の実装構造を製造する
ための製造方法を説明する。半導体装置21の半導体素
子形成領域に抵抗素子30を、不純物拡散層やポリシリ
コン層によって形成する。抵抗素子30の両端に高さの
高い突起電極と、抵抗素子30の中央部に高さの低い突
起電極とを、第1の実施例と同じ製造方法で形成する。 基板11の形成方法と、この基板11に配置した接続電
極12の製造方法とに関しても、第1の実施例と同じ製
造方法で形成する。
Next, a manufacturing method for manufacturing the mounting structure of the semiconductor device 21 using the anisotropic conductive adhesive 28 described using FIG. 5 will be described. A resistance element 30 is formed in a semiconductor element formation region of the semiconductor device 21 using an impurity diffusion layer or a polysilicon layer. High-height protruding electrodes at both ends of the resistive element 30 and low-height protruding electrodes at the center of the resistive element 30 are formed using the same manufacturing method as in the first embodiment. The method of forming the substrate 11 and the method of manufacturing the connection electrode 12 disposed on the substrate 11 are also the same as in the first embodiment.

【0047】異方性導電接着剤28は、主剤28aと、
導電粒28bと、非導電粒28cとで構成する。主剤2
8aは、ガラスペースト等の無機質材料や、エポキシ樹
脂、ポリエステル樹脂等の有機質材料で構成する。導電
粒28bは、弾性を有するスチレンとジビニルベンゼン
との共重合体からなるプラスティックビーズに、ニッケ
ル,アルミニウム,金,銀等の金属を、一種または二種
以上をメッキ処理して形成する。非導電粒28cは、グ
ラスファイバや金属酸化物等の無機質材料や、ポリメチ
ルメタクリレート等の硬度の高い有機質材料で形成した
ビーズにて構成する。
The anisotropic conductive adhesive 28 includes a main agent 28a,
It is composed of conductive particles 28b and non-conductive particles 28c. Main agent 2
8a is made of an inorganic material such as glass paste, or an organic material such as epoxy resin or polyester resin. The conductive particles 28b are formed by plating one or more metals such as nickel, aluminum, gold, and silver onto plastic beads made of an elastic copolymer of styrene and divinylbenzene. The non-conductive particles 28c are made of beads made of an inorganic material such as glass fiber or metal oxide, or a hard organic material such as polymethyl methacrylate.

【0048】異方性導電接着剤28は、ロール混練によ
り主材28aに導電粒28bと、非導電粒28cとを混
ぜ合わせ形成する。印刷法によって、接続電極12を配
置した基板11に異方性導電接着剤28を適量塗布して
、80℃程度の温度で仮焼成する。その後、高さの異な
る突起電極を有する半導体装置21を基板11上に配置
して、120〜150℃の温度で圧力を加えながら接続
を行なう。
The anisotropic conductive adhesive 28 is formed by mixing the main material 28a with conductive particles 28b and non-conductive particles 28c by roll kneading. By a printing method, an appropriate amount of anisotropic conductive adhesive 28 is applied to the substrate 11 on which the connection electrode 12 is arranged, and pre-baked at a temperature of about 80°C. Thereafter, semiconductor devices 21 having protruding electrodes of different heights are placed on the substrate 11, and connections are made while applying pressure at a temperature of 120 to 150°C.

【0049】異方性導電接着剤28の導電粒28bの大
きさを、非導電粒28cの直径に突起電極の台座部分2
5aの高さを加えた寸法よりも小さいものを用いた場合
の実装構造を図5(a)に示す。高さの低い突起電極は
基板11に配置した接続電極12とは導通せず、高さの
高い突起電極だけが接続電極12と電気的接続が行われ
る。この結果基板11に配置した接続電極12の間の抵
抗は、半導体素子領域に形成した抵抗素子30になる。
The size of the conductive particles 28b of the anisotropic conductive adhesive 28 is adjusted to the diameter of the non-conductive particles 28c on the pedestal portion 2 of the protruding electrode.
FIG. 5(a) shows a mounting structure in the case of using a device smaller than the dimension including the height of 5a. The protruding electrodes with a low height are not electrically connected to the connection electrodes 12 disposed on the substrate 11, and only the protruding electrodes with a high height are electrically connected to the connection electrodes 12. As a result, the resistance between the connection electrodes 12 arranged on the substrate 11 becomes the resistance element 30 formed in the semiconductor element region.

【0050】また異方性導電接着剤28の導電粒28b
の大きさを、非導電粒28cの直径に突起電極の台座部
分25aの高さを加えた寸法よりも大きいものを用いた
場合の実装構造を図5(b)に示す。高さの低い突起電
極と高さの高い突起電極との両方が、基板11に配置し
た接続電極12と導通する。この結果、基板11に配置
した接続電極12の間の抵抗は、抵抗素子30の中央部
に高さの低い突起電極を設けると、半導体素子領域に形
成した抵抗素子30の二分の一になる。このように異方
性導電接着剤28の導電粒28bの大きさを選ぶことに
より、任意の抵抗値を有する回路を実装時に選択するこ
とが可能である。
[0050] Also, the conductive particles 28b of the anisotropic conductive adhesive 28
FIG. 5B shows a mounting structure in which the size is larger than the sum of the diameter of the non-conductive particles 28c and the height of the pedestal portion 25a of the protruding electrode. Both the short protruding electrode and the high protruding electrode are electrically connected to the connection electrode 12 disposed on the substrate 11. As a result, the resistance between the connection electrodes 12 arranged on the substrate 11 becomes one-half that of the resistance element 30 formed in the semiconductor element region when a low-height protruding electrode is provided at the center of the resistance element 30. By selecting the size of the conductive particles 28b of the anisotropic conductive adhesive 28 in this way, it is possible to select a circuit having an arbitrary resistance value at the time of mounting.

【0051】この高さの異なる突起電極と大きさの異な
る導電粒とを組み合わせる半導体装置は、図5を用いて
説明した抵抗素子だけではなく、容量素子にも応用可能
である。
A semiconductor device in which protruding electrodes of different heights and conductive particles of different sizes are combined can be applied not only to the resistive element described using FIG. 5 but also to a capacitive element.

【0052】[0052]

【発明の効果】本発明による高さの異なる突起電極を有
する半導体装置を用いた実装構造および製造方法では、
基板に他の部品を搭載してできた段差に対応できるため
、小型高密度な実装が可能となる。さらに基板表面だけ
の実装だけではなく、基板に実装した部品の上からさら
に接続が可能となり、従来にない小型でしかも高密度な
半導体装置の実装構造および製造方法を提供することが
でき、絶大な効果が得られる。
[Effects of the Invention] In the mounting structure and manufacturing method using a semiconductor device having protruding electrodes of different heights according to the present invention,
Since it can accommodate steps created by mounting other components on the board, it enables compact, high-density mounting. Furthermore, it is now possible to connect not only on the surface of the board, but also on top of the components mounted on the board, making it possible to provide an unprecedented compact and high-density mounting structure and manufacturing method for semiconductor devices. Effects can be obtained.

【0053】また高さの異なる突起電極を有する半導体
装置を異方性導電接着剤を用いて接続する場合、同一の
半導体装置を使用するにもかかわらず、異方性導電接着
剤の導電粒の大きさを変えることで、半導体装置の内部
回路を選択することが可能になる。これはトリミング技
術に応用が可能で、従来は半導体装置の特性を検査して
、その結果によって、抵抗素子や容量素子等の受動部品
をハンダ付やレーザによるトリミング、あるいは内部メ
モリーによって制御するものはデータの書き込み作業が
必要となる。本発明によれば、ユーザーが半導体装置を
基板に装着する最終段階で異方性導電接着剤の導電粒の
大きさを選択し、任意の電気回路を選択することが可能
となり、低コストかつ作業が簡略な手法で多大な効果を
有する。
Furthermore, when semiconductor devices having protruding electrodes of different heights are connected using an anisotropic conductive adhesive, the conductive particles of the anisotropic conductive adhesive are connected even though the same semiconductor devices are used. By changing the size, it becomes possible to select the internal circuit of the semiconductor device. This can be applied to trimming technology. Conventionally, the characteristics of semiconductor devices were inspected, and passive components such as resistive elements and capacitive elements were trimmed by soldering or laser, or controlled by internal memory based on the results. Data writing work is required. According to the present invention, the user can select the size of the conductive particles of the anisotropic conductive adhesive at the final stage of attaching the semiconductor device to the board, and select an arbitrary electric circuit, thereby reducing cost and work. is a simple method with great effects.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の第1の実施例における半導体装置の実
装構造を示す断面図である。
FIG. 1 is a cross-sectional view showing a mounting structure of a semiconductor device in a first embodiment of the present invention.

【図2】本発明で用いる高さの異なる突起電極を有する
半導体装置の製造方法を工程順に示す断面図である。
FIG. 2 is a cross-sectional view illustrating, in order of steps, a method for manufacturing a semiconductor device having protruding electrodes of different heights used in the present invention.

【図3】本発明で用いる高さの異なる突起電極を有する
半導体装置の他の実施例における製造方法を工程順に示
す断面図である。
FIG. 3 is a cross-sectional view showing, in order of steps, a manufacturing method in another embodiment of a semiconductor device having protruding electrodes of different heights used in the present invention.

【図4】本発明による第2の実施例を示す半導体装置の
実装構造を示す断面図である。
FIG. 4 is a sectional view showing a mounting structure of a semiconductor device according to a second embodiment of the present invention.

【図5】本発明の半導体装置の実装構造における第3の
実施例を示す断面図である。
FIG. 5 is a sectional view showing a third embodiment of the semiconductor device mounting structure of the present invention.

【図6】従来例であるフリップチップボンディング法を
説明するための断面図である。
FIG. 6 is a cross-sectional view for explaining a conventional flip chip bonding method.

【図7】従来例であるチップオングラス法を説明するた
めの断面図である。
FIG. 7 is a cross-sectional view for explaining a conventional chip-on-glass method.

【符号の説明】[Explanation of symbols]

11  基板 12  接続電極 21  半導体装置 22  接続電極パッド 23  保護膜 24  共通電極膜 25  突起電極 11 Board 12 Connection electrode 21 Semiconductor device 22 Connection electrode pad 23 Protective film 24 Common electrode film 25 Protruding electrode

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】  半導体装置の接続電極パッド上に複数
の高さの異なる突起電極を有することを特徴とする半導
体装置の実装構造。
1. A mounting structure for a semiconductor device, comprising a plurality of protruding electrodes having different heights on connection electrode pads of the semiconductor device.
【請求項2】  半導体装置の半導体素子形成面上の全
面に保護膜を形成し、フォトリソグラフィーとエッチン
グにより接続電極パッド上に開口部を形成し、全面に共
通電極膜を形成する工程と、全面にメッキレジストを形
成し高さの高い突起電極の形成領域に開口部を形成する
工程と、メッキにより突起電極の台座部分を形成し、該
メッキレジストを除去する工程と、メタルマスクを前記
半導体装置上に配置し、該メタルマスク開口の突起電極
の形成領域にハンダを形成し、熱処理を行い該ハンダを
丸めて突起電極の先端部を形成し、該突起電極をマスク
にして前記共通電極膜をエッチングする工程とを有する
ことを特徴とする半導体装置の製造方法。
2. A step of forming a protective film on the entire surface of the semiconductor element forming surface of the semiconductor device, forming an opening on the connection electrode pad by photolithography and etching, and forming a common electrode film on the entire surface; a step of forming a plating resist on the substrate and forming an opening in a region where a high protruding electrode is to be formed; a step of forming a pedestal portion of the protruding electrode by plating and removing the plating resist; and a step of applying a metal mask to the semiconductor device. solder is formed on the protruding electrode formation region of the metal mask opening, heat-treated, the solder is rolled up to form the tip of the protruding electrode, and the common electrode film is formed using the protruding electrode as a mask. 1. A method for manufacturing a semiconductor device, comprising the step of etching.
【請求項3】  半導体装置の半導体素子形成面上の全
面に保護膜を形成し、フォトリソグラフィーとエッチン
グにより接続電極パッド上に開口部を形成し、全面に共
通電極膜を形成する工程と、全面に第1のメッキレジス
トを形成し高さの高い突起電極の形成領域に開口部を形
成する工程と、メッキにより突起電極の台座部分を形成
し、該第1のメッキレジストを除去する工程と、全面に
第2のメッキレジストを形成し突起電極の形成領域に開
口部を形成し、メッキにより突起電極の先端部を形成し
、該第2のメッキレジストを除去し、該突起電極をマス
クにして前記共通電極膜をエッチングする工程とを有す
ることを特徴とする半導体装置の製造方法。
3. A step of forming a protective film on the entire surface of the semiconductor element forming surface of the semiconductor device, forming an opening on the connection electrode pad by photolithography and etching, and forming a common electrode film on the entire surface; forming a first plating resist and forming an opening in the formation region of the tall protruding electrode; forming a pedestal portion of the protruding electrode by plating, and removing the first plating resist; A second plating resist is formed on the entire surface, an opening is formed in the region where the protruding electrode is to be formed, a tip of the protruding electrode is formed by plating, the second plating resist is removed, and the protruding electrode is used as a mask. A method for manufacturing a semiconductor device, comprising the step of etching the common electrode film.
【請求項4】  半導体装置の半導体素子形成面上の全
面に保護膜を形成し、フォトリソグラフィーとエッチン
グにより接続電極パッド上に開口部を形成し、全面に共
通電極膜を形成し、さらに全面に感光性レジストを形成
し、フォトリソグラフィーにより高さの高い突起電極の
形成領域に開口部を形成する工程と、全面に突起電極の
台座部分となる金属膜を形成する工程と、前記感光性レ
ジストを除去することにより前記感光性レジスト上に形
成した金属膜を除去し、前記感光性レジストの開口部に
突起電極の台座部分を形成する工程と、メタルマスクを
前記半導体装置上に配置し、該メタルマスク開口の突起
電極の形成領域にハンダを形成し、熱処理を行い該ハン
ダを丸めて突起電極の先端部を形成し、該突起電極をマ
スクにして前記共通電極膜をエッチングする工程とを有
することを特徴とする半導体装置の製造方法。
4. A protective film is formed on the entire surface of the semiconductor element formation surface of the semiconductor device, an opening is formed on the connection electrode pad by photolithography and etching, a common electrode film is formed on the entire surface, and a common electrode film is formed on the entire surface. A step of forming a photosensitive resist and forming an opening in a region where a tall protruding electrode is to be formed by photolithography, a step of forming a metal film that will become a pedestal part of the protruding electrode on the entire surface, and a step of forming the photosensitive resist. removing the metal film formed on the photosensitive resist and forming a pedestal portion of a protruding electrode in the opening of the photosensitive resist; placing a metal mask on the semiconductor device; forming solder in a region in which a protruding electrode is to be formed in a mask opening, performing heat treatment to round the solder to form a tip of the protruding electrode, and etching the common electrode film using the protruding electrode as a mask. A method for manufacturing a semiconductor device, characterized by:
【請求項5】  半導体装置の半導体素子形成面上の全
面に保護膜を形成し、フォトリソグラフィーとエッチン
グにより接続電極パッド上に開口部を形成し、全面に共
通電極膜を形成し、さらに全面に感光性レジストを形成
し、フォトリソグラフィーにより高さの高い突起電極の
形成領域に開口部を形成する工程と、全面に突起電極の
台座部分となる金属膜を形成する工程と、前記感光性レ
ジストを除去することにより前記感光性レジスト上に形
成した該金属膜を除去して、前記感光性樹脂の開口部に
突起電極の台座部分を形成する工程と、全面にメッキレ
ジストを形成し、突起電極の形成領域に開口部を形成し
、メッキにより突起電極の先端部を形成し、該メッキレ
ジストを除去し、該突起電極をマスクにして前記共通電
極膜をエッチングする工程とを有することを特徴とする
半導体装置の製造方法。
5. A protective film is formed on the entire surface of the semiconductor element forming surface of the semiconductor device, an opening is formed on the connection electrode pad by photolithography and etching, a common electrode film is formed on the entire surface, and a common electrode film is formed on the entire surface. A step of forming a photosensitive resist and forming an opening in a region where a tall protruding electrode is to be formed by photolithography, a step of forming a metal film that will become a pedestal part of the protruding electrode on the entire surface, and a step of forming the photosensitive resist. A step of removing the metal film formed on the photosensitive resist to form a pedestal portion of the protruding electrode in the opening of the photosensitive resin, and forming a plating resist on the entire surface of the protruding electrode. The method is characterized by comprising the steps of forming an opening in a formation region, forming a tip of a protruding electrode by plating, removing the plating resist, and etching the common electrode film using the protruding electrode as a mask. A method for manufacturing a semiconductor device.
JP3137054A 1990-12-13 1991-05-14 Packaging structure of semiconductor device and its manufacture Pending JPH04242939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3137054A JPH04242939A (en) 1990-12-13 1991-05-14 Packaging structure of semiconductor device and its manufacture

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP41010890 1990-12-13
JP2-410108 1990-12-13
JP3137054A JPH04242939A (en) 1990-12-13 1991-05-14 Packaging structure of semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH04242939A true JPH04242939A (en) 1992-08-31

Family

ID=26470482

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3137054A Pending JPH04242939A (en) 1990-12-13 1991-05-14 Packaging structure of semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH04242939A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0630056A1 (en) * 1993-05-28 1994-12-21 Toshiba Ave Co., Ltd Use of anisotropically conductive film for connecting leads of wiring board with electrode pads of photoelectric converting device and mounting method of the device
EP1403685A3 (en) * 1997-03-06 2004-04-14 Sharp Kabushiki Kaisha Liquid crystal display device
US6965552B2 (en) * 2002-02-01 2005-11-15 Hitachi, Ltd. Mounting method for optical device and optical head equipment
CN100410740C (en) * 2004-07-13 2008-08-13 精工爱普生株式会社 Electrooptical device, mounting structure, and electronic apparatus

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0630056A1 (en) * 1993-05-28 1994-12-21 Toshiba Ave Co., Ltd Use of anisotropically conductive film for connecting leads of wiring board with electrode pads of photoelectric converting device and mounting method of the device
US5506401A (en) * 1993-05-28 1996-04-09 Kabushiki Kaisha Toshiba Photoelectric converting device mounting apparatus with anisotropically conductive film for connecting leads of wiring board and electrode pads of photoelectric converting device and fabrication method thereof
US5786589A (en) * 1993-05-28 1998-07-28 Kabushiki Kaisha Toshiba Photoelectric converting device with anisotropically conductive film for connecting leads of wiring board and electrode pads of photoelectric converting device
EP1403685A3 (en) * 1997-03-06 2004-04-14 Sharp Kabushiki Kaisha Liquid crystal display device
EP1408364A1 (en) * 1997-03-06 2004-04-14 Sharp Kabushiki Kaisha Liquid crystal display device
EP1403686A3 (en) * 1997-03-06 2004-04-14 Sharp Kabushiki Kaisha Liquid crystal display device
US6965552B2 (en) * 2002-02-01 2005-11-15 Hitachi, Ltd. Mounting method for optical device and optical head equipment
CN100410740C (en) * 2004-07-13 2008-08-13 精工爱普生株式会社 Electrooptical device, mounting structure, and electronic apparatus
US7518691B2 (en) 2004-07-13 2009-04-14 Seiko Epson Corporation Electrooptical device, mounting structure, and electronic apparatus having wiring formed on and protruding from a base material to directly under an input bump on a semiconductor device

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