JPS5988863A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5988863A
JPS5988863A JP57199206A JP19920682A JPS5988863A JP S5988863 A JPS5988863 A JP S5988863A JP 57199206 A JP57199206 A JP 57199206A JP 19920682 A JP19920682 A JP 19920682A JP S5988863 A JPS5988863 A JP S5988863A
Authority
JP
Japan
Prior art keywords
substrate
main surface
lsi
electrode
substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57199206A
Other languages
Japanese (ja)
Inventor
Tsuyoshi Shiragasawa
白ケ澤 強
Shuji Kondo
修司 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57199206A priority Critical patent/JPS5988863A/en
Publication of JPS5988863A publication Critical patent/JPS5988863A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To contrive to make composite-multifunctional and speed up by a method wherein a desired electrode is directly connected by opposing the main surface of another LSI substrate to one LSI substrate, which are fixed to each other. CONSTITUTION:Functional elements are integrated on the main surface of the substrate 1 and covered with a protection film 2, a part of the film 2 is removed, and a bump electrode 3 is laid. Functional elements are integrated also on the main surface of the substrate 4, a protection film 5 and an electrode 6 are formed. The main surface of the substrate 4 is placed on the main surface of the substrate 1 in opposition thereto, and the solder plate electrodes 6 and 3 are heated and connected. If necessary, metallic lead wires 7 are connected simultaneously at the time of mutual connection of the electrodes. Epoxy resin 8 is applied on the side surface of the substrates and in gaps and solidified, resulting in adhesion. This constitution enables to make multifunctional to a high density by superposing LSI's without increasing the area of the substrate.

Description

【発明の詳細な説明】 産業上の利用分腎 本発明は、゛1′導体装置に関するものであり、特に高
密度多機能化11′導体装置を提供するものである。
DETAILED DESCRIPTION OF THE INVENTION Industrial Application The present invention relates to a 11' conductor device, and particularly provides a high-density, multi-functional 11' conductor device.

従来例の構成とその問題点 システム機器の小形化、高速化の要求に伴い、半導体集
積回路(以降LSIと称する)i!”?i密度化。
Conventional configuration and its problems With the demand for smaller and faster system equipment, semiconductor integrated circuits (hereinafter referred to as LSI) i! ”?i densification.

多機能化をする1fが望外れている。との為、 LSI
パターンの微細化がはかられているが、微細化に1″1
′う種々の間1mある為、実用トは微細化には限界があ
る。又、多機C肚化へのアプローチとしては高集積化に
よる大規模LSI化が行われている。一方、多機能化す
る為に半導体プロセスの複合化も一部に試みられている
が実用化にd、至−1ていない。
The multi-functional 1F is disappointing. Because of this, LSI
Efforts are being made to make the pattern finer, but it takes 1″1 to make the pattern finer.
'Since there is a distance of 1 m between various parts, there is a limit to miniaturization in practical use. Also, as an approach to multi-machine C storage, large-scale LSIs are being implemented through high integration. On the other hand, some attempts have been made to combine semiconductor processes in order to increase the number of functions, but this has not been put to practical use.

即ち屓種の゛I′−導体デバイスを同一基板上に形成す
る事は現在の技術では困難とされる。
That is, it is difficult with the current technology to form various types of I'-conductor devices on the same substrate.

この為、)14導体装置を多機能化、高積化する為に同
種又は異種の半導体基板を高密度実装する技術が提案さ
れ、一部に実施されている。
For this reason, in order to make the )14 conductor device multi-functional and highly stacked, a technique for high-density mounting of semiconductor substrates of the same type or different types has been proposed and partially implemented.

従来の一例を第1図をもとに説明する。A conventional example will be explained based on FIG.

第1図に於いて、セラミック基板1の上向上には、配線
パターン2及び外部電極3が設けてあり、史にLSIチ
ップ4の電極部と、同基板1−配線パターン2の−・部
とを接続する為の内部電極(図ボせず)が配置されてい
る。LSIチップ4の電極は、凸状をなす、いわゆるバ
ンプ形式で形成され、該バンプと、前記内部電極とは直
接に接続される“ソリソプチノブ″により接続される。
In FIG. 1, a wiring pattern 2 and an external electrode 3 are provided on the upper part of the ceramic substrate 1, and the electrode part of the LSI chip 4 and the - part of the wiring pattern 2 of the ceramic substrate 1 are connected to each other. Internal electrodes (not shown) are arranged to connect the The electrodes of the LSI chip 4 are formed in a convex shape, a so-called bump type, and the bumps and the internal electrodes are directly connected by a "sorisoptinob".

本構成によれば、同・基板上に複数の同オΦ、又3・・
−7 は異種のLSIチップを載置し更にLSIチップ相互を
配線できる為、従来の構成に比較するとLSIを高密度
に実装する事が可能と々っている。
According to this configuration, there are a plurality of the same OΦ on the same board, and 3...
-7 allows different types of LSI chips to be mounted and the LSI chips to be interconnected, making it possible to mount LSIs at a higher density than with conventional configurations.

しかしながら、本構成には以下に示す問題がある。However, this configuration has the following problems.

即ち、同一基板上に複数のLSIチップを二次元的に配
置する為、実装するLSIの個数が増えるに従い、基板
面積が増加する。
That is, since a plurality of LSI chips are two-dimensionally arranged on the same substrate, the substrate area increases as the number of LSIs to be mounted increases.

又チップ相互の電極は、配線を用いて接続されており、
配線容量、配線抵抗が存在し高速動作の為の障害となっ
ている。
Also, the electrodes of each chip are connected using wiring,
The presence of wiring capacitance and wiring resistance is an obstacle to high-speed operation.

発明の目的 本発明は以上の様な問題に鑑みなされたものであり、L
S4相互を高密度に接続し、複合多機能半導体装置を実
現し更に高速化を実現可能とする)1′導体装置を提供
するものである。
Purpose of the Invention The present invention was made in view of the above problems, and
The present invention provides a 1' conductor device which connects S4 to each other at high density, realizes a composite multi-functional semiconductor device, and makes it possible to realize higher speed.

発明の構成 本発明は高密度、高速化を実現する為に1個のLSI基
板1の主面上に、1個又は複数のLSI基板2の主面を
対向せしめ、LSI基板1の電極部とLSI基板2の所
望電極部を直接接続し、LSI基板1.2を相互に固着
して得られる゛I4導体装置である。
Composition of the Invention In order to achieve high density and high speed, the present invention has the main surface of one or more LSI substrates 2 facing the main surface of one LSI substrate 1, and the electrode portions of the LSI substrate 1 and This is an I4 conductor device obtained by directly connecting the desired electrode portions of the LSI substrate 2 and fixing the LSI substrates 1.2 to each other.

実施例の説明 本発明による半導体装置の実施例を第2図、第3図及び
第4図を用いて説明する。第2図〜第4図ともに本発明
半導体装置の断面図を示すものである。
DESCRIPTION OF EMBODIMENTS An embodiment of a semiconductor device according to the present invention will be described with reference to FIGS. 2, 3, and 4. Both FIGS. 2 to 4 show cross-sectional views of the semiconductor device of the present invention.

先ず第1図に於いて半導体基板1の主面にはトランジス
タ、抵抗等の機能素子が集積化形成され、更に同基板主
面上には表面保護膜2が形成されている。又同基板に対
する電気信号の入出力端子を構成する電極3は、前記表
面保護膜2の一部を除去したのち、凸状に、いわゆるバ
ンプ形式で構成される。次に半導体基板4の主面にも機
能素子が集積され、その主面上には表面保護膜5及び電
極6が設けである。ここで半導体基板4の主面は、前記
半導体基板1の主面上に対向して載置され、更に、半導
体基板4の電極6は半導体基板1の電極3と電気的に接
続されている。ここで電極相互の接続はハンダを用いて
おり、電極形成時に電極6、− ・ 部にハンダメッキを施しておき、接続時に加熱する事に
より容易に実現できる。又、必要があれば、当該半導体
装置の外にリードを取り出す事も可能である。本実施例
に於いては、電極相互の接続時に金属リード線7を同時
に接続する事により実現している。
First, in FIG. 1, functional elements such as transistors and resistors are integrated and formed on the main surface of a semiconductor substrate 1, and a surface protection film 2 is further formed on the main surface of the substrate. Further, the electrode 3 constituting the input/output terminal for electrical signals to the substrate is formed in a convex shape, so-called bump type, after a part of the surface protection film 2 is removed. Next, functional elements are integrated on the main surface of the semiconductor substrate 4, and a surface protection film 5 and an electrode 6 are provided on the main surface. Here, the main surface of the semiconductor substrate 4 is placed to face the main surface of the semiconductor substrate 1, and furthermore, the electrode 6 of the semiconductor substrate 4 is electrically connected to the electrode 3 of the semiconductor substrate 1. Here, the electrodes are connected to each other using solder, and this can be easily achieved by applying solder plating to the electrode 6, - · portion when forming the electrode, and heating it when connecting. Furthermore, if necessary, it is also possible to take out the leads outside the semiconductor device. In this embodiment, this is achieved by connecting the metal lead wires 7 at the same time when the electrodes are connected to each other.

以上の様に電極相互を接続したのち、前記半導体基板1
と2は相互に固着される。本実施例に於いては、相互の
基板側面及び基板間のすき間に、エポキシ樹脂8を塗布
し、固形化接着している。
After connecting the electrodes as described above, the semiconductor substrate 1
and 2 are fixed to each other. In this embodiment, epoxy resin 8 is applied to the side surfaces of the substrates and the gaps between the substrates, and the substrates are solidified and bonded.

本方法に依れば同種又は異種のLSIを積み重ねる為に
基板面積を増やすことなく高密度に多機能化を実現でき
る。
According to this method, high-density multifunctionalization can be realized without increasing the board area due to stacking LSIs of the same type or different types.

本実施例に於いては、当該半導体装置外部との接続の為
にリード線を新たに設けたが、本発明は新たにリード線
を設けなくても、外部との接続を行うことができる。
In this embodiment, a new lead wire was provided for connection to the outside of the semiconductor device, but the present invention allows connection to the outside without providing a new lead wire.

第3図に於いて半導体基板1に対向載置する半導体基板
4は、少なくとも半導体基板1の電極のうち外部接続電
極3′の上には配置しない様にする。
In FIG. 3, the semiconductor substrate 4 placed opposite the semiconductor substrate 1 is arranged so as not to be placed on at least the external connection electrode 3' of the electrodes of the semiconductor substrate 1.

このあと所望接続電極3及び6を接続し、基板相互をエ
ポキシ樹脂8により接着固定せしめる。以上の方法によ
れば外部接続型$3’は露出しており、外部との接続が
可能となる。本実施例に於いてはワイヤボンドによりA
71線9を介し外部との接続を行っている。
Thereafter, desired connection electrodes 3 and 6 are connected, and the substrates are bonded and fixed to each other with epoxy resin 8. According to the above method, the external connection type $3' is exposed and can be connected to the outside. In this example, A is connected by wire bonding.
It is connected to the outside via a 71 line 9.

以上の実施例に於いては1個の半導体基板に対して1個
の半導体基板を接続したが、1個の半導体基板に対して
複数個の半導体基板を接続する事も可能である。
In the above embodiments, one semiconductor substrate is connected to one semiconductor substrate, but it is also possible to connect a plurality of semiconductor substrates to one semiconductor substrate.

第4図に於いて半導体基板1の主面に対向して半導体基
板4.4’、4が載置され、所望電極相互が電気的に接
続され、基板相互も接着材(本実施例に於いてはエポキ
シ樹脂)により固着されている。本例によれば種々の機
[LSI又は種々の種類を同一半導体基板上に載置でき
複合機能を有する半導体装置を高密度に実現できる。例
えば、cpu用LSIと入出力用LSI、更にメモリL
SIやセンサーデバイス等を同一基板上に形成する事も
可能である。
In FIG. 4, semiconductor substrates 4, 4', 4 are placed facing the main surface of the semiconductor substrate 1, desired electrodes are electrically connected to each other, and the substrates are also bonded with adhesive (in this embodiment). It is fixed with epoxy resin). According to this example, various devices (LSIs) or various types can be mounted on the same semiconductor substrate, and a semiconductor device having multiple functions can be realized at high density. For example, a CPU LSI, an input/output LSI, and a memory LSI.
It is also possible to form SI, sensor devices, etc. on the same substrate.

7 発明の効果 本発明の゛1′導体装置は、゛14導体基板相r、1−
を縦方向に接続する構造をなし、基板間電極相41′、
を直接に接続する為、多機rト土導体装置を高密度に実
現で六、更に配線抵抗、配線界1i゛を大幅に軽減でき
る為、高速動作を可能ならしめるものである。
7 Effects of the Invention The 1' conductor device of the present invention has 14 conductor substrate phases r, 1-
The inter-substrate electrode phases 41',
Since the wires are directly connected to each other, it is possible to realize a high-density multi-layer conductor device, and furthermore, the wiring resistance and wiring field can be significantly reduced, making high-speed operation possible.

又、本発明によれば、゛1′導体ノi(板主面1−の能
動領域が本導体装置表面又C1裏面から深くなる為、α
線に」:るソフトエラーも大幅に減少せしめることがで
きる。
Also, according to the present invention, since the active area of the conductor 1' (i) becomes deeper from the surface of the conductor device or the back surface of C1, α
It is also possible to significantly reduce soft errors that occur on lines.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の?1′導体装置の構成を示す図、第2図
、第3図、第4図はそれぞれ本発明の実施例における半
導体装置の断面図である。 1.4・・・・・N4導体基板、3,6・・・・・・電
極、7・・・・・リード線、8・・・ ・エポキシ樹脂
、9・・・・・A7!線。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 ? 第2図
Is Figure 1 conventional? 1', which shows the structure of the conductor device, and FIGS. 2, 3, and 4 are sectional views of the semiconductor device according to the embodiments of the present invention, respectively. 1.4...N4 conductor board, 3,6...electrode, 7...lead wire, 8... -epoxy resin, 9...A7! line. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure? Figure 2

Claims (1)

【特許請求の範囲】[Claims] 機能素子と電極部を有する第1の)1′導体基板の主面
に、機能素子を集積化し電極部を有する他の少くとも1
個の第2の半導体基板tの主面を対向載置せしめ、前記
第1と第2の基板の所望電極相互を接続し、基板相互を
固着ぜしめてなる゛1′導体装置。
On the main surface of the first) 1' conductor substrate having the functional element and the electrode part, at least another one having the functional element integrated therein and having the electrode part.
A conductor device (1) is constructed by placing the main surfaces of two second semiconductor substrates t facing each other, connecting desired electrodes of the first and second substrates to each other, and fixing the substrates to each other.
JP57199206A 1982-11-12 1982-11-12 Semiconductor device Pending JPS5988863A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57199206A JPS5988863A (en) 1982-11-12 1982-11-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57199206A JPS5988863A (en) 1982-11-12 1982-11-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5988863A true JPS5988863A (en) 1984-05-22

Family

ID=16403898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57199206A Pending JPS5988863A (en) 1982-11-12 1982-11-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5988863A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6189657A (en) * 1984-10-08 1986-05-07 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JPH0548359U (en) * 1991-11-28 1993-06-25 三洋電機株式会社 Semiconductor device
WO1998058409A1 (en) * 1997-06-16 1998-12-23 Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho Process for mounting semiconductor chip, process for manufacturing chip-on-chip structure, and process for manufacturing chip-on-board structure
EP0913866B1 (en) * 1997-03-10 2005-07-20 Seiko Epson Corporation Semiconductor Device and Circuit Board Having the Same Mounted Thereon

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6189657A (en) * 1984-10-08 1986-05-07 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JPH0548359U (en) * 1991-11-28 1993-06-25 三洋電機株式会社 Semiconductor device
EP0913866B1 (en) * 1997-03-10 2005-07-20 Seiko Epson Corporation Semiconductor Device and Circuit Board Having the Same Mounted Thereon
WO1998058409A1 (en) * 1997-06-16 1998-12-23 Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho Process for mounting semiconductor chip, process for manufacturing chip-on-chip structure, and process for manufacturing chip-on-board structure

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