JP3692353B2 - Assembling method of semiconductor device - Google Patents

Assembling method of semiconductor device Download PDF

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Publication number
JP3692353B2
JP3692353B2 JP2002367536A JP2002367536A JP3692353B2 JP 3692353 B2 JP3692353 B2 JP 3692353B2 JP 2002367536 A JP2002367536 A JP 2002367536A JP 2002367536 A JP2002367536 A JP 2002367536A JP 3692353 B2 JP3692353 B2 JP 3692353B2
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connection
lsi
pad
semiconductor device
opening
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JP2003179096A (en
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正夫 佐々木
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Description

【０００１】
【発明の属する技術分野】
本発明は、集積回路と外部回路に接続されて該集積回路に信号を入出力するパッド部とを備えた半導体装置（以下、ＬＳＩという）のアッセンブリ方法に関するものである。
【０００２】
【従来の技術】
図２（ａ）〜（ｃ）は、従来のＬＳＩ（その１）を示す平面図であり、同図（ａ）はＬＳＩのパッド部のレイアウト図であり、同図（ｂ）は同図（ａ）のＡ部分の拡大図であり、同図（ｃ）は同図（ａ）の接続状態を示す図である。
【０００３】
このＬＳＩ１０のアッセンブリ方法では、図示しない集積回路が基板に形成される共に、該集積回路に信号を入出力する複数の配線パタンが形成される。この複数の配線パタンに端子となる複数のパッド１１が形成される。ＬＳＩ１０の表面は、保護膜１２で覆われるが、複数のパッド１１の箇所の保護膜１２が除去されて窓１３が形成される。窓１３と該窓１３から露出したパッド１１とで、複数のパッド部１４が形成される。
【０００４】
これらのパット部１４は、ワイヤボンディング用のパッド部であり、図２（ｃ）のように、パッド部１４の窓１３から露出したパッド１１と外部回路との間がワイヤ１５で接続されることにより、外部回路とＬＳＩ１０とのアッセンブリが行われる。
【０００５】
図３（ａ）〜（ｃ）は、従来のＬＳＩ（その２）を示す平面図であり、同図（ａ）はＬＳＩのパッド部のレイアウト図であり、同図（ｂ）は同図（ａ）のＢ部分の拡大図であり、同図（ｃ）は同図（ａ）の接続状態を示す図である。
【０００６】
このＬＳＩ２０には、例えば前述のＬＳＩ１０と同様の集積回路が基板に形成されると共に、複数の配線パタンが形成される。この複数の配線パタンに端子となるＬＳＩ１０と同様の複数のパッド１１が形成される。ＬＳＩ２０の表面は、保護膜２１で覆われるが、各パッド１１の箇所の保護膜２１が除去されて図３（ｂ）のような窓２２が形成され、該窓２２から露出したパッド１１上に、半田等で構成されたバンプ２３が堆積され、保護膜２１の表面からさらに突出して形成される。この窓２２とバンプ２３とで、パッド部２５が形成される。
【０００７】
これらのパット部２５のバンプ２３を用いて、外部回路２６を直接接続することより、図３（ｃ）のように、ＴＡＢ（ Tape Automated Bonding ）或いはＣＯＧ（ Chip On Glass ）方式のアッセンブリリ、すなわち、外部テープ基材や外部ガラス基板等の実装基材とのアッセンブリが行われる。
【０００８】
【発明が解決しようとする課題】
しかしながら、従来のＬＳＩのアッセンブリ方法では、次のような課題があった。
【０００９】
ＬＳＩ１０，２０は、複数のパッド部１４，２５の構造によって外部回路に対する接続方法が異なるので、該ＬＳＩ１０，２０が、例え同じ集積回路と配線パタンを持ち、同じ動作を行うものであっても、パッド部１４，２５の構造で決まる１種類のアッセンブリしか実施することができなかった。そのため、ワイヤボンドで外部回路と接続するＬＳＩ１０と、ＴＡＢ方式で外部回路の接続をするＬＳＩ２０とを、別々に作製することになり、開発効率及び量産効果を向上できないという課題があった。
【００１０】
【課題を解決するための手段】
前記課題を解決するために、本発明のＬＳＩのアッセンブリ方法では、半導体チップと、前記半導体チップの表面上に形成された共通の配線パタンに形成された第１の接続部および第２の接続部と、前記第１の接続部と実装基材とをワイヤを用いて接続する際に用いられる第１の開口部と前記第２の接続部と前記実装基材とをバンプを用いて接続する際に用いられる第２の開口部とを備え前記配線パタンおよび前記配線パタンが形成された前記半導体チップの前記表面を覆う保護膜と、を有するＬＳＩを準備する。
【００１１】
前記第１の開口部を用いたワイヤ接続による実装形態および前記第２の開口部を用いたバンプ接続による実装形態のうち、要求に応じて前記２つの実装形態のいずれか一方を選択して前記半導体装置と前記実装基材とのアッセンブリを行う。これにより、同一の構造のＬＳＩで複数の実装形態が選択的にとれるようになる。
【００１３】
【発明の実施の形態】
（第１の実施形態）
図１（ａ），（ｂ）は、本発明の第１の実施形態を示すＬＳＩの平面図であり、同図（ａ）はパッド部の配置を示すレイアウト図であり、同図（ｂ）は同図（ａ）のＣ部分の拡大図である。
【００１４】
このＬＳＩ３０のアッセンブリ方法では、矩形の基板に形成された半導体チップである図示しない集積回路と、該集積回路に接続された図示しないアルミニウム等で形成された複数の配線パタンとを有し、該ＬＳＩ３０の表面が、保護膜３１で覆われる。複数の配線パタンには、端子となる複数のパッド３２が形成され、該各パッド３２の位置に外部回路に対して信号を入出力するパッド部４０がそれぞれ形成される。
【００１５】
図４は、図１中のパッド部４０の構造を示す断面図である。
【００１６】
複数のパッド部４０には、共通のパッド３２に対して設けられた第１の接続部４０Ａと第２の接続部４０Ｂとが、それぞれ形成される。接続部４０Ａには、保護膜３１が除去された第２の開口部である第１の窓４１と、パッド３２における該窓４１から露出した部分４２とが、形成される。接続部４０Ｂには、保護膜３１が除去された第１の開口部である第２の窓４３と、パッド３２における窓４３から露出した部分４４と、その部分４４上に堆積された導電性部材のバンプ４５とが、形成される。パンプ４５は、例えば銅等の下地層４５ａと、金や半田等の接続層４５ｂとがパッド３２に積層されると共に、保護膜３１から突起して形成される。
【００１７】
このＬＳＩ３０のアッセンブリ方法では、各パッド部４０の接続部４０Ａが基板の中心側を向き、接続部４０Ｂが基板の外側を向くように、複数のパッド部４０がレイアウトされる。
【００１８】
図５（ａ），（ｂ）は、図１の接続例を示す平面図である。
【００１９】
ＬＳＩ３０のパッド部４０における接続部４０Ａは、ワイヤボンディングのアッセンブリに適した構造であり、接続部４０ＢはＴＡＢ方式やＣＯＧ方式のアッセンブリに適した構造である。そのため、ＬＳＩ３０をワイヤボンディングで外部回路に接続する要求がある場合には、図５（ａ）のように、各パッド部４０の接続部４０Ａと外部回路との間をワイヤ３５でそれぞれ接続する。ＬＳＩ３０をＴＡＢ方式やＣＯＧ方式で外部回路に接続する要求がある場合には、接続部４０Ｂにおける接続層４５ｂを、テープや硝子５０に形成された外部回路に直接接続する。
【００２０】
以上のように、この第１の実施形態のアッセンブリ方法では、各パッド部４０に、共通のパッド３２に対して外部回路を接続するための２つの接続部４０Ａ，４０Ｂをそれぞれ形成し、その接続部４０Ａをワイヤボンディングによって外部回路と接続可能な構造とし、接続部４０ＢをＴＡＢ方式やＣＯＧ方式によって外部回路と接続可能な構造にしたので、ＬＳＩ３０は、複数の実装形態がとれるようになる。そのため、ＬＳＩ３０のパッド部４０の変更を行わなくても、ＬＳＩ３０の完成後に、要求に応じた実装形態を選択すれば、複数のアッセンブリが可能になるので、ＬＳＩ３０の開発効率が向上すると共に、量産効率が向上する。
【００２１】
（第２の実施形態）
図６は、本発明の第２の実施形態を示すＬＳＩの平面図である。
【００２２】
このＬＳＩ６０のアッセンブリ方法では、矩形の基板に形成された半導体チップである図示しない集積回路と、該集積回路に接続された図示しないアルミニウム等で形成された複数の配線パタンとを有し、該ＬＳＩ６０の表面が、保護膜６１で覆われる。複数の配線パタンには端子となる複数のパッド６２が形成され、該各パッド６２の位置に、外部回路に対して信号を入出力するパッド部７０がそれぞれ形成される。
【００２３】
各パッド部７０には、図４と同様の構造の第１の接続部４０Ａ及び第２の接続部４０Ｂがそれぞれ形成される。ただし、このＬＳＩ６０では、各パッド部７０の接続部４０Ａが基板の外側を向き、接続部４０Ｂが基板の中心側をそれぞれ向くように、複数のパッド部７０がレイアウトされる。
【００２４】
図７（ａ），（ｂ）は、図６の接続例を示す平面図である。
【００２５】
ＬＳＩ６０のパッド部７０における接続部４０Ａは、ワイヤボンディングのアッセンブリに適した構造であり、接続部４０ＢはＴＡＢ方式やＣＯＧ方式のアッセンブリに適した構造である。そのため、ＬＳＩ６０をワイヤボンディングで外部回路に接続する要求がある場合には、図７（ａ）のように、各パッド部７０の外側の接続部４０Ａと外部回路との間をワイヤ６５でそれぞれ接続する。さらに、必要に応じて、チップコンデンサ等のデバイス６６，６７を、中心側の接続部４０Ｂに接続して搭載する。
【００２６】
ＬＳＩ６０をＴＡＢ方式やＣＯＧ方式で外部回路に接続する要求がある場合には、中心側の接続部４０Ｂにおける接続層４５ｂを、テープや硝子５０に形成された外部回路に直接接続する。さらに追加して、ワイヤボンディングで他の外部回路に接続する要求がある場合には、図７（ｂ）のように、外側の接続部４０Ａと外部回路との間をワイヤ６５でそれぞれ接続する。
【００２７】
以上のように、この第２の実施形態のアッセンブリ方法では、各パッド部７０に２つの接続部４０Ａ，４０Ｂをそれぞれ形成し、その接続部４０Ａを基板の外側に向け、接続部４０Ｂを中心側に向けてレイアウトするので、第１の実施形態の製造方法と同様に、ワイヤボンディングによる外部回路との接続が可能になると共に、ＴＡＢ方式やＣＯＧ方式による外部回路との接続が可能になり、複数の実装形態がとれる。さらに、その両方の実装形態を同時に施すことが可能になり、ＬＳＩ６０の開発効率が向上すると共に、量産効率が向上する。その上、例えばワイヤボンディングによる実装を行った状態で、従来ではＬＳＩ６０の周辺回路に設けていたデバイス６６，６７を該ＬＳＩ６０上に搭載することが可能になり、このＬＳＩ６０を組み込むシステムを小型化できる。
【００２８】
（第３の実施形態）
図８は、本発明の第３の実施形態を示すＬＳＩの平面図である。
【００２９】
このＬＳＩ８０のアッセンブリ方法では、矩形の基板に形成された半導体チップである図示しない集積回路と、該集積回路に接続された図示しないアルミニウム等で形成された複数の配線パタンとを有し、該ＬＳＩ８０の表面が、保護膜８１で覆われる。複数の配線パタンには端子となる複数のパッド８２が形成され、該各パッド８２の位置に、外部回路に対して信号を入出力する２種類のパッド部９０，１００が適宜形成される。
【００３０】
図９は、図８中のパッド部１００の構造を示す断面図である。
【００３１】
パッド部９０には、図４と同様の構造の第１の接続部４０Ａ及び第２の接続部４０Ｂがそれぞれ形成される。これに対し、パッド部１００には、図９のように、共通のパッド８２に対して設けられた第１の接続部１００Ａと、２つの第２の接続部１００Ｂ，１００Ｃとが形成される。
【００３２】
接続部１００Ａには、保護膜８１が除去された第２の開口部である第１の窓１０１と、パッド８２における該窓１０１から露出した部分１０２とが形成される。接続部１００Ｂには、保護膜８１が除去された第１の開口部である第２の窓１０３と、パッド８２における窓１０３から露出した部分１０４と、その部分１０４上に堆積された導電性部材のバンプ１０５とが形成される。パンプ１０５は、例えば銅等の下地層１０５ａと、金や半田等の接続層１０５ｂとがパッド８２に積層されて形成される。接続部１００Ｃには、保護膜８１が除去された第１の開口部である第２の窓１０６と、パッド８２における窓１０６から露出した部分１０７と、その部分１０７上に堆積された導電性部材のバンプ１０８とが形成される。パンプ１０８は、例えば銅等の下地層１０８ａと、金や半田等の接続層１０８ｂとがパッド８２に積層されて保護膜８１から突起して形成される。
【００３３】
このように、ＬＳＩ８０の各パッド部９０，１００における接続部４０Ａ，１００Ａは、ワイヤボンディングのアッセンブリに適した構造であり、接続部４０Ｂ，１００Ｂ，１００ＣはＴＡＢ方式やＣＯＧ方式のアッセンブリに適した構造である。そのため、ＬＳＩ８０をワイヤボンディングで外部回路に接続する要求がある場合には、各パッド部９０，１００の接続部４０Ａ，１００Ａと外部回路との間をワイヤ８５でそれぞれ接続する。さらに、必要に応じて、チップコンデンサ等のデバイス８６，８７を、選択された接続部４０Ｂ，１００Ｂ，１００Ｃに直接接続して搭載する。ここで、パッド部１００では、接続部１００Ｂ，１００Ｃを有しているので、２つのデバイス８６，８７の接続が可能になっている。
【００３４】
ＬＳＩ８０をＴＡＢ方式やＣＯＧ方式で外部回路に接続する要求がある場合には、各パッド９０，１００の接続部４０Ｂ，１００Ｂ，１００Ｃにおける接続層４５ｂ，１０５ｂ，１０８ｂを、テープや硝子に形成された外部回路に直接接続する。さらに追加して、ワイヤボンディングで他の外部回路に接続する要求がある場合には、図７（ｂ）のように、接続部４０Ａと外部回路との間をワイヤ８５でそれぞれ接続する。
【００３５】
以上のように、この第３の実施形態のアッセンブリ方法では、各パッド部９０，１００に２つの接続部４０Ａ，４０Ｂ或いは３つの接続部１００Ａ，１００Ｂ，１００Ｃをそれぞれ形成したので、第１の実施形態と同様に、ワイヤボンディングによる外部回路との接続が可能になると共に、ＴＡＢ方式やＣＯＧ方式によって外部回路との接続が可能なり、複数の実装形態がとれる。さらに、その両方の実施形態を同時に施すことが可能になり、ＬＳＩ８０の開発効率が向上すると共に、量産効率が向上する。その上、例えばワイヤボンディングによる実装を行った状態で、デバイス８６，８７の搭載が可能になるとと共に、１つのパッド部１００に２個のデバイス８６，８７が接続できるので、第２の実施形態よりも、適用可能な実装形態の種類が増加し、該ＬＳＩ８０を組み込むシステムが小型化できる。
【００３６】
なお、本発明は、上記実施形態の製造方法に限定されず種々の変形が可能である。
【００３７】
例えば、パッド部１００では、ＴＡＢ方式やＣＯＧ方式に適用可能な接続部１００、１００Ｂを形成しているが、その数は２個に限定されず、３個以上にしてもよい。また、パッド部１００にワイヤボンディングで接続可能な接続部１００Ａを複数形成してもよい。このようにすると、周辺回路での配線の引き回しが減少し、システムがさらに小型化する。
【００３８】
【発明の効果】
以上詳細に説明したように、本発明のＬＳＩのアッセンブリ方法によれば、第 1 の開口部を用いたワイヤ接続による実装形態および第 2 の開口部を用いたバンプ接続による実装形態のうち、要求に応じて 2 つの実装形態のいずれか一方を選択してＬＳＩと実装基材とのアッセンブリを行うようにしているので、ＬＳＩの構成を変えることなく、複数の実装形態を実現することが可能となる。これにより、ＬＳＩの開発効率を向上させると共に、量産効率を向上させることが可能となる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態を示すＬＳＩの平面図である。
【図２】従来のＬＳＩ（その１）を示す平面図である。
【図３】従来のＬＳＩ（その２）を示す平面図である。
【図４】図１中のパッド部４０を示す断面図である。
【図５】図１の接続例を示す平面図である。
【図６】本発明の第２の実施形態を示すＬＳＩの平面図である。
【図７】図６の接続例を示す平面図である。
【図８】本発明の第３の実施形態を示すＬＳＩの平面図である。
【図９】図８中のパッド部１００を示す断面図である
【符号の説明】
３０，６０，８０ ＬＳＩ
３１，６１，８１ 保護膜
３２，６２，８２ パッド
３５，６５，８５ ワイヤ
４０，７０，９０，１００ パッド部
４０Ａ，１００Ａ 第１の接続部
４０Ｂ，１００Ｂ，１００Ｃ 第２の接続部
４１，４３，１０１，１０３，１０６ 窓（開口部）
４５，１０５，１０８ バンプ
５０ テープ、硝子
６６，６７，８６，８７ デバイス（外部回路）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for assembling a semiconductor device (hereinafter referred to as an LSI) including an integrated circuit and a pad portion connected to an external circuit and inputting / outputting a signal to / from the integrated circuit.
[0002]
[Prior art]
FIGS. 2A to 2C are plan views showing a conventional LSI (part 1), FIG. 2A is a layout diagram of a pad portion of the LSI, and FIG. It is an enlarged view of A part of a), The figure (c) is a figure which shows the connection state of the figure (a).
[0003]
In this LSI 10 assembly method , an integrated circuit (not shown) is formed on a substrate, and a plurality of wiring patterns for inputting / outputting signals to / from the integrated circuit are formed. A plurality of pads 11 serving as terminals are formed on the plurality of wiring patterns. The surface of the LSI 10 is covered with a protective film 12, but the protective film 12 at the plurality of pads 11 is removed to form a window 13. A plurality of pad portions 14 are formed by the window 13 and the pad 11 exposed from the window 13.
[0004]
These pad portions 14 are wire bonding pad portions, and the pads 11 exposed from the windows 13 of the pad portions 14 and external circuits are connected by wires 15 as shown in FIG. As a result, the external circuit and the LSI 10 are assembled.
[0005]
FIGS. 3A to 3C are plan views showing a conventional LSI (part 2), FIG. 3A is a layout view of the pad portion of the LSI, and FIG. It is an enlarged view of B part of a), The figure (c) is a figure which shows the connection state of the figure (a).
[0006]
In the LSI 20, for example, an integrated circuit similar to the LSI 10 described above is formed on a substrate, and a plurality of wiring patterns are formed. A plurality of pads 11 similar to the LSI 10 serving as a terminal are formed on the plurality of wiring patterns. Although the surface of the LSI 20 is covered with a protective film 21, the protective film 21 at each pad 11 is removed to form a window 22 as shown in FIG. 3B, and the pad 11 exposed from the window 22 is formed on the pad 11. Bumps 23 made of solder or the like are deposited and formed so as to further protrude from the surface of the protective film 21. A pad portion 25 is formed by the window 22 and the bump 23.
[0007]
By directly connecting the external circuit 26 using the bumps 23 of these pad portions 25, as shown in FIG. 3C, a TAB (Tape Automated Bonding) or COG (Chip On Glass) type assembly , that is, Then, assembly with a mounting base material such as an external tape base material or an external glass substrate is performed.
[0008]
[Problems to be solved by the invention]
However, the conventional LSI assembly method has the following problems.
[0009]
Since the LSIs 10 and 20 have different connection methods to external circuits depending on the structures of the plurality of pad portions 14 and 25, even if the LSIs 10 and 20 have the same integrated circuit and wiring patterns and perform the same operation, Only one type of assembly determined by the structure of the pad portions 14 and 25 could be implemented. Therefore, the LSI 10 that is connected to the external circuit by wire bonding and the LSI 20 that is connected to the external circuit by the TAB method are separately manufactured, and there is a problem that the development efficiency and the mass production effect cannot be improved.
[0010]
[Means for Solving the Problems]
In order to solve the above-described problems, in the LSI assembly method of the present invention , the semiconductor chip and the first connection portion and the second connection portion formed in the common wiring pattern formed on the surface of the semiconductor chip. And, when connecting the first opening, the second connecting portion, and the mounting substrate using bumps, which are used when connecting the first connecting portion and the mounting substrate using wires. An LSI having a second opening portion used for the semiconductor device and having the wiring pattern and a protective film covering the surface of the semiconductor chip on which the wiring pattern is formed is prepared.
[0011]
Of the mounting form by wire connection using the first opening and the mounting form by bump connection using the second opening, either one of the two mounting forms is selected according to the request, and An assembly of the semiconductor device and the mounting substrate is performed. Thereby, a plurality of mounting forms can be selectively taken with the LSI having the same structure.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIGS. 1A and 1B are plan views of an LSI showing a first embodiment of the present invention. FIG. 1A is a layout diagram showing the arrangement of pad portions. FIG. 4 is an enlarged view of a portion C in FIG.
[0014]
This LSI 30 assembly method includes an integrated circuit (not shown) that is a semiconductor chip formed on a rectangular substrate, and a plurality of wiring patterns formed of aluminum (not shown) connected to the integrated circuit. Is covered with a protective film 31. A plurality of pads 32 serving as terminals are formed in the plurality of wiring patterns, and pad portions 40 for inputting / outputting signals to / from an external circuit are formed at the positions of the pads 32, respectively.
[0015]
FIG. 4 is a cross-sectional view showing the structure of the pad portion 40 in FIG.
[0016]
The plurality of pad portions 40 are respectively formed with a first connection portion 40A and a second connection portion 40B provided for the common pad 32. A first window 41 that is the second opening from which the protective film 31 has been removed and a portion 42 of the pad 32 that is exposed from the window 41 are formed in the connection portion 40A. The connection portion 40B includes a second window 43 that is a first opening from which the protective film 31 has been removed, a portion 44 exposed from the window 43 in the pad 32, and a conductive member deposited on the portion 44. The bump 45 is formed. The pump 45 is formed by, for example, laminating a base layer 45 a such as copper and a connection layer 45 b such as gold or solder on the pad 32 and projecting from the protective film 31.
[0017]
In the assembly method of the LSI 30, the plurality of pad portions 40 are laid out so that the connection portions 40A of the pad portions 40 face the center side of the substrate and the connection portions 40B face the outside of the substrate.
[0018]
5A and 5B are plan views showing the connection example of FIG.
[0019]
The connection portion 40A in the pad portion 40 of the LSI 30 has a structure suitable for wire bonding assembly, and the connection portion 40B has a structure suitable for TAB or COG assembly. Therefore, when there is a request to connect the LSI 30 to an external circuit by wire bonding, the connection portion 40A of each pad portion 40 and the external circuit are connected by wires 35 as shown in FIG. When there is a request to connect the LSI 30 to the external circuit by the TAB method or the COG method, the connection layer 45b in the connection unit 40B is directly connected to the external circuit formed on the tape or the glass 50.
[0020]
As described above, in the assembly method of the first embodiment, the two connection portions 40A and 40B for connecting the external circuit to the common pad 32 are formed in each pad portion 40, and the connection is made. Since the portion 40A has a structure that can be connected to an external circuit by wire bonding, and the connection portion 40B has a structure that can be connected to an external circuit by a TAB method or a COG method, the LSI 30 can take a plurality of mounting forms. Therefore, even if the pad portion 40 of the LSI 30 is not changed, a plurality of assemblies can be made by selecting a mounting form according to the requirements after the completion of the LSI 30, so that the development efficiency of the LSI 30 is improved and mass production is performed. Efficiency is improved.
[0021]
(Second Embodiment)
FIG. 6 is a plan view of an LSI showing a second embodiment of the present invention.
[0022]
This LSI 60 assembly method includes an integrated circuit (not shown) that is a semiconductor chip formed on a rectangular substrate, and a plurality of wiring patterns formed of aluminum (not shown) connected to the integrated circuit. The surface is covered with a protective film 61. A plurality of pads 62 serving as terminals are formed in the plurality of wiring patterns, and pad portions 70 for inputting / outputting signals to / from an external circuit are formed at the positions of the pads 62, respectively.
[0023]
Each pad portion 70 is formed with a first connection portion 40A and a second connection portion 40B having the same structure as in FIG. However, in the LSI 60, the plurality of pad portions 70 are laid out so that the connection portions 40A of the pad portions 70 face the outside of the substrate and the connection portions 40B face the center side of the substrate.
[0024]
7A and 7B are plan views showing the connection example of FIG.
[0025]
The connection portion 40A in the pad portion 70 of the LSI 60 has a structure suitable for wire bonding assembly, and the connection portion 40B has a structure suitable for TAB or COG assembly. Therefore, when there is a request to connect the LSI 60 to an external circuit by wire bonding, the connection part 40A outside each pad part 70 and the external circuit are respectively connected by wires 65 as shown in FIG. To do. Furthermore, as necessary, devices 66 and 67 such as chip capacitors are mounted by connecting to the connection portion 40B on the center side.
[0026]
When there is a request to connect the LSI 60 to an external circuit by the TAB method or the COG method, the connection layer 45b in the central connection portion 40B is directly connected to the external circuit formed on the tape or the glass 50. In addition, when there is a request to connect to another external circuit by wire bonding, the outer connection portion 40A and the external circuit are respectively connected by wires 65 as shown in FIG. 7B.
[0027]
As described above, in the assembly method according to the second embodiment, the two connection portions 40A and 40B are formed in each pad portion 70, the connection portion 40A faces the outside of the substrate, and the connection portion 40B is located on the center side. As in the manufacturing method of the first embodiment, it is possible to connect to an external circuit by wire bonding and to connect to an external circuit by a TAB method or a COG method. Can be implemented. Furthermore, both of the mounting forms can be applied simultaneously, so that the development efficiency of the LSI 60 is improved and the mass production efficiency is improved. In addition, it is possible to mount devices 66 and 67, which have been conventionally provided in the peripheral circuit of the LSI 60, on the LSI 60 in a state where mounting is performed by wire bonding, for example, and the system in which the LSI 60 is incorporated can be downsized. .
[0028]
(Third embodiment)
FIG. 8 is a plan view of an LSI showing a third embodiment of the present invention.
[0029]
This LSI 80 assembly method includes an integrated circuit (not shown) which is a semiconductor chip formed on a rectangular substrate, and a plurality of wiring patterns formed of aluminum or the like (not shown) connected to the integrated circuit. The surface is covered with a protective film 81. A plurality of pads 82 serving as terminals are formed in the plurality of wiring patterns, and two types of pad portions 90 and 100 for inputting / outputting signals to / from an external circuit are appropriately formed at the positions of the pads 82.
[0030]
FIG. 9 is a cross-sectional view showing the structure of the pad portion 100 in FIG.
[0031]
The pad portion 90 is formed with a first connection portion 40A and a second connection portion 40B having the same structure as in FIG. On the other hand, as shown in FIG. 9, the pad portion 100 is formed with a first connection portion 100A provided for the common pad 82 and two second connection portions 100B and 100C.
[0032]
A first window 101 which is a second opening from which the protective film 81 has been removed and a portion 102 of the pad 82 exposed from the window 101 are formed in the connection portion 100A. The connection portion 100B includes a second window 103 which is a first opening from which the protective film 81 has been removed, a portion 104 exposed from the window 103 in the pad 82, and a conductive member deposited on the portion 104. The bump 105 is formed. The pump 105 is formed, for example, by laminating a base layer 105 a such as copper and a connection layer 105 b such as gold or solder on the pad 82. The connection portion 100C includes a second window 106, which is a first opening from which the protective film 81 has been removed, a portion 107 exposed from the window 106 in the pad 82, and a conductive member deposited on the portion 107. Bumps 108 are formed. The bump 108 is formed by, for example, laminating a base layer 108 a such as copper and a connection layer 108 b such as gold or solder on the pad 82 and projecting from the protective film 81.
[0033]
As described above, the connection portions 40A and 100A in the pad portions 90 and 100 of the LSI 80 are structures suitable for wire bonding assemblies, and the connection portions 40B, 100B and 100C are structures suitable for TAB and COG assembly. It is. Therefore, when there is a request to connect the LSI 80 to an external circuit by wire bonding, the connection portions 40A and 100A of the pad portions 90 and 100 and the external circuit are connected by wires 85, respectively. Furthermore, devices 86 and 87 such as chip capacitors are directly connected to and mounted on the selected connection portions 40B, 100B, and 100C as necessary. Here, since the pad portion 100 includes the connection portions 100B and 100C, the two devices 86 and 87 can be connected.
[0034]
When there is a request to connect the LSI 80 to an external circuit by the TAB method or COG method, the connection layers 45b, 105b, 108b in the connection portions 40B, 100B, 100C of the pads 90, 100 are formed on tape or glass. Connect directly to external circuit. In addition, when there is a request to connect to another external circuit by wire bonding, the connection portion 40A and the external circuit are respectively connected by wires 85 as shown in FIG. 7B.
[0035]
As described above, in the assembly method of the third embodiment, the two connection portions 40A and 40B or the three connection portions 100A, 100B, and 100C are formed in the pad portions 90 and 100, respectively. Similarly to the configuration, connection to an external circuit by wire bonding is possible, and connection to an external circuit is possible by the TAB method or the COG method, so that a plurality of mounting forms can be taken. Furthermore, both of the embodiments can be applied at the same time, improving the development efficiency of the LSI 80 and improving the mass production efficiency. In addition, since the devices 86 and 87 can be mounted in a state where mounting is performed by wire bonding, for example, two devices 86 and 87 can be connected to one pad portion 100, so that the second embodiment can be used. However, the number of applicable mounting forms increases, and the system incorporating the LSI 80 can be downsized.
[0036]
In addition, this invention is not limited to the manufacturing method of the said embodiment, A various deformation | transformation is possible.
[0037]
For example, in the pad portion 100, the connection portions 100 and 100B applicable to the TAB method and the COG method are formed, but the number is not limited to two and may be three or more. A plurality of connection portions 100A that can be connected to the pad portion 100 by wire bonding may be formed. This reduces wiring routing in the peripheral circuit and further reduces the system size.
[0038]
【The invention's effect】
As described above in detail, according to the LSI assembly method of the present invention , a requirement among a mounting form by wire connection using the first opening and a mounting form by bump connection using the second opening is required. since to carry out the assembly of the LSI and the mounting base by selecting one of the two implementations in response to, without changing the configuration of the LSI, it is possible to realize a more implementations Become. As a result, LSI development efficiency can be improved and mass production efficiency can be improved.
[Brief description of the drawings]
FIG. 1 is a plan view of an LSI showing a first embodiment of the present invention.
FIG. 2 is a plan view showing a conventional LSI (part 1);
FIG. 3 is a plan view showing a conventional LSI (part 2);
4 is a cross-sectional view showing a pad portion 40 in FIG. 1. FIG.
FIG. 5 is a plan view showing a connection example of FIG. 1;
FIG. 6 is a plan view of an LSI showing a second embodiment of the present invention.
7 is a plan view showing a connection example of FIG. 6. FIG.
FIG. 8 is a plan view of an LSI showing a third embodiment of the present invention.
FIG. 9 is a cross-sectional view showing the pad portion 100 in FIG. 8;
30, 60, 80 LSI
31, 61, 81 Protective film 32, 62, 82 Pad 35, 65, 85 Wire 40, 70, 90, 100 Pad part 40A, 100A First connection part 40B, 100B, 100C Second connection part 41, 43, 101, 103, 106 Window (opening)
45, 105, 108 Bump 50 Tape, Glass 66, 67, 86, 87 Device (external circuit)

Claims (6)

半導体チップと、前記半導体チップの表面上に形成された共通の配線パタンに形成された第１の接続部および第２の接続部と、前記第１の接続部と実装基材とをワイヤを用いて接続する際に用いられる第１の開口部と前記第２の接続部と前記実装基材とをバンプを用いて接続する際に用いられる第２の開口部とを備え前記配線パタンおよび前記配線パタンが形成された前記半導体チップの前記表面を覆う保護膜と、を有する半導体装置を準備し、
前記第１の開口部を用いたワイヤ接続による実装形態および前記第２の開口部を用いたバンプ接続による実装形態のうち、要求に応じて前記２つの実装形態のいずれか一方を選択して前記半導体装置と前記実装基材とのアッセンブリを行うことを特徴とする半導体装置のアッセンブリ方法。 Wires are used for the semiconductor chip, the first connection portion and the second connection portion formed in the common wiring pattern formed on the surface of the semiconductor chip, and the first connection portion and the mounting base material. The wiring pattern and the wiring comprising a first opening used when connecting the second connecting part and a second opening used when connecting the mounting substrate to each other using bumps. Preparing a semiconductor device having a protective film covering the surface of the semiconductor chip on which a pattern is formed ;
Of the mounting form by wire connection using the first opening and the mounting form by bump connection using the second opening, either one of the two mounting forms is selected according to the request, and An assembly method of a semiconductor device, comprising assembling a semiconductor device and the mounting substrate. 請求項１記載の半導体装置のアッセンブリ方法において、前記第２の開口部は、前記第１の開口部よりも前記半導体チップの外周辺寄りに設けられていることを特徴とする半導体装置のアッセンブリ方法。2. The method of assembling a semiconductor device according to claim 1, wherein the second opening is provided closer to the outer periphery of the semiconductor chip than the first opening. . 請求項１記載の半導体装置のアッセンブリ方法において、前記第１の開口部は、前記第２の開口部よりも前記半導体チップの外周辺寄りに設けられていることを特徴とする半導体装置のアッセンブリ方法。2. The semiconductor device assembly method according to claim 1, wherein the first opening is provided closer to the outer periphery of the semiconductor chip than the second opening. . 請求項１〜３のいずれか１つに記載の半導体装置のアッセンブリ方法において、前記バンプは下地層と接続層とから構成された積層構造を備えることを特徴とする半導体装置のアッセンブリ方法。4. The method for assembling a semiconductor device according to claim 1, wherein the bump has a laminated structure including a base layer and a connection layer. 請求項１〜４のいずれか１つに記載の半導体装置のアッセンブリ方法において、In the assembly method of the semiconductor device as described in any one of Claims 1-4,
前記半導体チップは４辺を備える矩形であり、前記配線パタンは複数形成され、  The semiconductor chip is a rectangle having four sides, and a plurality of the wiring patterns are formed,
前記複数の配線パタンの前記第１の接続部はそれぞれ、前記半導体チップの前記各辺に沿って配置されていることを特徴とする半導体装置のアッセンブリ方法。  The semiconductor device assembly method, wherein the first connection portions of the plurality of wiring patterns are arranged along the sides of the semiconductor chip. 請求項１〜５のいずれか１つに記載の半導体装置のアッセンブリ方法において、前記配線パタンはアルミニウムで構成されていることを特徴とする半導体装置のアッセンブリ方法。6. The method of assembling a semiconductor device according to claim 1, wherein the wiring pattern is made of aluminum.
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