JP6473790B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, for example, a semiconductor device having a pad and a technique effective when applied to the manufacturing technique.

  In JP-A-8-241909 (Patent Document 1), the surface protection film covering the side close to the end side of the semiconductor chip among the plurality of sides constituting the pad and the surface protection covering the other sides are disclosed. A technique for making it larger than the coating area of the membrane is described.

JP-A-8-241909

  For example, in the pad formed on the semiconductor chip, most of the surface of the pad is exposed from the opening provided in the surface protective film, while the end of the pad is covered with the surface protective film. . That is, a surface protective film is formed at the end portion of the pad so as to cover the step caused by the thickness of the pad.

  Here, for example, the surface protective film covering the step formed on the end portion of the pad is cracked due to stress applied during dicing to separate the semiconductor chip or stress applied from the sealing body that seals the semiconductor chip. May occur. Therefore, in the current semiconductor device, there is room for improvement from the viewpoint of suppressing the occurrence of cracks in the surface protective film covering the step formed at the end of the pad and improving the reliability of the semiconductor device.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device according to an embodiment includes a rectangular semiconductor chip, and the semiconductor chip has an inclined portion provided at a connection portion between each of a plurality of pads and a lead-out wiring portion.

  According to one embodiment, the reliability of a semiconductor device can be improved.

It is the top view which looked at the semiconductor device which consists of a QFP package from the upper surface. It is sectional drawing cut | disconnected by the AA line of FIG. It is a figure which shows the layout structure of a semiconductor chip. It is a figure which expands and shows the vicinity area | region of the pad currently formed in the semiconductor chip. It is a figure which shows the deformation | transformation of a pad typically. FIG. 3 is an enlarged plan view showing a part of the semiconductor chip in the first embodiment. It is a figure which expands and shows a part of pad which is not provided with the inclination part which is the characteristics of Embodiment 1. FIG. FIG. 3 is an enlarged view showing a part of a pad provided with an inclined portion, which is a feature of the first embodiment. It is sectional drawing cut | disconnected by the AA line of FIG. It is a figure which shows typically the structure between the some pads in related technology. 4 is a diagram schematically showing a configuration between a plurality of pads in the first embodiment. FIG. It is typical sectional drawing cut | disconnected by the BB line of FIG. FIG. 9 is an enlarged plan view showing a part of a semiconductor chip in a modification of the first embodiment. It is a top view which shows the layout structure of a semiconductor wafer. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 16A is a plan view illustrating the manufacturing process of the semiconductor device subsequent to FIG. 15, and FIG. 16B is a cross-sectional view taken along line AA in FIG. FIGS. 17A and 17B are diagrams illustrating a manufacturing process of the semiconductor device following FIG. 16, in which FIG. 17A is a plan view and FIG. 17B is a cross-sectional view taken along line AA in FIG. FIG. 18A is a plan view of the semiconductor device manufacturing process subsequent to FIG. 17, and FIG. 18B is a cross-sectional view taken along line AA in FIG. FIG. 19A is a plan view illustrating the manufacturing process of the semiconductor device following FIG. 18, and FIG. 19B is a cross-sectional view taken along the line AA in FIG. It is the figure after forming a pad, and is a cross-sectional schematic diagram which shows the boundary region vicinity of an edge (a boundary line in this step). 7 is a flowchart showing a flow of a process for manufacturing a semiconductor device made of, for example, a QFP package after an integrated circuit is formed on a semiconductor wafer. FIG. 6 is an enlarged plan view showing a part of a semiconductor chip in a second embodiment. FIG. 9 is an enlarged plan view showing a part of a semiconductor chip in a third embodiment. FIG. 10 is an enlarged plan view showing a part of a semiconductor chip in a first modification of the third embodiment. FIG. 25 is an enlarged plan view showing a part of a semiconductor chip in a second modification of the third embodiment. FIG. 6 is an enlarged plan view showing a part of a semiconductor chip in a fourth embodiment. FIG. 10 is an enlarged plan view showing a part of a semiconductor chip in a modification of the fourth embodiment. FIG. 10 is a plan view showing a schematic configuration of a pad in a fifth embodiment. FIG. 25 is a plan view showing a schematic configuration of a pad in a modification of the fifth embodiment. FIG. 10 is an enlarged plan view showing a part of a semiconductor chip in a sixth embodiment. FIG. 38 is an enlarged plan view showing a part of the pad in the seventh embodiment. FIG. 25 is a cross-sectional view showing between pads in the seventh embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
<Configuration example of semiconductor device (QFP package)>
There are various types of semiconductor device package structures such as a BGA (Ball Grid Array) package and a QFP (Quad Flat Package) package. The technical idea in the first embodiment can be applied to these packages, and the configuration of a semiconductor device including a QFP package will be described below as an example.

  FIG. 1 is a plan view of a semiconductor device SA1 formed of a QFP package as viewed from above. As shown in FIG. 1, the semiconductor device SA1 has a rectangular shape, and the upper surface of the semiconductor device SA1 is covered with a resin (sealing body) MR. And the outer lead OL protrudes outward from the four sides that define the outer shape of the resin MR.

  Subsequently, the internal structure of the semiconductor device SA1 will be described. 2 is a cross-sectional view taken along line AA in FIG. As shown in FIG. 2, the back surface of the chip mounting portion TAB is covered with a resin MR. On the other hand, the semiconductor chip CHP is mounted on the upper surface of the chip mounting portion TAB, and the chip mounting portion TAB is separated from the inner lead IL1 (lead terminal). Pads PD are formed on the main surface of the semiconductor chip CHP. The pad PD formed on the semiconductor chip CHP is electrically connected to the inner lead IL1 with a wire W. The semiconductor chip CHP, the wire W, and the inner lead IL1 are covered with the resin MR, and the outer lead OL (lead terminal) integrated with the inner lead IL1 protrudes from the resin MR. The outer lead OL protruding from the resin MR is formed in a gull wing shape, and a plating film PF is formed on the surface thereof.

  The chip mounting portion TAB, the inner lead IL1, and the outer lead OL are made of, for example, a copper material or 42 alloy that is an alloy of iron and nickel, and the wire W is made of, for example, a gold wire. Is formed. The semiconductor chip CHP is made of, for example, silicon or a compound semiconductor (GaAs or the like), and a plurality of semiconductor elements such as MOSFETs are formed on the semiconductor chip CHP. A multilayer wiring is formed above the semiconductor element via an interlayer insulating film, and a pad PD connected to the multilayer wiring is formed on the uppermost layer of the multilayer wiring. Therefore, the semiconductor element formed on the semiconductor chip CHP is electrically connected to the pad PD via the multilayer wiring. In other words, the integrated circuit is formed by the semiconductor elements formed on the semiconductor chip CHP and the multilayer wiring, and the pads PD function as terminals that connect the integrated circuit and the outside of the semiconductor chip CHP. The pad PD is connected to the inner lead IL1 by a wire W, and is connected to an outer lead OL formed integrally with the inner lead IL1. Therefore, the integrated circuit formed in the semiconductor chip CHP can be electrically connected to the outside of the semiconductor device SA1 through the path of the pad PD → the wire W → the inner lead IL1 → the outer lead OL → the external connection device. I understand that I can do it. That is, it can be seen that the integrated circuit formed in the semiconductor chip CHP can be controlled by inputting an electric signal from the outer lead OL formed in the semiconductor device SA1. It can also be seen that the output signal from the integrated circuit can be taken out from the outer lead OL.

  Next, FIG. 3 is a diagram showing a layout configuration of the semiconductor chip CHP. In FIG. 3, the semiconductor chip CHP has, for example, a rectangular shape, and a plurality of pads PD are arranged along the edge ES of the semiconductor chip CHP. Specifically, as shown in FIG. 3, a seal ring SRG is formed inside the end side ES along the end side ES of the rectangular semiconductor chip CHP, and inside the seal ring SRG, A plurality of pads PD are arranged along the edge ES of the semiconductor chip CHP. In each of the plurality of pads PD, although not shown in FIG. 3, most of the surface of the pad PD is exposed from the opening provided in the surface protective film, while the end of the pad PD is Covered with a surface protective film.

  Here, for example, the surface protective film covering the edge of the pad PD is cracked by stress applied during dicing for separating the semiconductor chip CHP or stress applied from a resin (sealing body) that seals the semiconductor chip CHP. May occur. Therefore, in the current resin-encapsulated semiconductor device, there is room for improvement from the viewpoint of improving the reliability of the semiconductor device by suppressing the occurrence of cracks in the surface protective film covering the step formed at the end of the pad PD. Exists.

<Room for improvement>
FIG. 4 is an enlarged view showing a region near the pad PD formed on the semiconductor chip. As shown in FIG. 4, a seal ring SRG is formed inside the edge ES of the semiconductor chip, and a pad PD is formed inside the seal ring SRG. The pad PD has a rectangular shape, and a lead-out wiring portion DWU is formed integrally with the pad PD. The lead wiring part DWU has a function of connecting the pad PD and a wiring (not shown) formed below the pad PD. A surface protective film PAS is formed so as to cover the pad PD, and an opening OP exposing a part of the surface region of the pad PD is formed in the surface protective film PAS. That is, most of the surface region of the pad PD is exposed from the opening OP provided in the surface protective film PAS, while the end region including the end portion of the pad PD is covered with the surface protective film PAS. Yes.

  In the present specification, an end region of the pad PD covered with the surface protective film PAS is defined as a covering region. For example, in FIG. 4, dots are attached to the covering region. Further, in FIG. 4, dots are also attached to a part of the surface protection film PAS that covers the outside of the step due to the end of the pad PD. That is, the surface protective film PAS is formed over the base on which the pad PD is formed. For example, in FIG. 4, in the surface protective film PAS, in particular, a covering region that covers an end portion of the pad PD; Dots are attached to the portion of the surface protection film PAS formed near the outside of the step due to the end of the pad PD.

  Here, for example, a temperature cycle test or the like causes expansion or contraction of the resin that seals the semiconductor chip. For example, as shown in FIG. 5, stress resulting from the expansion or contraction of the resin is applied to the pad PD. Can be considered. That is, as indicated by the arrows in FIG. 5, it is conceivable that stress from the resin that seals the semiconductor chip is applied from the side ES of the semiconductor chip. In this case, the stress from the resin that seals the semiconductor chip causes deformation of the covering region of the pad PD covered with the surface protective film PAS, resulting in an “aluminum slide” in which a part of the pad PD is displaced, or surface protection. The possibility that a crack CLK is generated in a part of the covering region of the pad PD covered with the film PAS is increased.

  As a result of the study by the present inventor, the present inventors have found that the following three factors can be considered as factors causing the occurrence of “aluminum slide” and crack CLK. That is, as shown in FIG. 5, the first factor is that the connection portion between the pad PD and the lead-out wiring portion DWU is at a right angle, so that a crack CLK is likely to occur in the surface protective film PAS at this connection portion. It is to become. The first factor is that, for example, when the connection portion between the pad PD and the lead-out wiring portion DWU is a right angle, the discontinuous region (seam region) of the surface protection film PAS covering this connection portion is concentrated in one place. It can be considered that stress concentrates on the discontinuous region having low stress resistance, and the crack CLK is generated in the surface protective film PAS at the connection site.

  The second factor is that cracks CLK are likely to occur in the surface protective film PAS due to the small width of the covering region of the pad PD covered with the surface protective film PAS. The second factor is that the stress resistance is lower when the width of the covering region of the pad PD covered with the surface protection film PAS is smaller than when the width of the covering region of the pad PD covered with the surface protection film PAS is large. It is considered to be.

  Subsequently, the third factor is the length of a line segment (a part of one side of the pad PD) in a direction orthogonal to the width of the covering region with respect to the width of the covering region of the pad PD covered with the surface protective film PAS. Due to the increase in the length, an “aluminum slide” in which a part of the pad PD shifts and a crack CLK is likely to occur in the surface protective film PAS. The third factor is that as the length of the line segment in the direction orthogonal to the width of the covering region becomes longer, the line segment becomes more easily bent due to stress from the direction orthogonal to the line segment, and the deformation of the line segment increases. Can be understood from.

  Therefore, in the present specification, a technical idea for suppressing the occurrence of “aluminum slide” and cracks CLK will be described by paying attention to the first to third factors described above. In particular, in the first embodiment, a contrivance against the first factor that the crack CLK is generated in the surface protective film PAS in the connection portion due to the connection portion between the pad PD and the lead-out wiring portion DWU being a right angle. The technical idea that has been applied will be described.

<Configuration of semiconductor chip>
FIG. 6 is an enlarged plan view showing a part of the semiconductor chip CHP in the first embodiment. In FIG. 6, the semiconductor chip CHP has, for example, a rectangular shape having a plurality of end sides ES, and corner portions CNR are formed by the end sides ES that intersect each other. A seal ring SRG that suppresses entry of foreign matter into the semiconductor chip CHP is formed inside the end side of the semiconductor chip CHP, and an end side ES of the semiconductor chip CHP is formed inside the seal ring SRG. A plurality of pads PD mainly composed of aluminum are arranged along the line. Each of the plurality of pads PD has, for example, a rectangular shape typified by a rectangular shape, and in each of the plurality of pads PD, most of the surface of the pad PD is provided in the surface protective film PAS. While exposed from the opening OP, the end of the pad PD is covered with a surface protective film. In addition, a lead wiring part DWU is provided integrally with each of the plurality of pads PD, and the lead wiring part DWU is covered with a surface protective film PAS. In FIG. 6, the seal ring SRG is formed inside the edge ES of the semiconductor chip CHP. However, a crack that may occur during dicing between the edge ES of the semiconductor chip CHP and the seal ring SRG. In some cases, a dummy pattern that suppresses the progression into the semiconductor chip CHP (in the chip region) is provided. At this time, a dummy pattern is not always necessary, but it is desirable to provide a dummy pattern in order to prevent cracks during dicing and to improve flatness in the CMP process performed when forming each wiring layer.

  In this specification, the “main component” refers to a material component that is contained most in the constituent materials constituting the member (layer or film). For example, the “pad PD mainly including aluminum” "" Means that the material of the pad PD contains the most aluminum (Al). The intent of using the term “main component” in this specification is to express that, for example, the pad PD is basically composed of aluminum, but does not exclude the case where impurities are included in addition. I use it.

  For example, when attention is paid to a pad PD generally used in a semiconductor device, the pad PD usually has a structure in which an aluminum film is sandwiched between barrier conductor films made of a titanium / titanium nitride film. That is, the pad PD includes a first barrier conductor film, an aluminum film formed on the first barrier conductor film, and a second barrier conductor film formed on the aluminum film. In this case, when the pad PD is composed of a laminated film composed of the first barrier conductor film, the aluminum film, and the second barrier conductor film, the aluminum film occupies most of the pad PD. Is a pad PD whose main component is "."

  The aluminum film referred to in this specification is not only a pure aluminum film, but also an aluminum alloy film (AlSi film) in which silicon is added to aluminum, or an aluminum alloy in which silicon and copper are added to aluminum. It is used in a wide concept including a film (AlSiCu film). Therefore, the pad PD including these aluminum alloy films is also included in the “pad PD mainly composed of aluminum”. That is, the “pad PD mainly composed of aluminum” used in this specification is also used for a pad PD including an aluminum film and a barrier conductor film, and the pad PD when the aluminum film itself is an aluminum alloy film. Will also be used.

<Features in Embodiment>
Next, feature points in the first embodiment will be described. In FIG. 6, the characteristic point of the first embodiment is that an inclined portion SLP as a reinforcing pattern is provided at a connection portion between the pad PD and the lead-out wiring portion DWU. Thereby, according to the first embodiment, it is possible to suppress the occurrence of the crack CLK in the covering region where a part of the pad PD is covered with the surface protective film PAS. The reason for this will be described below with reference to the drawings.

  FIG. 7 is an enlarged view showing a part of the pad PD that is not provided with the inclined portion SLP, which is a feature of the first embodiment. In FIG. 7, the pad PD and the lead wiring part DWU are integrally connected, and the inclined part SLP is not provided at the connection part between the pad PD and the lead wiring part DWU. That is, in FIG. 7, the connection angle of the connection part between the pad PD and the lead-out wiring part DWU is vertical (right angle). For this reason, as shown in FIG. 7, the surface protective film PAS covering the connection portion between the pad PD and the lead-out wiring portion DWU has a discontinuous region SM (seam region) at the time of film formation indicated by a dotted line concentrated in one place. Formed. As a result, in the pad PD shown in FIG. 7, stress is concentrated in the discontinuous region SM having low stress resistance, and the surface protective film PAS is likely to crack at the connection portion between the pad PD and the lead-out wiring portion DWU. Become.

  On the other hand, FIG. 8 is an enlarged view showing a part of the pad PD provided with the inclined portion SLP as a reinforcing pattern which is a feature of the first embodiment. In FIG. 8, the pad PD and the lead-out wiring part DWU are integrally connected, and an inclined part SLP is provided at a connection portion between the pad PD and the lead-out wiring part DWU. At this time, the shape of the inclined portion SLP is, for example, a right triangle shape. As a result, in FIG. 8, the connection angle of the connection portion between the pad PD and the lead-out wiring portion DWU becomes an obtuse angle that is an angle larger than 90 degrees.

In this case, in the pad PD shown in FIG. 7, since the inclined portion SLP does not exist, the connection angle of the connection portion between the pad PD and the lead-out wiring portion DWU is composed of one right angle. On the other hand, in the pad PD shown in FIG. 8, since the inclined portion SLP exists, the connection angle of the connection portion between the pad PD and the lead-out wiring portion DWU is composed of two obtuse angles. This means that in the pad PD shown in FIG. 7, one discontinuous region SM is formed corresponding to one right angle, whereas in the pad PD shown in FIG. 8, two obtuse angles are formed. This means that two discontinuous regions SM1 and SM2 are formed corresponding to the above. In other words, Oite the pad P D shown in FIG. 7, the surface protective film PAS covering the connecting portion of the pad PD and the lead-out wiring portion DWU, discrete regions at the time of film formation indicated by the dotted line SM (seam area) is 1 It is formed in a concentrated manner. On the other hand, in the pad PD shown in FIG. 8, the surface protective film PAS covering the connection portion between the pad PD and the lead wiring part DWU has two discontinuous regions SM1 and SM2 at the time of film formation indicated by dotted lines. It will be formed in a dispersed manner. As a result, in the pad PD according to the first embodiment having the inclined portion SLP, since there are two discontinuous regions SM1 and SM2 having low stress resistance, stress is applied to one discontinuous region having low stress resistance. Can be prevented from concentrating. In other words, in the pad PD according to the first embodiment having the inclined portion SLP, since there are two discontinuous regions SM1 and SM2 having low stress resistance, the stress is discontinuous between the two discontinuous regions SM1 and the discontinuous regions SM1. It is distributed to the area SM2. As a result, according to the first embodiment, since the stress is distributed to the two discontinuous regions SM1 and SM2, the stress applied to each of the discontinuous regions SM1 and SM2 is reduced. be able to. Therefore, according to the first embodiment, by providing the inclined portion SLP at the connection portion between the pad PD and the lead-out wiring portion DWU, the surface protective film PAS is cracked at the connection portion between the pad PD and the lead-out wiring portion DWU. Generation | occurrence | production can be suppressed effectively. From this, according to the semiconductor device in this Embodiment 1, the fall of the reliability by the crack generate | occur | produced in the surface protective film PAS can be suppressed. In other words, according to the first embodiment, the reliability of the semiconductor device can be improved.

  In particular, in the first embodiment, the width of the lead-out wiring unit DWU (the width in the X direction) is based on the length of the side to which the lead-out wiring unit DWU is connected among the plurality of sides constituting each of the plurality of pads PD. And the inclined portion SLP is provided on both sides of the lead-out wiring portion DWU. Therefore, according to the present embodiment, surface protection is provided on both sides of the connection portion between the pad PD and the lead-out wiring portion DWU by providing the inclined portions SLP on both sides of the connection portion between the pad PD and the lead-out wiring portion DWU. Generation of cracks in the film PAS can be effectively suppressed.

  Here, for example, the pad PD, the lead-out wiring portion DWU, and the inclined portion SLP are integrally formed from a film containing aluminum as a main component. As shown in FIG. 6, the lead-out wiring portion DWU is connected to a side farthest from the end side ES of the semiconductor chip CHP among a plurality of sides constituting each of the plurality of pads PD.

  This is because the side farthest from the edge ES of the semiconductor chip CHP among the plurality of sides constituting each of the plurality of pads PD is closest to the integrated circuit region formed inside the semiconductor chip CHP. This is because the connection distance between the integrated circuit formed in the integrated circuit region and the lead-out wiring part DWU can be shortened by providing the lead-out wiring part DWU on the side farthest from the edge ES of the CHP. . That is, by providing the lead wiring part DWU on the side farthest from the edge ES of the semiconductor chip CHP, it is possible to reduce the parasitic resistance of the wiring connecting the integrated circuit and the lead wiring part DWU. The performance of the apparatus can be improved.

  Further, in the configuration in which the lead wiring part DWU is provided on the side farthest from the end side ES of the semiconductor chip CHP shown in FIG. 6, a crack is generated in the surface protective film PAS at the connection portion between the pad PD and the lead wiring part DWU. It can be said that the configuration is desirable also from the viewpoint of suppressing this. For example, according to the study of the present inventor, for example, in FIG. 6, the stress applied to the covering region covering the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides constituting the pad PD is relatively This is because it tends to increase. That is, in FIG. 6, when the lead-out wiring portion DWU is provided on the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides constituting the pad PD, it is closest to the end side ES of the semiconductor chip CHP. It is considered that a connection portion between the pad PD and the lead-out wiring portion DWU that is likely to generate a crack is provided on the side, and a crack is likely to occur in the surface protection film PAS at the connection portion between the pad PD and the lead-out wiring portion DWU. Because it is.

  In the semiconductor device according to the first embodiment, even when the lead-out wiring portion DWU is provided on the side farthest from the end side ES, a contrivance is made to minimize the possibility of occurrence of cracks. That is, by providing the inclined portion SLP at the connection portion between the pad PD and the lead-out wiring portion DWU (first configuration), the stress is distributed to the two discontinuous regions SM1 and SM2 shown in FIG. As a result, the stress applied to each of the discontinuous region SM1 and the discontinuous region SM2 can be reduced (stress reduction effect by the first configuration). At the same time, in the semiconductor device according to the first embodiment, by providing the lead-out wiring part DWU on the side farthest from the end side ES of the semiconductor chip CHP (second configuration), the pad PD and the lead-out wiring part DWU are separated. The magnitude of the stress applied to the connection site can be reduced (stress reduction effect by the second configuration).

  As described above, in the semiconductor device according to the first embodiment, the surface protective film PAS is cracked at the connection portion between the pad PD and the lead-out wiring portion DWU due to the synergistic effect of the first configuration and the second configuration described above. This can be effectively suppressed.

  Furthermore, according to the present first embodiment, the connection distance between the integrated circuit formed in the inner region of the semiconductor chip CHP and the lead-out wiring portion DWU can be shortened by the above-described second configuration, whereby the integrated circuit is integrated. It is also possible to obtain an advantage that the parasitic resistance of the wiring connecting the circuit and the lead wiring portion DWU can be reduced.

  From the above, according to the first embodiment, it is possible to obtain a remarkable effect that the reliability can be improved while improving the performance of the semiconductor device.

  Next, FIG. 9 is a cross-sectional view taken along line AA of FIG. As shown in FIG. 9, a field effect transistor Q, which is an example of a semiconductor element, is formed on a semiconductor substrate 1S made of, for example, silicon. Above the field effect transistor Q, for example, from a fine copper wiring A fine layer FL is formed. A global layer GL made of copper wiring having a width larger than that of the copper wiring constituting the fine layer FL is formed above the fine layer FL. A plurality of pads PD are formed on the global layer GL. The pad PD and the global layer GL are connected to the lead-out wiring part DWU shown in FIG. As shown in FIG. 9, the pad PD is electrically connected to the field effect transistor Q formed on the semiconductor substrate 1S via the global layer GL and the fine layer FL.

  Subsequently, a surface protective film PAS is formed so as to cover the plurality of pads PD and fill the spaces between the plurality of pads PD. An opening OP is formed in the surface protection film PAS, and a part of the surface of the pad PD is exposed from the bottom of the opening OP. For example, a wire W made of a gold wire is connected to the surface of the pad PD exposed from the opening OP. On the surface protection film PAS including the surface of the pad PD to which the wire W is connected, for example, It is covered with resin MR.

  Here, one of the feature points in the first embodiment will be described with reference to FIG. 10 and FIG. FIG. 10 is a diagram schematically showing a configuration between a plurality of pads PD in the related art, and FIG. 11 is a diagram schematically showing a configuration between a plurality of pads PD in the first embodiment. First, as shown in FIG. 10, a surface protective film PAS is formed in a gap between the pads PD. The surface protective film PAS is formed by, for example, a silicon oxide film OXF1 formed by a plasma CVD method and a CVD. It is comprised from the silicon nitride film SNF formed by the method. At this time, the film thickness of the pad PD is 1000 to 2000 nm, for example, about 1600 nm. The film thickness of the silicon oxide film OXF1 is about 200 nm, and the film thickness of the silicon nitride film SNF is about 600 nm. Therefore, the thickness of the pad PD is larger than the sum of the thickness of the silicon oxide film OXF1 and the thickness of the silicon nitride film SNF (1600 nm> 200 nm + 600 nm = 800 nm). Therefore, as shown in FIG. 10, the gap between the pads PD is not completely filled with the surface protective film PAS made of the silicon oxide film OXF1 and the silicon nitride film SNF. As a result, for example, when a resin (not shown) covering the pad PD expands and contracts due to a temperature change in the temperature cycle test, the pad PD easily moves in the lateral direction (horizontal direction). This is because, in the pad PD shown in the related art shown in FIG. 10, an “aluminum slide” is likely to occur due to a temperature change, and the surface protective film that covers the end of the pad PD due to the “aluminum slide” It means that cracks are likely to occur in the surface protective film PAS due to a synergistic factor between the point that a large stress is easily applied to the PAS and the thin film thickness of the surface protective film PAS. That is, it can be said that the configurations of the pad PD and the surface protective film PAS shown in FIG. 10 have room for improvement from the viewpoint of suppressing the occurrence of “aluminum slide” and the occurrence of cracks.

  In the first embodiment, the thickness of the pad PD is considerably increased as described above. This is mainly formed in order to reduce the resistance when routing the wiring in the same layer as the pad PD, or to relieve the stress at the time of probe contact under the pad PD by the inspection by the probe. It is. However, as the volume of aluminum increases, the above-described “aluminum slide” is more likely to occur. Therefore, the countermeasure as in the first embodiment is necessary.

  On the other hand, in the first embodiment, as shown in FIG. 11, the surface protective film PAS is formed so as to completely fill the gap between the pads PD. Specifically, the surface protective film PAS is made of silicon oxide film OXF1 formed by plasma CVD method, silicon oxide film OXF2 formed by high density plasma CVD method (HDP: High Density Plasma), and TEOS as raw materials. The silicon oxide film OXF3 is formed by the plasma CVD method, and the silicon nitride film SNF is formed by the CVD method.

  At this time, the thickness of the pad PD is 1000 to 2000 nm, for example, about 1700 nm, and the thickness of the silicon oxide film OXF1 is about 200 nm. The thickness of the silicon oxide film OXF2 is about 900 nm, and the thickness of the silicon oxide film OXF3 is about 800 nm. Further, the film thickness of the silicon nitride film SNF is, for example, about 600 nm. Therefore, the thickness of the pad PD is smaller than the total thickness of the silicon oxide film OXF1, the silicon oxide film OXF2, the silicon oxide film OXF3, and the silicon nitride film SNF (1700 nm <200 nm + 900 nm + 800 nm + 600 nm = 2500 nm). Therefore, as shown in FIG. 11, the gap between the pads PD is completely filled with the surface protective film PAS made of the silicon oxide film OXF1, the silicon oxide film OXF2, the silicon oxide film OXF3, and the silicon nitride film SNF. Become. As a result, for example, even if a resin (not shown) that covers the pad PD expands and contracts due to a temperature change in the temperature cycle test, the pad PD is firmly fixed by the surface protective film PAS that fills the gap. The pad PD is difficult to move in the lateral direction (horizontal direction). This is because the pad PD shown in FIG. 11 according to the first embodiment is less likely to cause “aluminum slide” due to temperature change, thereby causing stress acting on the surface protective film PAS due to “aluminum slide”. Also means that it will be relaxed. Therefore, according to the first embodiment, the “aluminum slide” of the pad PD is generated due to the feature that the film thickness of the surface protection film PAS is thick enough to completely fill the gap between the pads PD. In addition to being difficult, cracks are less likely to occur in the surface protective film PAS. That is, the configuration of the pad PD and the surface protection film PAS in the first embodiment as shown in FIG. 11 is superior from the viewpoint of suppressing the occurrence of “aluminum slide” and the occurrence of cracks.

  As described above, one of the feature points of the first embodiment is that the surface protective film PAS is formed so as to completely fill the gap between the pads PD. According to the above, occurrence of “aluminum slide” and occurrence of cracks can be effectively suppressed, thereby improving the reliability of the semiconductor device.

  Next, FIG. 12 is a schematic cross-sectional view taken along line BB in FIG. As shown in FIG. 12, the seal ring region SRR is provided inside the end side ES of the semiconductor chip CHP, and the seal ring SRG is formed in the seal ring region SRR. Further, the inner region of the seal ring region SRR is an integrated circuit region ICR, and the lead wiring portion DWU formed integrally with the pad PD and the pad PD is formed in the integrated circuit region ICR. At this time, in the first embodiment, the dummy region is not provided outside the seal ring SRG. However, for example, a dummy pattern is provided outside the seal ring SRG and on the edge ES side of the semiconductor chip CHP. May be.

  The seal ring SRG disclosed in the present embodiment is formed by connecting multiple wiring layers and is connected to the semiconductor substrate 1S. Although not shown in detail, it is connected to a well formed in the semiconductor substrate 1S and is set to a fixed potential such as a ground potential. On the other hand, the dummy pattern can be formed of multiple wiring layers as in the case of the seal ring SRG. Each wiring layer may be connected or separated. Unlike the seal ring SRG, this dummy pattern is not connected to a fixed potential and is often in a floating state.

  Further, as shown in FIG. 12, a surface protective film PAS is formed so as to cover the pad PD1 and the lead wiring part DWU that are integrally formed. An opening OP is formed in the surface protective film PAS, and a part of the surface of the pad PD is exposed from the bottom of the opening OP. On the other hand, the entire lead wiring part DWU is formed of the surface protective film. Covered with PAS. The surface protective film PAS covers the seal ring region SRR formed outside the integrated circuit region ICR, and extends to the end side ES of the semiconductor chip CHP.

  In FIG. 12, the wiring structure and device structure formed in the lower layer of the pad PD and the extraction wiring portion DWU formed in the integrated circuit region ICR are basically the same as those in FIG. Yes. Also, in FIG. 12, illustration of a wire connected to the pad PD and a resin covering the surface protective film PAS is omitted.

<Modification>
The semiconductor device according to the first embodiment is configured as described above, and a modification of the first embodiment will be described below.

  FIG. 13 is an enlarged plan view showing a part of the semiconductor chip CHP in this modification. In FIG. 13, the characteristic point of this modification is that the lead-out wiring portion DWU is connected to the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides constituting each of the plurality of pads PD. In addition, an inclined portion SLP is provided at a connection portion between the lead-out wiring portion DWU and the pad PD. Thereby, according to this modification, it can suppress effectively that a crack generate | occur | produces in the surface protection film PAS in the connection site | part of the pad PD and the lead-out wiring part DWU similarly to Embodiment 1. FIG.

  For example, according to the study by the present inventor, the stress applied to the covering region covering the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides constituting the pad PD tends to be relatively large. That is, as shown in FIG. 13, when the lead-out wiring portion DWU is provided on the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides constituting the pad PD, the end side ES of the semiconductor chip CHP is provided. A connection site between the pad PD where the crack is likely to be generated and the lead-out wiring part DWU is provided on the side closest to. In this case, since it is considered that cracks are likely to occur in the surface protective film PAS at the connection portion between the pad PD and the lead-out wiring portion DWU, the semiconductor chip CHP among a plurality of sides constituting the pad PD is normal sense. It can be considered that the configuration in which the lead-out wiring portion DWU is provided on the side closest to the end side ES is difficult to be adopted from the viewpoint of suppressing the occurrence of cracks.

  However, in this modification, as a result of providing the inclined portion SLP at the connection portion between the lead wiring portion DWU and the pad PD, the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides constituting the pad PD. Even if the lead-out wiring part DWU is provided in the crack, cracks that are likely to occur at the connection portion between the pad PD and the lead-out wiring part DWU can be suppressed. In other words, in this modification, the configuration in which the inclined portion SLP is provided at the connection portion between the lead wiring portion DWU and the pad PD can suppress the occurrence of cracks at the connection portion between the pad PD and the lead wiring portion DWU. A configuration in which the lead wiring part DWU is provided on the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides to be configured is also permitted. That is, in this modification, from the viewpoint of preventing cracks, even if the lead wiring portion DWU is not originally employed, the inclined portion SLP is provided at the connection portion between the lead wiring portion DWU and the pad PD. This is possible by adopting a specific idea.

  As a result, according to the present modification, it is possible to improve the degree of freedom for arranging the lead-out wiring part DWU while suppressing the occurrence of cracks at the connection part between the lead-out wiring part DWU and the pad PD. That is, according to the present modification, the degree of freedom of the layout position of the entire semiconductor chip CHP can be increased as a result of the improvement of the degree of freedom of the layout position of the lead wiring part DWU formed integrally with the pad PD. This means that according to the present modification, it is possible to design a novel layout arrangement that is not bound by the conventional constraints, thereby improving the degree of freedom in designing the semiconductor device.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings. FIG. 14 is a plan view showing a layout configuration of the semiconductor wafer WF. As shown in FIG. 14, the semiconductor wafer WF has a substantially disk shape and has a plurality of chip regions CR in the internal region. A semiconductor element typified by a field effect transistor and a multilayer wiring layer are formed in each of the plurality of chip regions CR, and the plurality of chip regions CR are partitioned by a scribe region SCR. In the first embodiment, as shown in FIG. 14, a semiconductor wafer (semiconductor substrate) WF having a rectangular chip region CR and a scribe region SCR that partitions the chip region CR is prepared. At this stage, a semiconductor element typified by a field effect transistor is formed in each of the plurality of chip regions CR of the semiconductor wafer WF, and a multilayer wiring made of copper wiring is formed above the semiconductor element by, for example, a damascene method. A layer is formed. In the following process, the process of forming a pad on the uppermost layer of the multilayer wiring layer in each of the plurality of chip regions CR will be described.

  First, as shown in FIG. 15, a barrier conductor film BCF1, an aluminum film AF formed on the barrier conductor film BCF1, and a barrier conductor film BCF2 formed on the aluminum film AF are formed on the interlayer insulating film IL. A laminated film is formed. The barrier conductor film BCF1 is formed from, for example, a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method. The aluminum film AF is formed of a film containing aluminum as a main component, and can be formed by using, for example, a sputtering method. Furthermore, the barrier conductor film BCF2 is formed of, for example, a titanium nitride film, and can be formed by using, for example, a sputtering method. Note that a stacked film of titanium and titanium nitride may be used. Here, for example, the thickness of the barrier conductor film BCF1 is about 110 nm (the thickness of the titanium film (50 nm) + the thickness of the titanium nitride film (60 nm)), and the thickness of the aluminum film AF is about 1500 nm. is there. The film thickness of the barrier conductor film BCF2 (the film thickness of the titanium nitride film) is about 75 nm.

  Subsequently, as shown in FIGS. 16A and 16B, by using a photolithography technique and an etching technique, a laminated film composed of the barrier conductor film BCF1, the aluminum film AF, and the barrier conductor film BCF2 is formed. Pattern. By patterning the laminated film, along the boundary line between the chip region and the scribe region, a rectangular pad PD, a lead wiring portion DWU provided in the pad PD, and the pad PD and lead wiring portion are provided in the chip region. The inclined portion SLP provided at the connection site with the DWU is integrally formed. At this time, since the pad PD, the lead wiring part DWU, and the inclined part SLP are formed from the same laminated film, the height of the pad PD, the height of the lead wiring part DWU, and the slope part SLP are Almost the same height.

  Next, as shown in FIGS. 17A and 17B, a silicon oxide film OXF1 is formed on the interlayer insulating film IL so as to cover the pad PD, the lead-out wiring portion DWU, and the inclined portion SLP. The silicon oxide film OXF1 can be formed by, for example, a plasma CVD method (Chemical Vapor Deposition), and the thickness of the silicon oxide film OXF1 is about 200 nm. Subsequently, a silicon oxide film OXF2 is formed over the silicon oxide film OXF1. The silicon oxide film OXF2 can be formed by, for example, a high-density plasma CVD method having characteristics in which film etching and film formation proceed simultaneously, and the film thickness of the silicon oxide film OXF2 is about 900 nm. Thereafter, a silicon oxide film OXF3 is formed over the silicon oxide film OXF2. The silicon oxide film OXF3 can be formed by, for example, a plasma CVD method using TEOS as a raw material, and the thickness of the silicon oxide film OXF3 is about 800 nm. Then, a silicon nitride film SNF is formed on the silicon oxide film OXF3. The silicon nitride film SNF can be formed by using, for example, a CVD method. In this way, the surface protective film PAS made of the silicon oxide film OXF1, the silicon oxide film OXF2, the silicon oxide film OXF3, and the silicon nitride film SNF is formed so as to cover the pad PD, the lead-out wiring portion DWU, and the inclined portion SLP. be able to.

  At this time, since the film thickness of the surface protection film PAS is larger than the film thickness of the pad PD in the first embodiment, the gap between the pads PD is formed between the silicon oxide film OXF1, the silicon oxide film OXF2, and the silicon oxide film. The film is completely filled with the surface protective film PAS made of the film OXF3 and the silicon nitride film SNF.

  Subsequently, as shown in FIGS. 18A and 18B, by using a photolithography technique and an etching technique, an opening OP that exposes a part of the surface of the pad PD is formed in the surface protective film PAS. Form. On the other hand, the opening that exposes the lead wiring part DWU and the slope part SLP is not formed, and the surface of the lead wiring part DWU and the surface of the slope part SLP are kept covered with the surface protective film PAS. Thereafter, as shown in FIGS. 19A and 19B, the surface of the pad PD exposed from the opening OP is etched to etch the barrier formed on the surface of the pad PD exposed from the opening OP. The conductor film (titanium nitride film) is removed. As a result, the aluminum film is exposed from the opening OP.

  As described above, the pad PD can be formed on the uppermost layer of the multilayer wiring layer. Specifically, FIG. 20 is a diagram after the pad PD is formed, and is a schematic cross-sectional view showing the vicinity of the boundary region of the edge ES (a boundary line at this stage). In FIG. 20, a seal ring region SRR and an integrated circuit region ICR are formed inside the scribe region SCR. A seal ring SRG is formed in the seal ring region SRR. The seal ring SRG is formed in the same process as the multilayer wiring (not shown in FIG. 20) formed in the integrated circuit region ICR. In the integrated circuit region ICR, the pad PD is formed in the uppermost layer.

  Next, the subsequent steps will be described with reference to a flowchart. FIG. 21 is a flowchart showing a flow of steps for manufacturing a semiconductor device made of, for example, a QFP package after an integrated circuit is formed on a semiconductor wafer.

  First, after an integrated circuit is formed in each of a plurality of chip regions of the semiconductor wafer, the semiconductor wafer is diced along the scribe region (S101 in FIG. 21). As a result, a semiconductor chip in which an integrated circuit is formed by dividing a plurality of chip regions into individual pieces can be obtained. Then, after mounting the semiconductor chip on the chip mounting portion formed on the lead frame (S102 in FIG. 21), the pad formed on the semiconductor chip and the inner lead are connected by a wire (S103 in FIG. 21). Thereafter, the chip mounting portion, the semiconductor chip, the wires, and the inner leads are sealed with resin (S104 in FIG. 21). Then, after cutting the dam formed on the lead frame (S105 in FIG. 21), a plating film is formed on the surface of the outer lead exposed from the resin (S106 in FIG. 21). Subsequently, after forming a mark on the surface of the resin (S107 in FIG. 21), an outer lead protruding from the resin is formed (S108 in FIG. 21). After manufacturing the semiconductor device in this way, an electrical characteristic inspection is performed (S109 in FIG. 21). Then, a temperature cycle test is performed on the semiconductor device (S110 in FIG. 21), and the semiconductor device determined to be non-defective is shipped as a product.

(Embodiment 2)
In the first embodiment, the first factor that the crack CLK is generated in the surface protective film PAS at the connection part due to the right angle of the connection part between the pad PD and the lead-out wiring part DWU has been devised. The technical idea was explained. In the second embodiment, in addition to the technical idea described in the first embodiment, the surface protection film is further caused by the small width of the covering region of the pad PD covered with the surface protection film PAS. A technical idea in which a second factor that the crack CLK is likely to occur in the PAS is devised will be described.

  FIG. 22 is an enlarged plan view showing a part of the semiconductor chip CHP in the second embodiment. In FIG. 22, the feature point of the second embodiment is that the center position of the opening OP is displaced in the inner direction (center direction) of the semiconductor chip CHP with respect to the center position of each of the plurality of pads PD. It is in.

  Thereby, as shown in FIG. 22, the width of the covering region CVR2 of the surface protection film PAS covering the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides constituting each of the plurality of pads PD is It becomes wider than the width of the covering region CVR1 of the surface protection film PAS that covers the side farthest from the end side ES of the semiconductor chip CHP. This is because among the plurality of sides constituting the pad PD, the side to which the stress due to the expansion and contraction of the resin (not shown) caused by the temperature change is most easily applied (the side closest to the end side ES of the semiconductor chip CHP). ) Can be relatively widened (the width in the Y direction). Then, since the relatively wide width (width in the Y direction) of the covering region CVR2 means that the crack resistance against stress is improved, according to the semiconductor device in the second embodiment, the semiconductor device The generation of cracks in the covering region CVR2 of the surface protective film PAS that covers the side closest to the end side ES of the chip CHP can be suppressed. That is, according to the second embodiment, by providing the inclined portion SLP at the connection portion between the lead-out wiring portion DWU and the pad PD, the occurrence of cracks at the connection portion can be suppressed, and the edge ES of the semiconductor chip CHP can be suppressed. It is possible to obtain an effect capable of suppressing the generation of cracks in the covering region CVR2 of the surface protective film PAS that covers the nearest side. That is, the technical idea in the second embodiment is a device for the first factor and the second factor described above, and as a result of effectively suppressing the synergistic factor between the first factor and the second factor, excellent crack resistance is achieved. A highly reliable semiconductor device having the above can be provided.

  Furthermore, as shown in FIG. 22, in the second embodiment, attention is paid to the pad PD1 closest to the corner CNR of the semiconductor chip CHP among the plurality of pads PD. Specifically, as shown in FIG. 22, the pad PD1 closest to the corner CNR of the semiconductor chip CHP covers the side closest to the corner of the semiconductor chip CHP among the plurality of sides constituting the pad PD1. The width of the coating region CVR3 of the surface protection film PAS is also made wider than the width of the coating region CVR1 of the surface protection film PAS that covers the side farthest from the end side ES of the semiconductor chip CHP.

  As a result, in the second embodiment, in the pad PD1 closest to the corner portion CNR of the semiconductor chip CHP, the stress (semiconductor chip) on which the stress due to the expansion and contraction of the resin (not shown) caused by the temperature change tends to increase The width (width in the Y direction) of the covering region CVR2 that covers the edge closest to the edge ES of the CHP can be made relatively large. In addition, in the second embodiment, the width of the covering region CVR3 covering the side closest to the corner CNR where stress tends to be large can be relatively widened. As a result, in the second embodiment, the crack resistance is particularly improved in the pad PD1 disposed at the position closest to the corner CNR of the semiconductor chip CHP.

  As a means for realizing a configuration in which the center position of the opening OP is shifted in the inner direction (center direction) of the semiconductor chip CHP with respect to the center position of each of the plurality of pads PD, the size (area) of the pad PD is used. The first means for reducing the size of the opening OP while maintaining the size, and the second means for increasing the size of the pad PD while maintaining the size (area) of the opening OP can be considered. For example, as an advantage of the first means, since the size of the pad PD is maintained, the technical idea of the second embodiment can be realized without increasing the interval (pitch) for arranging the plurality of pads PD. A point can be mentioned. In this case, for example, it is possible to obtain an advantage of realizing the technical idea in the second embodiment while suppressing an increase in the number of semiconductor chips.

  On the other hand, as the advantage of the second means, since the size of the opening OP is maintained, the present embodiment is achieved without impairing the connection reliability of the wire connected to the surface of the pad PD exposed from the opening OP. The point which can implement | achieve the technical idea in 2 can be mentioned. In this case, for example, it is possible to obtain an advantage that the technical idea of the second embodiment can be realized without affecting the reliability of the semiconductor device (particularly, the reliability of wire connection).

  The manufacturing method of the semiconductor device in the second embodiment is basically the same as the manufacturing method of the semiconductor device in the first embodiment. However, in the method of manufacturing the semiconductor device according to the second embodiment, the photolithography technique and the etching technique in the step of forming the opening OP that exposes a part of the surface of each of the plurality of pads PD in the surface protection film PAS. The patterning using is changed. Specifically, the patterning process of the opening OP is performed such that the center position of the opening OP is shifted inward (center direction) of the chip region with respect to the center position of each of the plurality of pads PD. . That is, in the patterning process of the opening OP, the width of the covering region CVR2 of the surface protection film PAS that covers the side closest to the boundary line among the plurality of sides constituting each of the plurality of pads PD is the farthest from the boundary line. This is performed so as to be wider than the width of the covering region CVR1 of the surface protective film PAS covering the other side.

  Furthermore, in the patterning process of the opening OP in the second embodiment, among the plurality of pads PD, the pad PD1 closest to the corner portion CNR of the chip region, the chip region of the plurality of sides constituting the pad PD1. The covering region CVR3 of the surface protection film PAS covering the side closest to the corner CNR is also made wider than the width of the covering region CVR1 of the surface protection film PAS covering the side farthest from the boundary line.

(Embodiment 3)
In the first embodiment and the second embodiment, the configuration example in which the plurality of pads PD are arranged in one row along the edge ES of the semiconductor chip CHP has been described. In the third embodiment, A configuration example in which a plurality of pads PD are arranged in a plurality of rows (for example, two rows) along the edge ES of the semiconductor chip CHP will be described.

  FIG. 23 is an enlarged plan view showing a part of the semiconductor chip CHP in the third embodiment. In FIG. 23, a plurality of pads are arranged in two rows along the edge ES of the semiconductor chip CHP. Specifically, the plurality of pads are on the side close to the end side ES of the semiconductor chip CHP, on the side far from the end side ES of the semiconductor chip CHP, and on the side far from the end side ES of the semiconductor chip CHP. A plurality of inner pads IPD disposed along the side ES are included. For example, FIG. 23 shows an example in which outer pads OPD and inner pads IPD arranged in two rows are arranged in a so-called staggered arrangement. Here, the outer pad OPD is arranged in the first row that is close to the end side ES, and the inner pad IPD is arranged in the second row that is far from the end side ES.

  As shown in FIG. 23, in the plurality of inner pads IPD, the lead-out wiring portion is connected to the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides constituting each of the plurality of inner pads IPD. A DWU is provided, and an inclined portion SLP (IN) is provided at a connection portion between each of the plurality of inner pads IPD and the lead-out wiring portion DWU.

  On the other hand, in the plurality of outer pads OPD, a lead-out wiring portion DWU is provided so as to be connected to a side farthest from the end side ES of the semiconductor chip CHP among a plurality of sides constituting each of the plurality of outer pads OPD. ing. An inclined portion SLP (OUT) is provided at a connection portion between each of the plurality of outer pads OPD and the lead-out wiring portion DWU.

  Here, for example, the shape and size of the inclined portion SLP (IN) provided integrally with the inner pad IPD are the same as the shape and size of the inclined portion SLP (OUT) provided integrally with the outer pad OPD. It is the same.

  As described above, in the third embodiment, in any of the outer pad OPD and the inner pad IPD arranged in the staggered arrangement, the inclined portion SLP (OUT) or the inclined portion SLP (IN) is connected to the connection portion with the lead-out wiring portion DWU. Is provided. As a result, also in the third embodiment, cracks occur in the covering region where a part of the outer pad OPD is covered with the surface protective film PAS and the covering region where a part of the inner pad IPD is covered with the surface protective film PAS. Can be suppressed. That is, the technical idea described in the first embodiment can be applied not only to a plurality of pads PD arranged in one row, but also in a plurality of rows represented by, for example, a staggered arrangement as in the third embodiment. The present invention can also be applied to a plurality of inner pads IPD and a plurality of outer pads OPD that are arranged in the above.

<Modification 1>
In the third embodiment, as shown in FIG. 23, the shape and size of the inclined portion SLP (IN) provided integrally with the inner pad IPD is the same as the inclined portion SLP provided integrally with the outer pad OPD. Although an example in which the shape and size of (OUT) are the same has been described, in the first modification, an example in which the size of the inclined portion SLP (IN) is different from the size of the inclined portion SLP (OUT) will be described.

  FIG. 24 is an enlarged plan view showing a part of the semiconductor chip CHP in the first modification. In FIG. 24, in the first modification, the size (area) of the inclined portion SLP (IN) provided integrally with the inner pad IPD is equal to the inclined portion SLP (OUT) provided integrally with the outer pad OPD. ) Is larger than the size (area). In other words, the size of the inclined portion SLP (OUT) provided integrally with the outer pad OPD is smaller than the size of the inclined portion SLP (IN) provided integrally with the inner pad IPD.

  The reason for this will be described below. According to the study by the present inventors, it has been found that the stress applied to the covering region covering the side closest to the end side ES of the semiconductor chip CHP tends to be relatively large among the plurality of sides constituting the pad. Yes. In consideration of this point, when focusing on the inner pad IPD shown in FIG. 24, in the inner pad IPD, the lead-out wiring portion is located on the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides constituting the inner pad IPD. A DWU is provided. Therefore, in the inner pad IPD, a connection portion between the inner pad IPD and the lead-out wiring part DWU exists on the side closest to the end side ES of the semiconductor chip CHP where stress is likely to increase. This means that in the inner pad IPD, there is a connection site between the inner pad IPD and the lead-out wiring part DWU at a location where the stress is relatively large, and the surface protection film PAS covering the connection site is present. Cracks are likely to occur in the coated region. Therefore, in the first modification, a large-sized inclined portion SLP (IN) is provided at this connection portion from the viewpoint of sufficiently suppressing the occurrence of cracks at the connection portion between the inner pad IPD and the lead-out wiring portion DWU. . That is, as the size of the inclined portion SLP (IN) increases, it is considered that the occurrence of cracks at the connection portion between the inner pad IPD and the lead-out wiring portion DWU can be suppressed, and thus the inner pad IPD and the lead-out wiring portion DWU. A large-sized inclined portion SLP (IN) is provided at the connection site. Thereby, even when a relatively large stress is applied to the connection portion between the inner pad IPD and the lead-out wiring portion DWU, the occurrence of cracks at this connection portion can be sufficiently suppressed.

  On the other hand, paying attention to the outer pad OPD shown in FIG. 24, in the outer pad OPD, the lead wiring portion DWU is provided on the side farthest from the end side ES of the semiconductor chip CHP among the plurality of sides constituting the outer pad OPD. It has been. Therefore, in the outer pad OPD, there is a connection site between the outer pad OPD and the lead-out wiring portion DWU on the side farthest from the end ES of the semiconductor chip CHP, where the stress is assumed not to be relatively large. Become. This means that in the outer pad OPD, there is a connection part between the outer pad OPD and the lead-out wiring part DWU at a place where the stress is relatively difficult to increase, and the surface protective film PAS covering this connection part is present. It can be considered that cracks hardly occur in the covered region. Therefore, in the first modification, the occurrence of cracks at the connection portion between the outer pad OPD and the lead-out wiring portion DWU is less likely to be a problem than the occurrence of cracks at the connection portion between the inner pad IPD and the lead-out wiring portion DWU. In consideration of the above, a small-size inclined portion SLP (OUT) is provided at a connection portion between the outer pad OPD and the lead-out wiring portion DWU. That is, even if the size of the inclined portion SLP (OUT) is small, it is considered that the occurrence of cracks at the connection portion between the outer pad OPD and the lead-out wiring portion DWU can be suppressed, so that the outer pad OPD and the lead-out wiring portion DWU A small-sized inclined portion SLP (OUT) is provided at the connection site. As a result, in the first modification, the size of the inclined portion SLP (IN) provided integrally with the inner pad IPD is larger than the size of the inclined portion SLP (OUT) provided integrally with the outer pad OPD. In this way, a configuration that increases the size is realized. Even in this configuration, it is possible to suppress the occurrence of cracks at the connection portion between the inner pad IPD and the lead-out wiring portion DWU, and to suppress the generation of cracks at the connection portion between the outer pad OPD and the lead-out wiring portion DWU. be able to.

<Modification 2>
In the second modification, an example will be described in which the inclined portion SLP (IN) is provided integrally with the inner pad IPD, but the inclined portion is not provided at the connection portion between the outer pad OPD and the lead-out wiring portion DWU.

  FIG. 25 is an enlarged plan view showing a part of the semiconductor chip CHP in the second modification. For example, as described in the first modification, in the outer pad OPD, the lead-out wiring portion DWU is provided on the side farthest from the end side ES of the semiconductor chip CHP among the plurality of sides constituting the outer pad OPD. It has been. In this case, in the outer pad OPD, since it is considered that the magnitude of stress applied to the connection portion between the outer pad OPD and the lead-out wiring portion DWU is relatively small, the covering region of the surface protection film PAS covering this connection portion It can be estimated that cracks are unlikely to occur. Therefore, in the second modification, the occurrence of cracks at the connection portion between the outer pad OPD and the lead-out wiring portion DWU is less likely to be a problem than the occurrence of cracks at the connection portion between the inner pad IPD and the lead-out wiring portion DWU. In consideration of this point, the connecting portion between the outer pad OPD and the lead-out wiring portion DWU is configured not to be provided with an inclined portion. Also in this modified example 2 configured as described above, the inner pad IPD is integrally provided with the inclined portion SLP (IN), and therefore, cracks at the connection portion between the inner pad IPD and the lead-out wiring portion DWU are eliminated. Generation | occurrence | production can fully be suppressed.

(Embodiment 4)
In the fourth embodiment, similarly to the third embodiment, the surface protection film PAS is further assumed on the assumption that a plurality of pads are arranged in a staggered arrangement along the edge ES of the semiconductor chip CHP. A technical idea that also incorporates a contrivance for the second factor that the surface protection film PAS is likely to crack due to the small width of the covering region of the pad covered with 1 will be described.

  FIG. 26 is an enlarged plan view showing a part of the semiconductor chip CHP in the fourth embodiment. In FIG. 26, in the fourth embodiment, assuming a staggered arrangement, the center positions of the openings OP coincide with the center positions of the plurality of inner pads IPD in the plurality of inner pads IPD constituting the staggered arrangement. ing. On the other hand, in the plurality of outer pads OPD configuring the staggered arrangement, the center position of the opening OP is shifted in the inner direction (center direction) of the semiconductor chip CHP with respect to the respective center positions of the plurality of outer pads OPD. ing.

  Accordingly, as shown in FIG. 26, the width of the covering region CVR2 of the surface protection film PAS that covers the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides constituting each of the plurality of outer pads OPD is as follows. The width of the coating region CVR1 of the surface protective film PAS covering the side farthest from the end side ES of the semiconductor chip CHP becomes larger. This is because among the plurality of sides constituting the outer pad OPD, the side to which the stress caused by the expansion and contraction of the resin (not shown) caused by the temperature change is most easily applied (closest to the end ES of the semiconductor chip CHP). This means that the width (width in the Y direction) of the covering region CVR2 covering the side) can be made relatively wide. Then, since the relatively wide width (width in the Y direction) of the covering region CVR2 means that the crack resistance against stress is improved, according to the semiconductor device of the fourth embodiment, the outer side In the pad OPD, it is possible to suppress the occurrence of cracks in the coating region CVR2 of the surface protection film PAS that covers the side closest to the end side ES of the semiconductor chip CHP. That is, according to the fourth embodiment, as in the third embodiment, the inclined portion SLP (OUT) is provided at the connection portion between the outer pad OPD and the lead wiring part DWU, and the inner pad IPD and the lead wiring are provided. By providing the inclined portion SLP (IN) at the connection site with the part DWU, the occurrence of cracks at the connection site can be suppressed. Furthermore, in the fourth embodiment, as shown in FIG. 26, the width (width in the Y direction) of the covering region CVR2 of the outer pad OPD can be relatively widened. As a result, the edge ES of the semiconductor chip CHP The occurrence of cracks in the covering region CVR2 of the surface protective film PAS covering the nearest side can also be suppressed.

  Furthermore, as shown in FIG. 26, the fourth embodiment focuses on the outer pad OPD1 that is the closest to the corner CNR of the semiconductor chip CHP among the plurality of outer pads OPD. Specifically, as shown in FIG. 26, in the outer pad OPD1 closest to the corner CNR of the semiconductor chip CHP, the side closest to the corner of the semiconductor chip CHP among the plurality of sides constituting the outer pad OPD1. The width of the covering region CVR3 of the surface protective film PAS covering the surface of the semiconductor chip CHP is also wider than the width of the covering region CVR1 of the surface protective film PAS covering the side farthest from the edge ES of the semiconductor chip CHP.

  As a result, in the fourth embodiment, in the outer pad OPD1 closest to the corner CNR of the semiconductor chip CHP, the side (semiconductor) where stress due to expansion and contraction of resin (not shown) caused by temperature change is likely to increase. The width (width in the Y direction) of the covering region CVR2 that covers the edge closest to the edge ES of the chip CHP can be relatively increased. In addition, in the fourth embodiment, the width of the covering region CVR3 covering the side closest to the corner portion CNR where stress tends to be large can be relatively widened. As a result, in the fourth embodiment, the crack resistance can be particularly improved in the outer pad OPD1 disposed at the position closest to the corner CNR of the semiconductor chip CHP.

<Modification>
Next, a modification of the fourth embodiment will be described. In the fourth embodiment, focusing on the outer pad OPD, the surface protective film PAS is likely to be cracked due to the small width of the covering region of the outer pad OPD covered with the surface protective film PAS. An example in which a device for the second factor was also incorporated was described. In the present modified example, an example in which a device for the second factor is also taken into account for the inner pad IPD will be described by paying attention to the inner pad IPD. That is, in the fourth embodiment, since the second factor described above is considered to be manifested in the outer pad OPD close to the edge ES of the semiconductor chip CHP, first, a device for the second factor with respect to the outer pad OPD. The example which took in was explained. Furthermore, in the present modification, the inner pad IPD is farther from the edge ES of the semiconductor chip CHP than the outer pad OPD, and thus it is considered that the above-described second factor is less affected than the outer pad OPD. Considering the possibility of some influence from the second factor. In other words, in the present modification, from the viewpoint of further improving the reliability of the semiconductor device, the device for the second factor is also adopted for the inner pad IPD.

  FIG. 27 is an enlarged plan view showing a part of the semiconductor chip CHP in the present modification. In FIG. 27, in the present modification, assuming the staggered arrangement, not only the plurality of outer pads OPD constituting the staggered arrangement but also the inner pad IPD, the center position of the opening OP is set to each of the plurality of inner pads IPD. There is a feature point in that it is shifted inward (center direction) of the semiconductor chip CHP with respect to the center position.

  Thereby, as shown in FIG. 27, the width of the covering region CVR2 of the surface protection film PAS covering the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides constituting each of the plurality of inner pads IPD is The width of the coating region CVR1 of the surface protective film PAS covering the side farthest from the end side ES of the semiconductor chip CHP becomes larger. This is because among the plurality of sides constituting the inner pad IPD, the side to which the stress caused by the expansion and contraction of the resin (not shown) caused by the temperature change is most easily applied (closest to the end ES of the semiconductor chip CHP). This means that the width (width in the Y direction) of the covering region CVR2 covering the side) can be made relatively wide. Then, since the relatively wide width (width in the Y direction) of the covering region CVR2 means that the crack resistance against stress is improved, according to the semiconductor device of this modification, the inner pad IPD. , The generation of cracks in the covering region CVR2 of the surface protective film PAS covering the side closest to the end side ES of the semiconductor chip CHP can be suppressed.

  Further, as shown in FIG. 27, in this modification, attention is paid to the inner pad IPD1 closest to the corner CNR of the semiconductor chip CHP among the plurality of inner pads IPD. Specifically, as shown in FIG. 27, in the inner pad IPD1 closest to the corner CNR of the semiconductor chip CHP, the side closest to the corner of the semiconductor chip CHP among the plurality of sides constituting the inner pad IPD1. The width of the covering region CVR3 of the surface protective film PAS covering the surface of the semiconductor chip CHP is also wider than the width of the covering region CVR1 of the surface protective film PAS covering the side farthest from the edge ES of the semiconductor chip CHP.

  Thereby, in this modification, in the inner pad IPD1 closest to the corner portion CNR of the semiconductor chip CHP, a side (semiconductor chip CHP) where stress due to expansion and contraction of resin (not shown) caused by temperature change is likely to increase. The width (width in the Y direction) of the covering region CVR2 covering the edge (side closest to the edge ES) can be made relatively wide. Furthermore, in this modified example, the width of the covering region CVR3 covering the side closest to the corner portion CNR where stress tends to be large can be relatively widened. As a result, in this modification, crack resistance can be particularly improved in the inner pad IPD1 disposed at the position closest to the corner CNR of the semiconductor chip CHP.

  As described above, according to the present modification, not only the outer pad OPD but also the inner pad IPD incorporates a device for the second factor. As a result, according to the present modification, crack resistance against the first factor and the second factor can be improved in both the plurality of outer pads OPD and the plurality of inner pads IPD arranged in a staggered arrangement, thereby Thus, the reliability of the semiconductor device can be further improved.

(Embodiment 5)
In the fifth embodiment, a technical idea in which the above-described third factor is devised will be described. That is, in the fifth embodiment, a line segment (1 of the pad PD) in a direction orthogonal to the width of the covering region with respect to the width of the covering region (width in the Y direction) of the pad PD covered with the surface protective film PAS. “Aluminum slide” in which part of the pad PD shifts and cracks CLK are likely to occur in the surface protective film PAS due to the length of the part (side part) (length in the X direction) becoming longer. Explain the device.

  FIG. 28 is a plan view showing a schematic configuration of the pad PD in the fifth embodiment. In FIG. 28, a lead wiring part DWU is provided integrally with the pad PD. At this time, the width (X-direction width) of the lead-out wiring unit DWU is shorter than the length of the side to which the lead-out wiring unit DWU is connected among the plurality of sides constituting the pad PD. And the center position of the width | variety of the lead-out wiring part DWU has shifted | deviated with respect to the center position of the side where the lead-out wiring part DWU is connected among the some sides which comprise the pad PD.

  In the pad PD according to the fifth embodiment configured as described above, as shown in FIG. 28, one side of the lead-out wiring unit DWU is connected to the lead-out wiring unit DWU in the side to which the lead-out wiring unit DWU is connected. The length of the non-contact line segment is the long side (long line segment side) (the left side of the lead-out wiring portion DWU in FIG. 28). On the other hand, the other side of the lead-out wiring unit DWU is the side where the length of the line segment that does not contact the lead-out wiring unit DWU on the side to which the lead-out wiring unit DWU is connected (short line segment side) (the lead-out wiring in FIG. Right side of the part DWU).

  In the pad PD according to the fifth embodiment configured as described above, the side deflection on the long line segment side increases due to the expansion and contraction of the resin (not shown) caused by the temperature change. As a result, the possibility of occurrence of “aluminum slide” and cracks on the long line segment side increases.

  Therefore, in the fifth embodiment, on the assumption that inclined portions are provided on both sides of the lead wiring portion DWU, the shape of the slope portion SLP1 provided on one side (long line segment side) of the lead wiring portion DWU, The shape of the inclined portion SLP2 provided on the other one side (short line segment side) of the lead wiring portion DWU is made asymmetric.

  Specifically, as shown in FIG. 28, the size of the inclined portion SLP1 provided on one side (long line segment side) of the lead wiring part DWU is set on the other side (short line segment side) of the lead wiring part. It is larger than the size of the inclined portion SLP2 provided. For example, as shown in FIG. 28, the shape of the inclined portion SLP1 provided on one side (long line segment side) of the lead-out wiring portion DWU is a trapezoidal shape, and the other side of the lead-out wiring portion DWU The shape of the inclined portion SLP2 provided on one side (short line segment side) is a triangular shape.

  Thereby, since the size of the inclined portion SLP provided on the long line segment side, on which the side bend is considered to increase, the bend on the long line segment side can be suppressed. As a result, according to the fifth embodiment, it is possible to effectively suppress the occurrence of “aluminum slide” and cracks that are manifested by bending on the long line segment side.

  In particular, according to the study of the present inventor, in FIG. 28, the width (width in the Y direction) of the surface protection film PAS covering the side to which the lead-out wiring portion DWU is connected among the plurality of sides constituting the pad PD. ) Is a1 and the width of the coating region of the surface protective film PAS (width in the X direction) is b1, and when the relationship b1 / a1 <3 is satisfied, due to the stress caused by the expansion and contraction of the resin, It has been found that the bending of the side of the pad PD can be sufficiently suppressed. Further, when the height (Y direction) of the trapezoidal shape that is the inclined portion SLP1 is a2, and the length of the base of the trapezoidal shape that is the inclined portion SLP1 is b2, the relationship b2 / a2 <3 is satisfied. It is desirable for the same reason. Furthermore, it is more desirable to satisfy (b2 / a2) + (b1 / a1) <3.

<Modification 1>
As described in the fifth embodiment, the size of the inclined portion SLP1 provided on one side (long line segment side) of the lead wiring part DWU is provided on the other side (short line segment side) of the lead wiring part. It is desirable to make it larger than the size of the inclined portion SLP2 from the viewpoint of preventing the occurrence of “aluminum slide” and cracks that are manifested by bending on the long line segment side.

  However, making the shape of the inclined portion SLP1 into a trapezoidal shape and making the shape of the inclined portion SLP2 into a triangular shape is merely an example. For example, as shown in FIG. 29, one side of the lead-out wiring portion DWU ( The shape of the inclined part SLP1 provided on the long line segment side is the first triangular shape, and the shape of the inclined part SLP2 provided on the other side (short line segment side) of the lead-out wiring part DWU is the second triangle. It is good also as a shape.

  At this time, the width (width in the Y direction) of the surface protection film PAS covering the side to which the lead wiring part DWU is connected among the plurality of sides constituting the pad PD is defined as a1, and the surface protection film PAS is covered. When the width of the region (width in the X direction) b1 is satisfied, from the viewpoint of surely preventing the occurrence of “aluminum slide” and cracks that satisfy the relationship of b1 / a1 <3, which are manifested by bending on the long line segment side. desirable. Further, when the height (Y direction) of the first triangular shape that is the inclined portion SLP1 is a2, and the length of the base (X direction) of the first triangular shape that is the inclined portion SLP1 is b2, b2 / a2 < It is desirable to satisfy the relationship 3 for the same reason. Furthermore, it is more desirable to satisfy (b2 / a2) + (b1 / a1) <3.

<Modification 2>
Further, the technique disclosed in FIGS. 28 and 29 can be applied to FIGS. 23, 24, and 25 described in the third embodiment. That is, as shown in FIG. 23, the above-described inclined portion SLP1 and inclined portion SLP2 may be formed in the first and second rows of the staggered arrangement. Further, as shown in FIG. 24, the size of the inclined portion SLP1 and the inclined portion SLP2 formed in the second row of the staggered arrangement is larger than the size of the inclined portion SLP1 and the inclined portion SLP2 formed in the first row of the staggered arrangement. You may form so that it may become. Further, as shown in FIG. 25, the inclined portion SLP1 and the inclined portion SLP2 may be formed only in the second row of the staggered arrangement and not formed in the first row. Further, the technique disclosed in FIG. 28 and FIG. 29 can be applied to the above-described fourth embodiment.

(Embodiment 6)
In the sixth embodiment, on the premise that there are a plurality of lead-out wiring portions DWU provided integrally with the pad PD, an example in which the technical idea in which the first factor is devised is applied to this premise configuration Will be described.

  FIG. 30 is an enlarged plan view showing a part of the semiconductor chip CHP in the sixth embodiment. In FIG. 30, for example, out of the plurality of outer pads OPD and the plurality of inner pads IPD arranged in a staggered arrangement, the outer pad OPD2 of the plurality of outer pads OPD is integrated with the outer pad OPD2 so as to be integrated with the lead wiring portion DWU1. And a lead-out wiring portion DWU2. This is an example of a layout configuration implemented to ensure the amount of current flowing through the outer pad OPD2, for example. That is, for example, when the amount of current flowing through the outer pad OPD2 is large and it is difficult to cope with only the single lead-out wiring part DWU1, the lead-out wiring part DWU1 and the lead-out wiring part DWU2 are provided integrally with the outer pad OPD2. Therefore, it is possible to cope with a case where the amount of current is large. Although not shown, the lead-out wiring unit DWU2 is provided with a contact to the lower layer wiring in the same manner as the lead-out wiring unit DWU1, and is electrically connected to the field effect transistor Q provided in the integrated circuit region. doing.

  Further, such a lead-out wiring unit DWU2 has a chip area when there is no space for providing additional pads between the two outer pads OPD or when two pads OPD having the same function such as a power source need to be arranged. This is effective in reducing the size.

  Specifically, as shown in FIG. 30, the outer pad OPD2 has a rectangular shape, and a plurality of lead-out wiring portions connected to the outer pad OPD2 are connected to the short sides of the outer pad OPD2. The wiring portion DWU1 and the lead-out wiring portion DWU2 connected to the long side of the outer pad OPD2. In this case, an inclined portion SLP (OUT) is provided at a connection portion between the outer pad OPD2 and the lead-out wiring portion DWU1, and an inclined portion SLP (OUT) is also provided at a connection portion between the outer pad OPD2 and the lead-out wiring portion DWU2. .

  Also in the outer pad OPD2 in the sixth embodiment configured as described above, it is possible to suppress the generation of cracks at the connection portion between the outer pad OPD2 and the lead-out wiring unit DWU1, and the outer pad OPD2 and the lead-out wiring unit DWU2 The occurrence of cracks can also be suppressed at the connection site.

  Further, in the sixth embodiment, the case where both the lead-out wiring unit DWU1 and the lead-out wiring unit DWU2 are formed in the outer pad OPD2 is illustrated. However, the present invention is not limited to this. For example, only the lead-out wiring unit DWU2 is provided in the outer pad OPD2. Even if it is formed, the same effect can be obtained.

  Further, in the sixth embodiment, an example of a staggered arrangement is shown, but the present invention can also be applied to a case where the pad is only one row as in the first and second embodiments. . That is, the technique disclosed in the sixth embodiment can be applied to the first to fifth embodiments.

(Embodiment 7)
In the seventh embodiment, an example in which the position of the opening of the silicon nitride film SNF is changed in the surface protective film PAS disclosed in FIG. 11 will be described.

  FIG. 31 is a plan view of the pad PD, and FIG. 32 is a cross-sectional view of the pad PD. In the seventh embodiment, after the silicon oxide film OXF1, the silicon oxide film OXF2, and the silicon oxide film OXF3 are formed, the opening OP1 is formed by patterning using the photoresist film as a mask. The barrier conductor film BCF2 is also etched in the same process, and the aluminum film AF is exposed from the opening OP1. Thereafter, a silicon nitride film SNF is formed and separately patterned to form an opening OP2 inside the opening OP1.

  In the seventh embodiment, the side surfaces of the silicon oxide film OXF1, the silicon oxide film OXF2, the silicon oxide film OXF3, and the barrier conductor film BCF2 can be covered with the silicon nitride film SNF in the opening OP1. For this reason, when titanium nitride is used as the barrier conductor film BCF2, it is possible to prevent the titanium nitride from being oxidized. When titanium nitride is oxidized, its volume expands and stress is applied to the surface protective film PAS thereon. As a result, there is a concern that cracks are likely to occur in the silicon nitride film SNF. Therefore, in the seventh embodiment, it is possible to further prevent the occurrence of cracks by covering the side surface of the barrier conductor film BCF2 with the silicon nitride film SNF.

  Needless to say, the technique disclosed in the seventh embodiment can be applied to the first to sixth embodiments. In that case, the opening OP2 of the seventh embodiment corresponds to the opening OP shown in the first to sixth embodiments.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and the embodiments are combined and implemented without departing from the scope of the invention. It goes without saying that it is possible.

  The embodiment includes the following forms.

(Appendix 1)
It has a rectangular semiconductor chip,
The semiconductor chip is
(A) a plurality of pads arranged along an edge of the semiconductor chip;
(B) a lead-out wiring portion provided in each of the plurality of pads;
(C) An inclined portion provided at a connection portion between each of the plurality of pads and the lead-out wiring portion,
Have
The width of the lead-out wiring portion is shorter than the length of the side to which the lead-out wiring portion is connected among the plurality of sides constituting each of the plurality of pads.
The semiconductor device in which the center position of the width of the lead-out wiring portion is deviated from the center position of the side to which the lead-out wiring portion is connected among the plurality of sides constituting each of the plurality of pads.

(Appendix 2)
In the semiconductor device according to attachment 1,
A semiconductor device, wherein the inclined portions are provided on both sides of the lead-out wiring portion.

(Appendix 3)
In the semiconductor device according to attachment 2,
The shape of the inclined portion provided on one side of the lead-out wiring portion and the shape of the slope portion provided on the other side of the lead-out wiring portion are asymmetric.

(Appendix 4)
In the semiconductor device according to attachment 3,
One side of the lead-out wiring part is a side having a long length of a line segment that does not contact the lead-out wiring part among the sides to which the lead-out wiring part is connected,
The other one side of the lead-out wiring part is a side where the length of a line segment that is not in contact with the lead-out wiring part among the sides to which the lead-out wiring part is connected is short,
The semiconductor device, wherein a size of the inclined portion provided on one side of the lead-out wiring portion is larger than a size of the inclined portion provided on the other side of the lead-out wiring portion.

(Appendix 5)
In the semiconductor device according to attachment 4,
The shape of the inclined portion provided on one side of the lead-out wiring portion is a trapezoidal shape, and the shape of the inclined portion provided on the other side of the lead-out wiring portion is a triangular shape. Semiconductor device.

(Appendix 6)
In the semiconductor device according to attachment 5,
(D) having a surface protective film covering each of the plurality of pads, the lead-out wiring portion, and the inclined portion;
The surface protective film is provided with an opening that exposes a part of the surface of each of the plurality of pads.
The height of the trapezoidal shape is a2,
A semiconductor device that satisfies a relationship of b2 / a2 <3, where b2 is the length of the base of the trapezoidal shape.

(Appendix 7)
In the semiconductor device according to attachment 4,
The shape of the inclined portion provided on one side of the lead-out wiring portion is a first triangular shape, and the shape of the inclined portion provided on the other side of the lead-out wiring portion is a second triangle. A semiconductor device in shape.

(Appendix 8)
In the semiconductor device according to attachment 7,
(D) having a surface protective film covering each of the plurality of pads, the lead-out wiring portion, and the inclined portion;
The surface protective film is provided with an opening that exposes a part of the surface of each of the plurality of pads.
The height of the first triangular shape is a2,
A semiconductor device satisfying a relationship of b2 / a2 <3, where b2 is a base length of the first triangular shape.

(Appendix 9)
It has a rectangular semiconductor chip,
The semiconductor chip is
(A) a plurality of pads arranged along an edge of the semiconductor chip;
(B) a lead-out wiring portion provided in each of the plurality of pads;
(C) An inclined portion provided at a connection portion between each of the plurality of pads and the lead-out wiring portion,
Have
A plurality of lead wiring portions are connected to the first pad of the plurality of pads,
The semiconductor device, wherein the inclined portion is provided at each connection portion of the plurality of lead-out wiring portions connected to the first pad.

(Appendix 10)
In the semiconductor device according to attachment 9,
Each of the plurality of pads has a rectangular shape,
The plurality of lead-out wiring portions connected to the first pad include a first lead-out wiring portion connected to the short side of the first pad and a second lead-out wiring connected to the long side of the first pad. A semiconductor device.

(Appendix 11)
(A) preparing a semiconductor substrate having a rectangular chip region and a scribe region that divides the chip region;
(B) A plurality of rectangular pads in the chip region along a boundary line between the chip region and the scribe region, and a lead-out wiring portion provided in each of the plurality of pads;
Forming an inclined portion provided at a connection site between each of the plurality of pads and the lead-out wiring portion;
A method for manufacturing a semiconductor device.

(Appendix 12)
In the method for manufacturing a semiconductor device according to attachment 11,
(C) forming a surface protective film that covers the plurality of pads, the lead-out wiring portion, and the inclined portion;
(D) forming an opening that exposes a part of the surface of each of the plurality of pads in the surface protective film;
(E) after the step (d), obtaining a semiconductor chip by dicing the semiconductor substrate along the scribe region;
(F) a step of connecting a wire to each surface of the plurality of pads exposed from the opening after the step (e);
(G) After the step (f), a step of sealing the semiconductor chip;
A method for manufacturing a semiconductor device, comprising:

(Appendix 13)
In the method for manufacturing a semiconductor device according to attachment 12,
(G) A method for manufacturing a semiconductor device, comprising a step of performing a temperature cycle test after the step.

(Appendix 14)
In the method for manufacturing a semiconductor device according to attachment 12,
In the step (d), the opening is formed so that the center position of the opening is shifted inward of the chip region with respect to the center position of each of the plurality of pads. Method.

(Appendix 15)
In the method for manufacturing a semiconductor device according to attachment 12,
In the step (d), among the plurality of sides constituting each of the plurality of pads, the width of the covering region of the surface protection film covering the side closest to the boundary line is the side farthest from the boundary line A method of manufacturing a semiconductor device, wherein the opening is formed to be wider than a width of a covering region of the surface protection film covering the surface.

(Appendix 16)
In the method for manufacturing a semiconductor device according to attachment 15,
In the step (d), in the first pad closest to the corner of the chip region among the plurality of pads, the corner of the chip region among the plurality of sides constituting the first pad. Forming the opening so that the width of the covering region of the surface protective film covering the side closest to the boundary is wider than the width of the covering region of the surface protective film covering the side farthest from the boundary line, A method for manufacturing a semiconductor device.

1S Semiconductor substrate AF Aluminum film BCF1 Barrier conductor film BCF2 Barrier conductor film CHP Semiconductor chip CLK Crack CNR Corner part CR Chip area CVR1 Covering area CVR2 Covering area CVR3 Covering area DWU Leading wiring part DWU1 Leading wiring part DWU2 Leading wiring part FL Edge part Fine layer GL Global layer ICR Integrated circuit region IL Interlayer insulating film IL1 Inner lead IPD Inner pad IPD1 Inner pad MR Resin OL Outer lead OP Opening OPD Outer pad OPD1 Outer pad OPD2 Outer pad OXF1 Silicon oxide film OXF2 Silicon oxide film OXF3 Silicon oxide Film PAS Surface Protective Film PD Pad PD1 Pad PF Plating Film Q Field Effect Transistor SA1 Semiconductor Device SCR Eve region SLP Inclined portion SLP (IN) Inclined portion SLP (OUT) Inclined portion SLP1 Inclined portion SLP2 Inclined portion SM Discontinuous region SM1 Discontinuous region SM2 Discontinuous region SNF Silicon nitride film SRG Seal ring SRR Seal ring region TAB Chip mounting portion W wire WF semiconductor wafer

Claims (18)

A semiconductor chip having a rectangular shape in plan view,
The semiconductor chip is
In a plan view, a plurality of pads that are disposed along the edge of the semiconductor chip and each have a protruding portion that faces the edge of the semiconductor chip;
A surface protective film covering a part of each of the plurality of pads;
An opening exposing a portion of each surface of the plurality of pads from the surface protective film;
Have
The plurality of pads have a plurality of sides in plan view,
The protruding portion is formed on a part of the plurality of sides facing the end side of the semiconductor chip,
The protrusion is electrically connected to a wiring provided in a lower layer of the plurality of pads through a contact hole,
The protrusion is in plan view,
A first side close to the end side of the semiconductor chip;
A second side intersecting the first side;
A third side facing the second side and intersecting the first side;
Have
At least one of the second side and the third side has a portion that is inclined so that the width of the protruding portion is reduced in a direction from the opening toward the end side of the semiconductor chip in a plan view. , Semiconductor devices. The semiconductor device according to claim 1,
Both the second side and the third side have a portion that is inclined so that the width of the protruding portion is reduced in the direction from the opening toward the end side of the semiconductor chip in plan view. Semiconductor device. The semiconductor device according to claim 1,
The length of the said 1st edge | side is a semiconductor device shorter than the length of the part of the said protrusion part on the opposite side to the said 1st edge | side. The semiconductor device according to claim 1,
Each of the plurality of pads is a semiconductor device covered with the surface protective film. The semiconductor device according to claim 4,
The semiconductor device, wherein the surface protective film is covered with a resin. The semiconductor device according to claim 1,
Each of the plurality of pads is formed of a film containing aluminum as a main component,
The surface protection film is a semiconductor device formed of a silicon oxide film and a silicon nitride film. The semiconductor device according to claim 1,
A semiconductor device, wherein a seal ring is formed between the plurality of pads and the edge of the semiconductor chip. The semiconductor device according to claim 7,
The said seal ring is a semiconductor device formed of the multilayer wiring containing the layer provided with the wiring to which the said protrusion part is connected. The semiconductor device according to claim 1,
In each of the plurality of pads in plan view, the width of the covering region of the surface protection film covering the side closest to the end side of the semiconductor chip covers the side farthest from the end side of the semiconductor chip. A semiconductor device having a width wider than the width of the covering region of the surface protective film. The semiconductor device according to claim 9.
In a plan view, in the first pad closest to the corner of the semiconductor chip among the plurality of pads, the width of the covering region of the surface protection film covering the side closest to the corner of the semiconductor chip is A semiconductor device, which is wider than a width of a covering region of the surface protection film covering a side farthest from the end side of the semiconductor chip. A semiconductor chip having a rectangular shape in plan view,
The semiconductor chip is
A plurality of outer pads located near the edge of the semiconductor chip and disposed along the edge;
A plurality of inner pads located away from the end side of the semiconductor chip and disposed along the end side;
A surface protection film covering a part of each of the plurality of outer pads and a part of each of the plurality of inner pads;
An opening that exposes part of the surface of each of the plurality of outer pads and the plurality of inner pads from the surface protective film;
Have
Each of the plurality of outer pads has a plurality of sides in a plan view, and a protrusion formed on a part of the side opposite to the end side of the semiconductor chip,
Each of the plurality of inner pads has a plurality of sides in a plan view, and a protrusion formed on a part of the side facing the end side of the semiconductor chip,
Each of the protrusions of the plurality of outer pads is electrically connected to a wiring provided in a lower layer of the plurality of outer pads through a contact hole,
Each of the protrusions of the plurality of inner pads is electrically connected to a wiring provided in a lower layer of the plurality of inner pads through a contact hole,
Each of the protrusions of the plurality of inner pads is in plan view,
A first side close to an end side of the semiconductor chip;
A second side intersecting the first side;
A third side facing the second side and intersecting the first side;
Have
At least one of the second side and the third side has a width of the protruding portion of each of the plurality of inner pads reduced in a direction from the opening toward the end side of the semiconductor chip in plan view. A semiconductor device having an inclined portion. The semiconductor device according to claim 11,
In both the second side and the third side, the width of the protruding portion of each of the plurality of inner pads is reduced in the direction from the opening toward the end side of the semiconductor chip in plan view. A semiconductor device having a portion inclined to the surface. The semiconductor device according to claim 11,
The length of the said 1st edge | side is a semiconductor device shorter than the length of the part of the said protrusion part on the opposite side to the said 1st edge | side. The semiconductor device according to claim 11,
Each end of the plurality of outer pads is covered with the surface protective film,
The semiconductor device, wherein each end of the plurality of inner pads is also covered with the surface protective film. The semiconductor device according to claim 11,
Each of the protrusions of the plurality of outer pads is in plan view,
A fourth side close to a side opposite to the end side of the semiconductor chip;
A fifth side intersecting the fourth side;
A sixth side facing the fifth side and intersecting the fourth side;
Have
At least one of the fifth side and the sixth side has the protrusion of each of the plurality of outer pads in a direction from the opening toward the side opposite to the end side of the semiconductor chip in plan view. A semiconductor device having a portion inclined so as to reduce the width of the portion. The semiconductor device according to claim 11,
Each of the protrusions of the plurality of outer pads is in plan view,
A fourth side close to a side opposite to the end side of the semiconductor chip;
A fifth side intersecting the fourth side;
A sixth side facing the fifth side and intersecting the fourth side;
Have
The fifth side and the sixth side of the plurality of outer pads in the direction from the opening toward the side opposite to the end side of the semiconductor chip in plan view. A semiconductor device configured such that the width does not change. The semiconductor device according to claim 11,
In each of the plurality of outer pads in plan view, the width of the covering region of the surface protection film covering the side closest to the end side of the semiconductor chip is the side farthest from the end side of the semiconductor chip. Wider than the width of the covering region of the surface protective film covering,
In plan view, in the first outer pad closest to the corner of the semiconductor chip among the plurality of outer pads, the width of the covering region of the surface protection film covering the side closest to the corner of the semiconductor chip is also A semiconductor device having a width wider than the width of the covering region of the surface protection film covering the side farthest from the end side of the semiconductor chip. The semiconductor device according to claim 17,
In each of the plurality of inner pads in plan view, the width of the covering region of the surface protection film that covers the side closest to the end side of the semiconductor chip is the side farthest from the end side of the semiconductor chip. Wider than the width of the covering region of the surface protective film covering,
In a plan view, among the plurality of inner pads, in the first inner pad closest to the corner of the semiconductor chip, the width of the covering region of the surface protective film covering the side closest to the corner of the semiconductor chip is also A semiconductor device having a width wider than the width of the covering region of the surface protection film covering the side farthest from the end side of the semiconductor chip.

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