JPH0945724A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0945724A JPH0945724A JP7212470A JP21247095A JPH0945724A JP H0945724 A JPH0945724 A JP H0945724A JP 7212470 A JP7212470 A JP 7212470A JP 21247095 A JP21247095 A JP 21247095A JP H0945724 A JPH0945724 A JP H0945724A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor device
- film layer
- pads
- pad portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置におけ
る金属配線及び電極部の配置に関し、特に、高密度集積
化された半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the arrangement of metal wirings and electrode parts in a semiconductor device, and more particularly to a semiconductor device integrated with high density.
【０００２】[0002]
【従来の技術】従来の半導体装置における金属配線及び
電極部の配置を示す、図２（ａ）は半導体装置の平面
図、図２（ｂ）は図２（ａ）のＡ−Ａ′線断面図であ
る。2. Description of the Related Art FIG. 2 (a) is a plan view of a semiconductor device and FIG. 2 (b) is a sectional view taken along the line AA 'in FIG. It is a figure.
【０００３】図中、１は半導体装置、２は保護膜、３は
半導体基板６上の酸化膜層５の窓あけされた部分に形成
された電極部であり、４は、例えばアルミニウムから成
る金属配線層である。In the figure, 1 is a semiconductor device, 2 is a protective film, 3 is an electrode portion formed in a portion of the oxide film layer 5 on the semiconductor substrate 6 where a window is opened, and 4 is a metal made of, for example, aluminum. It is a wiring layer.
【０００４】このうち、電極部３は、半導体基板６上に
形成された半導体素子の取出し用ボンディングパッド部
であり、例えば、図示しないリードフレームとワイヤボ
ンディングにより接続される。Of these, the electrode portion 3 is a bonding pad portion for taking out a semiconductor element formed on the semiconductor substrate 6, and is connected to, for example, a lead frame (not shown) by wire bonding.
【０００５】また、金属配線層４は、上記電極部３の間
を結び、任意の回路を構成している。Further, the metal wiring layer 4 connects the electrode portions 3 to form an arbitrary circuit.
【０００６】[0006]
【発明が解決しようとする課題】ところで、現在のＩＣ
製造においては、より一層の高密度化・小型化が図られ
ており、これに伴って微細加工技術も進歩しているが、
高集積化が進むに従って、ＩＣチップ上におけるボンデ
ィングパッド部の占める面積比率も大きくなり、小型化
を阻害していた。By the way, current ICs
In manufacturing, further densification and miniaturization have been sought, and along with this, fine processing technology has also advanced,
As the degree of integration increases, the area ratio of the bonding pad portion on the IC chip also increases, which hinders miniaturization.
【０００７】また、単にボンディングパット部の面積を
小さくしただけでは、信頼性に欠け、作業性も悪いとい
う問題がある。Further, simply reducing the area of the bonding pad portion causes a problem that reliability is poor and workability is poor.
【０００８】さらに、ボンディングパット部の配置も、
任意に選択できる余地がないので、設計の自由度が少な
いという問題もあった。Further, the arrangement of the bonding pad is
Since there is no room for arbitrary selection, there is also a problem that the degree of freedom in design is low.
【０００９】本発明の目的は、以上に述べたような従来
の半導体装置のもつ問題に鑑み、高集積化する半導体装
置において、より一層の高密度化・小型化を図り、且つ
性能を維持した半導体装置を得るにある。In view of the problems of the conventional semiconductor device as described above, the object of the present invention is to further increase the density and size of the semiconductor device to be highly integrated and maintain the performance. In obtaining a semiconductor device.
【００１０】[0010]
【課題を解決するための手段】本発明によれば、上述の
目的は、半導体基板上に、各半導体素子の下部パッド部
間を結ぶ金属配線層と、絶縁膜層とが順に積層されてお
り、かつ絶縁膜層には下部パッド部に対応した部分に窓
あけがされ、さらに絶縁膜層上に下部パッド部と導通す
る上部ボンディングパッド部が形成されており、半導体
装置の電極部が、金属配線層と同じ層に形成された下部
パッド部と、金属配線層上の絶縁膜層の上面に形成され
た上部ボンディングパッド部とから成り、絶縁膜層上に
は、上部ボンディングパッド部のみが形成された半導体
装置により達成される。According to the present invention, the above-described object is to form a metal wiring layer connecting between lower pad portions of each semiconductor element and an insulating film layer in this order on a semiconductor substrate. In the insulating film layer, a window is opened in a portion corresponding to the lower pad portion, and an upper bonding pad portion that is electrically connected to the lower pad portion is formed on the insulating film layer. It consists of a lower pad part formed on the same layer as the wiring layer and an upper bonding pad part formed on the upper surface of the insulating film layer on the metal wiring layer. Only the upper bonding pad part is formed on the insulating film layer. It is achieved by the semiconductor device described above.
【００１１】[0011]
【発明の実施の形態】本発明の実施例を図１（ａ）、
（ｂ）に基づいて詳細に説明する。図１（ａ）は本発明
に係る半導体装置の実施例を示す平面図であり、図１
（ｂ）は図１（ａ）中のＢ−Ｂ′線断面図である。図
中、図２と同じ部分については同符号を付し、その詳細
な説明は省略する。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention is shown in FIG.
A detailed description will be given based on (b). 1A is a plan view showing an embodiment of a semiconductor device according to the present invention.
FIG. 1B is a sectional view taken along line BB ′ in FIG. 2, those parts which are the same as those corresponding parts in FIG. 2 are designated by the same reference numerals, and a detailed description thereof will be omitted.
【００１２】図１中、１０は半導体装置、１１は半導体
基板６上の酸化膜層５の窓あけされた部分に形成された
下部パッド部であり、例えばアルミニウムから成る金属
配線層４により、これら下部パッド部３の間を結び、任
意の回路を構成している。In FIG. 1, 10 is a semiconductor device, and 11 is a lower pad portion formed in a window-opened portion of an oxide film layer 5 on a semiconductor substrate 6, which is formed by a metal wiring layer 4 made of, for example, aluminum. The lower pad portions 3 are connected to form an arbitrary circuit.
【００１３】図中１２は、上記金属配線層４及び下部パ
ッド部１１上に形成された層間絶縁膜であり、後述する
保護膜と同様の材料から成る。例えば、ＮＳＧ（ノンド
ープ・シリケートガラス）、ＰＳＧ（リンシリケートガ
ラス）またはＳｉＮ（窒化シリコン）等から構成され
る。Reference numeral 12 in the drawing denotes an interlayer insulating film formed on the metal wiring layer 4 and the lower pad portion 11, and is made of the same material as a protective film described later. For example, it is made of NSG (non-doped silicate glass), PSG (phosphorus silicate glass), SiN (silicon nitride), or the like.
【００１４】図中８は、例えばアルミニウムから成る金
属配線９を介して、下部パッド部１１と導通接続された
上部ボンディングパッド部であり、図示しないリードフ
レームとワイヤボンディング等で接続される取り出し電
極部である。Reference numeral 8 in the drawing denotes an upper bonding pad portion which is conductively connected to the lower pad portion 11 via a metal wiring 9 made of, for example, aluminum, and an extraction electrode portion which is connected to a lead frame (not shown) by wire bonding or the like. Is.
【００１５】また、図中７は、半導体装置１０の最上部
に位置する保護膜であり、上部ボンディングパッド部８
に対応する部分には窓あけがされている。Reference numeral 7 in the drawing denotes a protective film located at the uppermost portion of the semiconductor device 10, and an upper bonding pad portion 8
There is a window in the part corresponding to.
【００１６】図１（ａ）に示されるように、隣り合うパ
ッド８は互いに千鳥状に配され、このことにより、下部
パッド１１に比較して面積が大きいボンディングパッド
８が形成される。As shown in FIG. 1A, adjacent pads 8 are arranged in a zigzag pattern, whereby bonding pads 8 having a larger area than the lower pads 11 are formed.
【００１７】[0017]
【発明の効果】以上述べたように、本発明によれば、半
導体基板に接する下部パッド部及びこの下部パッド部と
同じ層に位置する金属配線層と、上部ボンディングパッ
ド部とが異る層に形成されると共に、この上部ボンディ
ングパット部のみが配設された専用層が形成されるた
め、上部ボンディングパッドの形状を、ＩＣの高集積化
に左右されることなく大型化できることから、作業性も
良く、信頼性の高い半導体装置を得ることができる。As described above, according to the present invention, the lower pad portion contacting the semiconductor substrate, the metal wiring layer located in the same layer as the lower pad portion, and the upper bonding pad portion are different layers. Since the dedicated layer is formed and only the upper bonding pad portion is formed, the shape of the upper bonding pad can be increased without being influenced by the high integration of the IC, and the workability is also improved. A good and highly reliable semiconductor device can be obtained.
【００１８】また、上部ボンディングパッドの位置も任
意に選択でき、設計の自由度が増す。Further, the position of the upper bonding pad can be arbitrarily selected, which increases the degree of freedom in design.
【００１９】さらに、上部ボンディングパッド部が、金
属配線層と異る層に形成されていることから、上部ボン
ディングパッド部の大きさに左右されずに、ＩＣの高密
度化・小型化をより一層図ることができる。Further, since the upper bonding pad portion is formed in a layer different from the metal wiring layer, the density and size of the IC can be further improved regardless of the size of the upper bonding pad portion. Can be planned.
【図１】（ａ）は、本発明による半導体装置の実施例を
示す平面図である。（ｂ）は、（ａ）に示す半導体装置
のＢ−Ｂ′線断面図である。FIG. 1A is a plan view showing an embodiment of a semiconductor device according to the present invention. (B) is a BB 'sectional view taken on the line of the semiconductor device shown in (a).
【図２】（ａ）は、従来の半導体装置の一例を示す平面
図である。（ｂ）は、（ａ）に示す半導体装置のＡ−
Ａ′線断面図である。FIG. 2A is a plan view showing an example of a conventional semiconductor device. (B) is A- of the semiconductor device shown in (a).
It is an A'line sectional view.
４ 金属配線層 ５ 酸化膜層 ６ 半導体基板 ７ 保護膜層 ８ 上部ボンディングパッド部 ９ 金属配線 １０ 半導体装置 １１ 下部パッド部 １２ 絶縁膜層 4 metal wiring layer 5 oxide film layer 6 semiconductor substrate 7 protective film layer 8 upper bonding pad portion 9 metal wiring 10 semiconductor device 11 lower pad portion 12 insulating film layer
Claims (2)
ッド部間を結ぶ金属配線層と、絶縁膜層とが順に積層さ
れており、かつ該絶縁膜層には該下部パッド部に対応し
た部分に窓あけがされ、さらに該絶縁膜層上に該下部パ
ッド部と導通する上部ボンディングパッド部が形成され
ており、半導体装置の電極部が、該金属配線層と同じ層
に形成された該下部パッド部と、該金属配線層上の該絶
縁膜層の上面に形成された該上部ボンディングパッド部
とから成り、該絶縁膜層上には、該上部ボンディングパ
ッド部のみが形成されていることを特徴とする半導体装
置。1. A metal wiring layer connecting between lower pad portions of each semiconductor element and an insulating film layer are sequentially laminated on a semiconductor substrate, and the insulating film layer corresponds to the lower pad portions. A window is opened in the portion, and an upper bonding pad portion that is electrically connected to the lower pad portion is formed on the insulating film layer, and the electrode portion of the semiconductor device is formed in the same layer as the metal wiring layer. A lower pad portion and an upper bonding pad portion formed on the upper surface of the insulating film layer on the metal wiring layer, and only the upper bonding pad portion is formed on the insulating film layer. A semiconductor device characterized by:
上記絶縁膜層上に保護膜層が形成されていることを特徴
とする請求項第１に記載の半導体装置。2. Excluding the upper bonding pad portion,
The semiconductor device according to claim 1, wherein a protective film layer is formed on the insulating film layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7212470A JPH0945724A (en) | 1995-07-28 | 1995-07-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7212470A JPH0945724A (en) | 1995-07-28 | 1995-07-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0945724A true JPH0945724A (en) | 1997-02-14 |
Family
ID=16623184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7212470A Pending JPH0945724A (en) | 1995-07-28 | 1995-07-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0945724A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998029261A1 (en) * | 1996-12-26 | 1998-07-09 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
| JP2003086530A (en) * | 2001-09-11 | 2003-03-20 | Sony Corp | Ion implantation method and apparatus |
| JP2018029193A (en) * | 2017-09-21 | 2018-02-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
1995
- 1995-07-28 JP JP7212470A patent/JPH0945724A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998029261A1 (en) * | 1996-12-26 | 1998-07-09 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
| US6259158B1 (en) | 1996-12-26 | 2001-07-10 | Hitachi, Ltd. | Semiconductor device utilizing an external electrode with a small pitch connected to a substrate |
| US6841871B2 (en) | 1996-12-26 | 2005-01-11 | Hitachi, Ltd. | Semiconductor device utilizing pads of different sizes connected to an antenna |
| JP2003086530A (en) * | 2001-09-11 | 2003-03-20 | Sony Corp | Ion implantation method and apparatus |
| JP2018029193A (en) * | 2017-09-21 | 2018-02-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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