JP2009231371A - Semiconductor chip and semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor chip capable of downsizing and a semiconductor apparatus. <P>SOLUTION: A semiconductor chip includes: a semiconductor substrate 11 having an upper surface, a bottom surface and a side face 13 for connecting them; an upper wire 15 provided on the upper surface and connected with a semiconductor element formed on the semiconductor substrate 11; a plurality of connection terminals 26 provided on the bottom surface and placed separately from the side face 13 in an interior surrounded by the side face 13; a through wire 25 passing through a through-hole 21 passing through the semiconductor substrate 11 for electrically connecting the upper wire 15 with the connection terminals 26; and an insulative isolation film 27 provided on the bottom surface between the connection terminals 26 and placed across a recess 31 from the connection terminals 26. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor chip having a wiring penetrating a semiconductor substrate and a semiconductor device.

  Semiconductor devices are required to be miniaturized, that is, to reduce the mounting area with respect to the wiring board, and to reduce the height from the wiring board.

  2. Description of the Related Art Conventionally, semiconductor devices in which a semiconductor chip is fixed to a lead frame, connected with bonding wires, and lead terminals extend from a sealing resin are widely used. A semiconductor device packaged with a sealing resin or the like with respect to a semiconductor chip requires a space for mounting several to several tens of times.

  Therefore, the semiconductor chip is bonded onto one main surface of the island (internal lead), the island forms a part of the external connection electrode, and a plurality of lead terminals are provided at positions away from the island, and the electrode pad of the semiconductor chip And a lead terminal are electrically connected by a bonding wire, and a semiconductor device is disclosed that is entirely covered with a sealing resin (see, for example, Patent Document 1).

In the disclosed semiconductor device, since the bottom surface of the internal lead and the lead terminal are formed in the same plane and do not protrude from the sealing resin, the mounting is performed in comparison with the case where the lead terminal extends from the sealing resin. However, since the semiconductor device and the lead terminal are connected by a bonding wire, an area (horizontal expansion) for arranging the lead terminal in a plane is necessary, and bonding is also performed. Since a certain height is required on the semiconductor chip in order to form a loop in the wire, there is a problem that miniaturization is insufficient.
JP 10-313082 A (page 4, FIG. 1)

  An object of this invention is to provide the semiconductor chip and semiconductor device which can be reduced in size.

  A semiconductor chip of one embodiment of the present invention includes a semiconductor substrate having a top surface, a bottom surface facing the top surface, and a side surface connecting the top surface and the bottom surface, and a semiconductor element formed on the semiconductor substrate. An upper wiring connected to the plurality of terminals, a plurality of connection terminals disposed on the bottom surface and spaced apart from the side surface, and through the through hole penetrating the semiconductor substrate, the upper wiring and the connection terminals are electrically connected. And a through-hole wiring that is provided on the bottom surface and is spaced apart from the connection terminal to form a recess between the connection terminal and the connection terminal.

  According to another aspect of the present invention, there is provided a semiconductor device according to any one of claims 1 to 4, an internal lead connected to a connection terminal of the semiconductor chip, and a lead terminal connected to the internal lead. And the semiconductor chip, the internal lead, and a sealing resin for sealing the lead terminal so that the lead terminal is exposed on the surface mounted on the wiring board.

  According to the present invention, it is possible to provide a semiconductor chip and a semiconductor device that can be miniaturized.

  Embodiments of the present invention will be described below with reference to the drawings. In the figure shown below, the same code | symbol is attached | subjected to the same component.

  A semiconductor chip according to Embodiment 1 of the present invention will be described with reference to FIGS. 1A and 1B are diagrams schematically showing a configuration of a semiconductor chip, FIG. 1A is a plan view seen from the bottom surface, and FIG. 1B is a cross-sectional view taken along line AA in FIG. It is. 2A and 2B are diagrams schematically showing mounting of the semiconductor chip on the wiring board. FIG. 2A is a cross-sectional view of the wiring board, and FIG. 2B is a cross-sectional view of the semiconductor chip fixed to the wiring board. .

  As shown in FIG. 1, the semiconductor chip 1 passes through a semiconductor substrate 11, an upper wiring 15 on the upper surface of the semiconductor substrate 11, a connection terminal 26 on the bottom surface of the semiconductor substrate 11, and a through hole 21 that penetrates the semiconductor substrate 11. In addition, a through wiring 25 that electrically connects the upper wiring 15 and the connection terminal 26, and a separation film 27 that is spaced apart from the connection terminal 26 and has an insulating property and poor solder wettability are provided. The semiconductor chip 1 has a form that can be mounted on a wiring board described later. When the semiconductor chip 1 is mounted on a wiring board placed almost horizontally, the upper surface of the semiconductor substrate 11 is the upper surface, the lower surface of the semiconductor substrate 11 is the bottom surface, and the upper surface and the bottom surface The side surface in between is called a side surface.

  The semiconductor substrate 11 is made of silicon, but may be a compound semiconductor such as GaAs or GaN. The semiconductor substrate 11 has, for example, a rectangular shape with a side of about 300 μm and a shape close to a rectangular parallelepiped with a thickness of about 100 μm.

  Although not shown, the semiconductor substrate 11 has a semiconductor element made of, for example, a bipolar transistor on the upper surface, and three electrodes are formed thereon. The semiconductor element may be a bipolar transistor, a diode, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or may be an integrated circuit by adding elements such as a resistor, a capacitor, and an inductor. .

  The three electrodes of the bipolar transistor are connected to an upper wiring 15 formed thereon, with an interlayer insulating film (not shown) such as a silicon oxide film covering the upper surface of the semiconductor substrate 11 interposed therebetween, for example. The upper wiring 15 is made of, for example, Al, and leads an electrode of a semiconductor element arranged at the center of the semiconductor substrate 11 to the peripheral portion of the semiconductor substrate 11. The upper wiring 15 can be made of a conductive material mainly composed of Al, such as Al or AlSiCu, or a conductive material mainly composed of Cu, Au, W, Cu, Au, W, or the like. is there.

  For example, one end of the upper wiring 15 is connected to the collector, one is connected to the base, and the other two are connected to the emitter. The other ends of the upper wiring 15 are respectively positioned so as to cover the upper surface side openings of the through holes 21 and are disposed so as to block all the upper surface side openings. The other end of the upper wiring 15 may be disposed so as to block a part of the upper surface side opening.

  A protective film 17 made of a silicon nitride film, a polyimide resin, an epoxy resin, a fluorine resin, or the like is formed on the upper surface of the semiconductor substrate 11 so as to cover the upper wiring 15 and the like.

  The through holes 21 are arranged with openings at four corners on the upper surface and the bottom surface of the semiconductor substrate 11. The through-hole 21 has a large diameter on the bottom surface side, for example, 50 to 100 μm, and a small diameter on the top surface side, for example, 25 to 50 μm, and is surrounded by a wall surface that is substantially close to the side surface of the truncated cone. The substantially circular opening on the upper surface side reaches the upper wiring 15. The edge of the substantially circular opening on the bottom surface side is located at a position about 25 μm from the side surface 13 of the semiconductor substrate 11 and enters the center side (inside) of the bottom surface. The wall surface of the through hole 21 hardly affects the characteristics of the semiconductor element or the like formed on the semiconductor substrate 11, that is, at a position where the change in electric field or magnetic field distribution of the semiconductor element or the like caused by the wall surface can be substantially ignored. It is formed.

  An insulating film 23 made of, for example, a silicon oxide film is formed on the wall surface of the through hole 21, and a base layer (for example, made of Ti and Cu) is formed on the surface of the insulating film 23 and the surface of the upper wiring 15 on the through hole 21 side. A through wiring 25 made of Cu (not shown) and Cu (surface) thereon is formed. The film thickness of the through wiring 25 is, for example, about 5 to 10 μm, and the surface of the through wiring 25 substantially forms a side surface and an upper surface of a truncated cone. Note that the through wiring 25 can be formed thicker or thinner depending on the characteristics required for the semiconductor chip 1.

  The connection terminal 26 is formed of a conductive material continuous from the through wiring 25, and is formed concentrically with the substantially circular opening on the bottom surface side of the through hole 21, that is, in a donut shape. The outside of the connection terminal 26 enters the inside of the bottom surface by about 5 μm from each side surface 13 of the corner of the semiconductor substrate 11. The connection terminal 26 has an insulating film 23 continuous from the wall surface side of the through hole 21 as a base. The film thickness of the connection terminal 26 is substantially the same as the film thickness of the through wiring 25 and is, for example, about 5 to 10 μm.

  Next, a method of forming the through hole 21, the through wiring 25, the connection terminal 26, and the like will be described. The through hole 21 is formed from the bottom surface of the semiconductor substrate 11 by, for example, a well-known RIE (Reactive Ion Etching) method compatible with high-speed processing.

  An insulating film 23 made of a silicon oxide film is formed on the wall surface of the through hole 21 and the bottom surface of the semiconductor substrate 11 by, for example, a CVD (Chemical Vapor Deposition) method. Thereafter, the insulating film 23 on the through hole 21 side of the upper wiring 15 is removed by, for example, an EB (Electron Beam) method. For example, a base layer (not shown) made of Ti and Cu is formed on the surface of the insulating film 23 of the through hole 21 and the upper wiring 15 on the through hole 21 side by a PVD (Physical Vapor Deposition) method such as sputtering. . Then, Cu is formed thereon (surface) by a plating method.

  Before plating, a resist for plating having an opening is formed at a position to be the through wiring 25 and the connection terminal 26 on the base layer, and then Cu is plated to form the through wiring 25 and the connection terminal 26. Is done. Thereafter, unnecessary base layers are removed by etching using the formed through wiring 25 and connection terminal 26 as a mask. At the time of this etching, the surface of the through wiring 25 and the connection terminal 26 is partially etched at the same time. However, since the etched portion is formed thick in advance, there is no problem.

  The separation film 27 separates the connection terminals 26 at the corners of the four corners on the bottom surface of the semiconductor substrate 11. The separation film 27 is made of, for example, a silicon oxide film, and is formed to have a film thickness that is substantially the same as the surface of the connection terminal 26. The separation film 27 is cut off at the corners of the four corners in the shape of a fan or a shape close to a fan shape including the nearest connection terminal 26 around the corner of the bottom surface of the semiconductor substrate 11. A groove-like recess 31 having a width of about 10 μm or more and a depth corresponding to each film thickness is formed and separated.

  The separation film 27 is not limited to a silicon oxide film, and has poor wettability with respect to solder, that is, has a property of repelling solder, for example, an aluminum oxide film, a silicon nitride film, a resin such as polyimide, PSG (Phosphorus Silicate Glass) ), Silicate glasses such as BSG (Boron Silicate Glass) and BPSG (Boron Phospho Silicate Glass), and insulating films such as SOG (Spin on Glass) can be used. Note that the poor wettability with respect to solder means that the contact angle of the molten solder with the surface of the separation film 27 becomes large and the solder appears to be rounded.

  As described above, the semiconductor chip 1 includes the semiconductor substrate 11 having the upper surface, the bottom surface, and the side surface 13 that connects these surfaces, and the upper wiring 15 that is on the upper surface and is connected to the semiconductor element formed on the semiconductor substrate 11. And a plurality of connection terminals 26 arranged on the bottom surface and spaced apart from the side surface 13 on the inner side surrounded by the side surface 13, and the upper wiring 15 and the connection terminals 26 through the through holes 21 penetrating the semiconductor substrate 11. Are provided on a bottom surface between the connection terminals 26 and an insulating separation film 27 disposed with a recess 31 therebetween.

  The semiconductor chip 1 is in a form after being singulated. In other words, before being singulated, the semiconductor chip 1 is manufactured by a series of manufacturing processes by configuring a semiconductor wafer in a state of being arranged in a lattice pattern, although illustration is omitted. Thereafter, the semiconductor wafer is separated into semiconductor chips 1 by a dicing method using a blade or the like so as to have the side surface 13. During dicing, the protective film 17, the interlayer insulating film (not shown), the semiconductor substrate 11, and the insulating film 23 are cut.

  Next, mounting of the semiconductor chip 1 on the wiring board will be described. The semiconductor chip 1 has a connection terminal 26 on the bottom surface and can be mounted on the surface. Further, since the top surface is covered with the protective film 17 and the bottom surface is covered with the insulating film 23, the through wiring 25, or the separation film 27, it has moisture resistance and the like.

  As shown in FIG. 2A, a wiring substrate 41 for surface mounting the semiconductor chip 1 is prepared. Substrate wiring 43 having terminals is formed on the surface of the wiring substrate 41 at positions corresponding to the connection terminals 26, and the substrate wiring 43 between the substrate wirings 43 and unnecessary exposure is covered with the solder resist 45. An appropriate amount of solder 51 is formed on the surface of the substrate wiring 43. Instead of the solder 51, it is possible to use a conductive adhesive such as an Ag paste.

  As shown in FIG. 2B, the semiconductor chip 1 is mounted on the surface of the wiring board 41. The semiconductor chip 1 is placed on the molten solder 51 so that the connection terminal 26 is applied, and the position where the surface tension of the solder 51 and the semiconductor chip 1 are balanced, that is, the substrate wiring 43 and the connection terminal 26 face each other. Moves to a position (self-alignment effect) and is fixed by cooling. It is advantageous that the connection terminal 26 is preliminarily subjected to solder plating or the like so as to improve the wettability with the solder.

  A gap between the through wiring 25 and the solder 51 or the wiring substrate 41 is filled with dry air and is in a sealed state. In addition to dry air, dry nitrogen or inert gas can be used. Thereafter, although not shown, it is possible to perform potting with an epoxy resin or the like so as to cover the semiconductor chip 1.

  In the semiconductor chip 1, the upper wiring 15 connected to the semiconductor element on the upper surface is connected to the connection terminal 26 on the bottom surface using the through wiring 25 formed inside the through hole 21 as the wiring. Although the semiconductor chip 1 requires a region for forming the through hole 21 and the connection terminal 26, it is not necessary to stretch the bonding wire to the outside of the semiconductor chip 1, and the area for mounting can be reduced. .

  Further, in the semiconductor chip 1, instead of the bonding wire, the upper wiring 15 is connected to the connection terminal 26 using the through wiring 25 having a large cross-sectional area perpendicular to the connection direction and a short distance as the wiring, so that the inductance is reduced. Therefore, it is possible to suppress the deterioration of the high frequency characteristics of the semiconductor element.

  Further, in order to form the upper wiring 15 in contact with the upper portion of the through hole 21, the semiconductor chip 1 needs to draw the upper wiring 15 to the corners of the four corners. It is not necessary to make the insulating film and the wiring layer on the upper surface of the substrate 11 have a special configuration. Therefore, the thickness of the semiconductor chip 1 can be formed thin enough to be almost determined by the protective film 17, the semiconductor substrate 11, and the connection terminal 26.

  In addition, since the semiconductor chip 1 has the separation film 27 having poor solder wettability disposed with the recess 31 away from the connection terminal 26, when the solder 51 for mounting is more than an appropriate amount, the recess 31 and The amount that protrudes beyond the separation membrane 27 is suppressed. That is, a part of the solder 51 wraps around the concave portion 31 to reduce the amount of the solder 51 that moves in the direction of the adjacent connection terminal 26, thereby suppressing a short circuit between the connection terminals 26. As a result, the semiconductor chip 1 can improve the mounting yield. Note that the gap inside the through wiring 25 derived from the through hole 21 is effective in reducing the amount of excessive solder 51 flowing out from the connection terminal 26.

  Further, in the semiconductor chip 1, the outside of the connection terminal 26 is inside the bottom surface by about 5 μm from both side surfaces 13 of the corners of the semiconductor substrate 11. When dicing into individual pieces, there is no need to cut through wiring 25, so that the through wiring 25 is not peeled off or pulled, and the manufacturing yield of the semiconductor chip 1 can be improved. . In addition, since it is not necessary to cut both the semiconductor substrate 11 and the through wiring 25, it is possible to prevent the blade of the dicing apparatus from rapidly deteriorating and to reduce the frequency of blade replacement.

  Next, a first modification of the first embodiment will be described with reference to FIG. FIG. 3 is a diagram schematically showing the configuration of the semiconductor chip, FIG. 3 (a) is a plan view seen from the bottom surface direction, and FIG. 3 (b) is a sectional view taken along line BB in FIG. 3 (a). It is. The semiconductor chip 1 is different in that two connection terminals are connected on the bottom surface of the semiconductor substrate. In addition, the same code | symbol is attached | subjected to the same component as the said Example 1, and the description is abbreviate | omitted.

  As shown in FIG. 3, the semiconductor chip 2 has connection terminals 26 similar to the connection terminals 26 of the first embodiment at diagonal positions from the lower left to the upper right of the drawing. It has the connecting terminal 56 extended in the diagonal direction in the corner position. The connection terminal 56 has a structure in which connection terminals 56a and 56b having the same position and structure as the connection terminal 26 of the first embodiment are connected by a conductive material so that the connection terminal 56c at the center is constricted with a smooth curve. ing. Note that the two connection terminals connected on the bottom surface do not necessarily have to be constricted at the center, and do not necessarily have to be in a diagonal position.

  The upper wiring 15 corresponding to the connection terminals 56a and 56b is connected to the two emitters of the semiconductor chip 1 of the first embodiment.

  The separation membrane 27 has a boundary formed so as to form a recess 31 therebetween at a distance of about 10 μm or more from the connection terminal 56. That is, the separation membrane 27 has a shape surrounding the connection terminal 26 and along the extending direction of the connection terminal 56. Other configurations are almost the same as those of the semiconductor chip 1 of the first embodiment.

  In the semiconductor chip 2, the two connection terminals 56 a and 56 b at diagonal positions are connected to form one connection terminal 56. Therefore, the upper wiring 15 corresponding to the connection terminals 56 a and 56 b needs to be connected on the upper surface of the semiconductor substrate 11. The degree of freedom of wiring on the upper surface is increased. Further, when the semiconductor chip 2 is mounted, it is possible to flow the solder 51 in the diagonal direction, so that a short circuit between the connection terminal 26 and the connection terminal 56 can be reduced. Further, more heat can be radiated from the bottom surface of the semiconductor substrate 11 through the connection terminal 56. In addition, the semiconductor chip 1 according to the first embodiment has the same effects.

  Next, a second modification of the first embodiment will be described with reference to FIG. 4A and 4B are diagrams schematically showing the configuration of the semiconductor chip. FIG. 4A is a plan view viewed from the bottom surface, and FIG. 4B is a cross-sectional view taken along the line CC in FIG. It is. The semiconductor chip 1 is different from the semiconductor chip 1 in that two connection terminals are connected at the bottom surface of the semiconductor substrate and a heat radiation hole is provided at the center of the bottom surface of the semiconductor substrate. In addition, the same code | symbol is attached | subjected to the same component as the said Example 1 and the modification 1, and the description is abbreviate | omitted.

  As shown in FIG. 4, the semiconductor chip 3 has connection terminals 26 and 57 similar to the connection terminals 26 and 56 of the first modification of the first embodiment. The connection terminal 57 has connection terminals 57a, 57b, and 57c corresponding to the connection terminals 56a, 56b, and 56c of Modification 1, respectively, and a heat dissipation hole 61 is provided at the center of the connection terminal 57c. The constriction is small. Note that the two connection terminals connected on the bottom surface do not necessarily have to be constricted at the center, and do not necessarily have to be in a diagonal position.

  The heat radiation hole 61 of the connection terminal 57 c reaches the central portion, that is, the central bottom surface portion of the semiconductor substrate 11 to the central portion in the thickness direction of the semiconductor substrate 11. The heat radiation hole 61 is separated from the semiconductor element on the upper surface of the semiconductor substrate 11 to such an extent that the characteristics are not substantially affected. Similar to the surface of the through hole 21, a through wiring film 25 a corresponding to the insulating film 23 and the through wiring 25 is formed on the surface of the heat radiation hole 61. The connection terminal 57c around the heat radiation hole 61 can be formed away from the connection terminals 57a and 57b. When the connection terminal 57c is separated from the connection terminals 57a and 57b, heat dissipation is weakened. Therefore, it is preferable that the connection terminal 57c is connected and fixed on a wiring board (see FIG. 2) having heat dissipation means connected to the connection terminal 57c.

  The separation membrane 27 has a boundary formed so as to form a recess 31 therebetween at a distance of about 10 μm or more from the connection terminal 57. That is, the separation membrane 27 has a shape surrounding the connection terminal 26 and along the extending direction of the connection terminal 57. Other configurations are almost the same as those of the semiconductor chip 2 of the first modification of the first embodiment.

  Since the semiconductor chip 3 has a large surface area corresponding to the heat radiation hole 61 formed and has the through wiring film 25 a and the wide connection terminal 57, the semiconductor of the first modification example from the bottom surface side of the semiconductor substrate 11. It is possible to dissipate more heat by radiation and conduction than the chip 2. In addition, the semiconductor chip 2 of the first modification of the first embodiment has the same effect.

  A semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIG. 5A and 5B are diagrams schematically showing the configuration of the semiconductor device. FIG. 5A is a plan view seen from the bottom surface, and FIG. 5B is a cross-sectional view taken along the line DD in FIG. It is. The semiconductor device is different from the first embodiment in that the semiconductor chip 1 of the first embodiment is packaged by covering with a sealing resin. In addition, the same code | symbol is attached | subjected to the component same as Example 1, and the description is abbreviate | omitted.

  As shown in FIG. 5, the semiconductor device 5 includes a semiconductor chip 1 according to the first embodiment, a lead terminal 75 connected to the connection terminal 26 of the semiconductor chip 1, and at least one surface of the lead terminal 75 exposed. A chip 1, internal leads 73, and a sealing resin 81 for sealing the lead terminals 75 are provided.

  The semiconductor device 5 has an outer shape on the surfaces of the sealing resin 81 and the lead terminals 75 and is substantially a rectangular parallelepiped. At the four corners of the mounting surface side (referred to as the bottom surface) of the sealing resin 81, the respective surfaces of the four lead terminals 75 and the side surfaces of the sealing resin 81 are respectively connected to the respective surfaces of the four lead terminals 75 from the bottom surface. Exposed. The internal lead 73 and the lead terminal 75 can use a well-known lead frame, and are made of, for example, Cu, Cu alloy, Fe—Ni alloy, or the like.

  The lead terminal 75 is bent in a staircase shape or a gull wing shape, and is connected to the internal lead 73 that is one step higher than the bottom surface. The top surface opposite to the bottom surface of the internal lead 73 is formed to be substantially flat. The four internal leads 73 are separated from each other, and the upper surfaces of the four internal leads 73 are substantially flat. The upper surfaces of the four internal leads 73 and the four connection terminals 26 of the semiconductor chip 1 are in corresponding positions, and the connection terminals 26 of the semiconductor chip 1 are connected to the internal leads 73 via solder 71. Instead of the solder 71, it is possible to use a conductive adhesive such as an Ag paste.

  A gap between the through wiring 25 and the solder 71 or the internal lead 73 is filled with dry air and is in a sealed state. In addition to dry air, dry nitrogen or inert gas can be used.

  The portions excluding the bottom surface and one side surface of the internal lead 73, the semiconductor chip 1, and the lead terminal 75 are covered with a sealing resin 81.

  The semiconductor device 5 does not require a bonding wire in order to connect the connection terminal 26 and the internal lead 73. For this reason, the height for forming the bonding wire in a loop shape is not required on the upper side of the semiconductor chip 1, and the height of the semiconductor device 5 can be kept low. Further, in order to connect the bonding wire and the internal lead, it is not necessary to arrange the internal lead at a position separated from the semiconductor chip 1, and the mounting area can be reduced. Compared to the semiconductor chip 1, both the mounting area and the height are increased, but the semiconductor device 5 is easier to handle.

  In addition, since the semiconductor device 5 does not use a bonding wire, it is possible to reduce inductance compared to a semiconductor device that requires a bonding wire, and to suppress deterioration of high-frequency characteristics of a semiconductor element. .

  As a modification of the second embodiment, the semiconductor chip 2 of the first modification of the first embodiment or the semiconductor chip 3 of the second modification of the first embodiment is fixed to the internal lead 73 instead of the semiconductor chip 1. Thus, a semiconductor device can be obtained. The semiconductor devices according to these modified examples have the same effects as the semiconductor device 5 according to the second embodiment.

  As mentioned above, this invention is not limited to the said Example, In the range which does not deviate from the summary of this invention, it can change and implement variously.

  For example, in the embodiment, the example in which there are four connection terminals of the semiconductor chip is shown, but there may be a plurality other than four, and some of the plurality of dummy terminals are not connected to the semiconductor element. It can be a connection terminal.

  In the embodiment, the lead terminal of the semiconductor device is formed by being bent in a staircase shape or a gull wing shape. However, the step with the internal lead can be formed by etching. By using internal leads and lead terminals by etching, the semiconductor device can be made smaller.

  In the embodiment, an example in which the semiconductor device is mounted on the internal lead has been shown. However, the portion constituting the height from the bottom surface corresponding to the height difference between the internal lead and the lead terminal is the height of the semiconductor chip. It is possible to fix the semiconductor chip to the bottom surface side of the internal lead by increasing the height so that the distance is within the range. In this deformed configuration, the upper and lower sides of the semiconductor chip are inverted.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A semiconductor substrate having a top surface, a bottom surface facing the top surface, and a side surface connecting the top surface and the bottom surface, and an upper wiring on the top surface and connected to a semiconductor element formed on the semiconductor substrate And a plurality of connection terminals disposed on the bottom surface and spaced apart from the side surface on the inner side surrounded by the side surface, passing through the semiconductor substrate and passing through the upper wiring and the connection terminal. A semiconductor chip comprising: a through wiring for electrical connection; and an insulating separation film located on the bottom surface between the connection terminals and disposed at a distance from the connection terminal.

(Supplementary note 2) The semiconductor chip according to supplementary note 1, wherein a surface of the separation membrane is substantially flush with a surface of the connection terminal.

(Supplementary note 3) The semiconductor chip according to supplementary note 1, wherein the connection terminals are connected to each other by a conductive material on the bottom surface.

(Supplementary Note 4) The semiconductor chip according to Supplementary Note 1, wherein the upper wiring is covered with a protective film.

(Additional remark 5) The said semiconductor element is a semiconductor chip of Additional remark 1 currently formed in the said upper surface of the said semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows typically the structure of the semiconductor chip based on Example 1 of this invention, FIG.1 (a) is the top view seen from the bottom face direction, FIG.1 (b) is the AA line | wire of FIG.1 (a). FIG. FIGS. 2A and 2B are diagrams schematically showing mounting of a semiconductor chip according to a first embodiment of the present invention on a wiring board, FIG. 2A is a cross-sectional view of the wiring board, and FIG. 2B is a semiconductor chip fixed to the wiring board. FIG. FIGS. 3A and 3B are diagrams schematically illustrating a configuration of a semiconductor chip according to a first modification of the first embodiment of the present invention, in which FIG. 3A is a plan view viewed from the bottom surface, and FIG. Sectional drawing along a BB line. FIG. 4A is a diagram schematically illustrating a configuration of a semiconductor chip according to a second modification of the first embodiment of the present invention, FIG. 4A is a plan view viewed from the bottom surface, and FIG. 4B is a diagram of FIG. Sectional drawing along CC line. 5A and 5B are diagrams schematically illustrating a configuration of a semiconductor device according to a second embodiment of the present invention, in which FIG. 5A is a plan view seen from the bottom surface, and FIG. 5B is a DD line in FIG. FIG.

Explanation of symbols

1, 2, 3 Semiconductor chip 11 Semiconductor substrate 13 Side surface 15 Upper wiring 17 Protective film 21 Through hole 23 Insulating film 25 Through wiring 25a Through wiring films 26, 56, 56a, 56b, 56c, 57, 57a, 57b, 57c Connection terminal 27 Separation membrane 31 Recess 41 Wiring substrate 43 Substrate wiring 45 Solder resist 51, 71 Solder 61 Heat radiation hole 73 Internal lead 75 Lead terminal 81 Sealing resin

Claims (5)

A semiconductor substrate having a top surface, a bottom surface facing the top surface, and a side surface connecting the top surface and the bottom surface;
An upper wiring on the upper surface and connected to a semiconductor element formed on the semiconductor substrate;
A plurality of connection terminals located on the bottom surface and spaced apart from the side surface;
A through-wiring that electrically connects the upper wiring and the connection terminal through a through-hole penetrating the semiconductor substrate;
An insulating separation film on the bottom surface, spaced apart from the connection terminal and forming a recess with the connection terminal;
A semiconductor chip comprising:   A hole that reaches the vicinity of the semiconductor element from the bottom surface, a conductive material that is disposed inside the side surface and spaced apart from the side surface, is formed in the hole portion, and is connected to the connection terminal; The semiconductor chip according to claim 1, further comprising:   The semiconductor chip according to claim 1, wherein the through hole is formed in a peripheral portion of the semiconductor substrate.   The semiconductor chip according to claim 1, wherein the through hole is closed by the upper wiring on the upper surface side. A semiconductor chip according to any one of claims 1 to 4,
An internal lead connected to the connection terminal of the semiconductor chip, and a lead terminal connected to the internal lead;
A sealing resin for sealing the semiconductor chip, the internal leads, and the lead terminals so that the lead terminals are exposed on the surface to be mounted on the wiring board;
A semiconductor device comprising:

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