JP7165694B2 - semiconductor chip - Google Patents

Description

The present invention relates to a semiconductor device and its manufacturing technology, and more particularly to a technology effectively applied to a semiconductor device having pads and its manufacturing technology.

Japanese Patent Application Laid-Open No. 8-241909 (Patent Document 1) discloses that the surface protection film covering the side near the edge of the semiconductor chip among the plurality of sides constituting the pad covers the surface protection film covering the other sides. Techniques have been described for greater than membrane coverage.

JP-A-8-241909

For example, in a pad formed on a semiconductor chip, most of the surface of the pad is exposed through an opening provided in the surface protective film, while the edge of the pad is covered with the surface protective film. . That is, the surface protective film is formed at the end of the pad so as to cover the step due to the thickness of the pad.

Here, for example, cracks may occur in the surface protective film that covers the steps formed at the ends of the pads due to stress applied during dicing of the semiconductor chip and stress applied from the sealing body that seals the semiconductor chip. may occur. Therefore, in the current semiconductor device, there is room for improvement from the viewpoint of improving the reliability of the semiconductor device by suppressing the occurrence of cracks in the surface protective film covering the step formed at the end of the pad.

Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

A semiconductor device according to one embodiment includes a rectangular semiconductor chip, the semiconductor chip comprising:
It has an inclined portion provided at a connecting portion between each of the plurality of pads and the lead-out wiring portion.

According to one embodiment, reliability of a semiconductor device can be improved.

1 is a top plan view of a semiconductor device made up of a QFP package; FIG. FIG. 2 is a cross-sectional view taken along line AA of FIG. 1; 2 is a diagram showing a layout configuration of a semiconductor chip; FIG. FIG. 3 is an enlarged view of a region near a pad formed on a semiconductor chip; It is a figure which shows the deformation|transformation of a pad typically. 2 is an enlarged plan view showing a part of the semiconductor chip according to the first embodiment; FIG. FIG. 4 is an enlarged view showing a portion of a pad that is not provided with an inclined portion, which is a feature of Embodiment 1; FIG. 2 is an enlarged view showing a part of a pad provided with an inclined portion, which is a feature of Embodiment 1; FIG. 7 is a cross-sectional view taken along line AA of FIG. 6; It is a figure which shows typically the structure between several pads in related technology. FIG. 4 is a diagram schematically showing a configuration between a plurality of pads according to Embodiment 1; FIG. FIG. 7 is a schematic cross-sectional view taken along line BB of FIG. 6; FIG. 11 is a plan view showing an enlarged part of the semiconductor chip in the modification of the first embodiment; 2 is a plan view showing a layout configuration of a semiconductor wafer; FIG. FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device in Embodiment 1; 16A is a plan view, and FIG. 16B is a cross-sectional view taken along line AA of FIG. 16A, showing the manufacturing process of the semiconductor device following FIG. 15; 17A is a plan view and FIG. 17B is a cross-sectional view taken along the line AA of FIG. 17A, showing the manufacturing process of the semiconductor device following FIG. 16. FIG. 18A is a plan view and FIG. 18B is a cross-sectional view taken along the line AA of FIG. 18A, showing the manufacturing process of the semiconductor device following FIG. 17; 19(a) is a plan view and FIG. 19(b) is a cross-sectional view taken along the line AA of FIG. 19(a), showing the manufacturing process of the semiconductor device following FIG. 18; FIG. 10 is a view after forming the pads, and is a schematic cross-sectional view showing the vicinity of the boundary region of the edge (the boundary line at this stage). 4 is a flow chart showing a flow of processes for manufacturing a semiconductor device, for example, a QFP package after forming an integrated circuit on a semiconductor wafer. FIG. 11 is a plan view showing an enlarged part of a semiconductor chip according to a second embodiment; FIG. 11 is a plan view showing an enlarged part of a semiconductor chip in accordance with a third embodiment; FIG. 11 is a plan view showing an enlarged part of a semiconductor chip in Modification 1 of Embodiment 3; FIG. 11 is a plan view showing an enlarged part of a semiconductor chip in Modification 2 of Embodiment 3; FIG. 11 is a plan view showing an enlarged part of a semiconductor chip in accordance with a fourth embodiment; FIG. 21 is a plan view showing an enlarged part of a semiconductor chip in a modification of the fourth embodiment; FIG. 11 is a plan view showing a schematic configuration of a pad according to Embodiment 5; FIG. 21 is a plan view showing a schematic configuration of a pad in a modified example of Embodiment 5; FIG. 21 is a plan view showing an enlarged part of a semiconductor chip in accordance with a sixth embodiment; FIG. 21 is a plan view showing an enlarged part of a pad according to Embodiment 7; FIG. 21 is a cross-sectional view showing a portion between pads in Embodiment 7;

For the sake of convenience, the following embodiments are divided into a plurality of sections or embodiments when necessary, but unless otherwise specified, they are not independent of each other, and one There is a relationship of part or all of the modification, details, supplementary explanation, etc.

In addition, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), when it is particularly specified, when it is clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Needless to say.

Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., unless otherwise explicitly stated or in principle clearly considered to be otherwise, It shall include those that approximate or resemble the shape, etc. This also applies to the above numerical values and ranges.

In addition, in all the drawings for explaining the embodiments, the same members are basically given the same reference numerals, and repeated description thereof will be omitted. In order to make the drawing easier to understand, even a plan view may be hatched.

(Embodiment 1)
<Structure example of semiconductor device (QFP package)>
There are various types of package structures for semiconductor devices, such as BGA (Ball Grid Array) packages and QFP (Quad Flat Package) packages. The technical idea of the first embodiment can be applied to these packages, and the configuration of a semiconductor device made up of a QFP package will be described below as an example.

FIG. 1 is a top plan view of a semiconductor device SA1 made up of a QFP package. As shown in FIG. 1, the semiconductor device SA1 has a rectangular shape, and the upper surface of the semiconductor device SA1 is covered with a resin (sealing body) MR. Outer leads OL protrude outward from four sides defining the outer shape of the resin MR.

Next, the internal structure of the semiconductor device SA1 will be described. FIG. 2 is a cross-sectional view cut along line AA in FIG. As shown in FIG. 2, the rear surface of the chip mounting portion TAB is covered with a resin MR. On the other hand, a semiconductor chip CHP is mounted on the upper surface of the chip mounting portion TAB, and the chip mounting portion TAB is separated from the inner leads IL1 (lead terminals). A pad PD is formed on the main surface of the semiconductor chip CHP. The pads PD formed on the semiconductor chip CHP are electrically connected to the inner leads IL1 by wires W. As shown in FIG. These semiconductor chip CHP, wires W and inner leads IL1 are covered with a resin MR, and outer leads OL (lead terminals) integrated with the inner leads IL1 protrude from the resin MR. The outer lead OL protruding from the resin MR is molded in a gull-wing shape, and a plated film PF is formed on the surface thereof.

The chip mounting portion TAB, the inner leads IL1, and the outer leads OL are made of, for example, a copper material or 42 alloy (42 alloy) that is an alloy of iron and nickel, and the wire W is made of, for example, a gold wire. formed. The semiconductor chip CHP is made of, for example, silicon or a compound semiconductor (such as GaAs), and a plurality of semiconductor elements such as MOSFETs are formed in the semiconductor chip CHP. A multilayer wiring is formed above the semiconductor element with an interlayer insulating film interposed therebetween, and a pad PD connected to the multilayer wiring is formed in the uppermost layer of the multilayer wiring. Therefore, the semiconductor element formed in the semiconductor chip CHP is electrically connected to the pad PD via the multilayer wiring. In other words, an integrated circuit is formed by the semiconductor element formed in the semiconductor chip CHP and the multilayer wiring, and the pad PD functions as a terminal for connecting the integrated circuit and the outside of the semiconductor chip CHP. The pad PD is connected to the inner lead IL1 by a wire W, and connected to the outer lead OL integrally formed with the inner lead IL1. Therefore, the integrated circuit formed in the semiconductor chip CHP can be electrically connected to the outside of the semiconductor device SA1 through the path of pad PD→wire W→inner lead IL1→outer lead OL→external connection device. I know you can. That is, it can be seen that the integrated circuit formed in the semiconductor chip CHP can be controlled by inputting an electric signal from the outer lead OL formed in the semiconductor device SA1. Also, it can be seen that the output signal from the integrated circuit can be taken out from the outer lead OL.

Next, FIG. 3 is a diagram showing the layout configuration of the semiconductor chip CHP. In FIG. 3, the semiconductor chip CHP has, for example, a rectangular shape, and a plurality of pads PD are arranged along the edge ES of the semiconductor chip CHP. Specifically, as shown in FIG. 3, along the edge ES of the rectangular semiconductor chip CHP, a seal ring SRG is formed inside the edge ES. A plurality of pads PD are arranged along the edge ES of the semiconductor chip CHP. In each of the plurality of pads PD, although not shown in FIG. 3, most of the surface of the pad PD is exposed through an opening provided in the surface protective film, while the edge of the pad PD is , covered with a surface protective film.

Here, for example, due to stress applied during dicing for singulating the semiconductor chip CHP, stress applied from the resin (sealing body) that seals the semiconductor chip CHP, and the like, the surface protective film covering the end portion of the pad PD cracks. may occur. Therefore, in the current resin-encapsulated semiconductor device, there is room for improvement from the viewpoint of improving the reliability of the semiconductor device by suppressing the occurrence of cracks in the surface protective film covering the step formed at the end of the pad PD. exists.

<Room for improvement>
FIG. 4 is an enlarged view of a region near pads PD formed on a semiconductor chip. As shown in FIG. 4, a seal ring SRG is formed inside the edge ES of the semiconductor chip, and a pad PD is formed inside the seal ring SRG. The pad PD has a rectangular shape, and a lead-out wiring portion DWU is formed integrally with the pad PD. The lead-out wiring unit DWU has a function of connecting the pad PD and a wiring (not shown) formed under the pad PD. A surface protective film PAS is formed to cover the pad PD, and an opening OP is formed in the surface protective film PAS to expose part of the surface region of the pad PD. That is, most of the surface region of the pad PD is exposed from the opening OP provided in the surface protective film PAS, while the end region including the end of the pad PD is covered with the surface protective film PAS. there is

In this specification, the edge region of the pad PD covered with the surface protective film PAS is defined as a covered region, and dots are attached to this covered region in FIG. 4, for example. Furthermore, in FIG. 4, a portion of the surface protective film PAS covering the outside of the step due to the edge of the pad PD is also dotted. That is, the surface protective film PAS is formed over the base on which the pads PD are formed. For example, in FIG. A portion of the surface protective film PAS formed in the vicinity of the outside of the step due to the edge of the pad PD is dotted.

Here, for example, a temperature cycle test or the like causes expansion and contraction of the resin that seals the semiconductor chip, and as shown in FIG. can be considered. That is, as indicated by the arrows in FIG. 5, it is conceivable that the stress from the resin sealing the semiconductor chip is applied from the end side ES side of the semiconductor chip. In this case, the stress from the resin that seals the semiconductor chip deforms the covered area of the pad PD covered with the surface protective film PAS, causing "aluminum slide" in which a portion of the pad PD is displaced. There is an increased possibility that cracks CLK will occur in part of the covered area of the pad PD covered with the film PAS.

As a result of investigations on this point, the present inventors have found that the following three factors are conceivable as factors for the occurrence of "aluminum slide" and cracks CLK. That is, the first factor is that, as shown in FIG. 5, a crack CLK is likely to occur in the surface protective film PAS at the connecting portion due to the fact that the connecting portion between the pad PD and the lead-out wiring portion DWU is at right angles. It is said that it will be. The first factor is that, for example, when the connection portion between the pad PD and the lead-out wiring portion DWU is at right angles, the discontinuous region (seam region) of the surface protective film PAS covering this connection portion concentrates in one place. It can be considered that the stress concentrates on the discontinuous region with low stress resistance, and the crack CLK occurs in the surface protective film PAS at the connection portion.

The second factor is that cracks CLK are likely to occur in the surface protective film PAS due to the small width of the area covered by the surface protective film PAS of the pad PD. The second factor is that the smaller the width of the covered region of the pad PD covered with the surface protective film PAS, the lower the stress resistance than the larger the width of the covered region of the pad PD covered with the surface protective film PAS. It is considered to be.

Next, the third factor is the length of a line segment (part of one side of the pad PD) in a direction perpendicular to the width of the covering region of the pad PD covered with the surface protective film PAS. Due to the lengthening of the length, the “aluminum slide” in which a part of the pad PD is displaced and the crack CLK in the surface protective film PAS are likely to occur. The third factor is that the longer the length of the line segment in the direction perpendicular to the width of the covered area, the more easily the line segment bends due to the stress from the direction perpendicular to the line segment, and the greater the deformation of this line segment. can be understood from

Therefore, in this specification, focusing on the above-described first to third factors, technical ideas for suppressing the occurrence of "aluminum slide" and cracks CLK will be described. In particular, in the first embodiment, the crack CLK is generated in the surface protective film PAS at the connection portion due to the fact that the connection portion between the pad PD and the lead-out wiring portion DWU is at a right angle. The technical idea applied is explained.

<Configuration of semiconductor chip>
FIG. 6 is a plan view showing an enlarged part of the semiconductor chip CHP in the first embodiment. In FIG. 6, the semiconductor chip CHP has, for example, a rectangular shape having a plurality of edges ES, and corners CNR are formed by edges ES that cross each other. A seal ring SRG that prevents foreign matter from entering the interior of the semiconductor chip CHP is formed inside the edge of the semiconductor chip CHP. A plurality of pads PD whose main component is aluminum are arranged along the . Each of the plurality of pads PD has, for example, a rectangular shape represented by a rectangular shape, and most of the surface of each of the plurality of pads PD is provided on the surface protection film PAS While exposed from the opening OP, the end of the pad PD is covered with a surface protection film. A lead-out wiring portion DWU is provided integrally with each of the plurality of pads PD, and the lead-out wiring portion DWU is covered with a surface protection film PAS. In FIG. 6, the seal ring SRG is formed inside the edge ES of the semiconductor chip CHP. In some cases, a dummy pattern is provided to suppress the progress of the ions into the semiconductor chip CHP (within the chip region). At this time, the dummy pattern is not necessarily required, but it is desirable to provide the dummy pattern in order to prevent cracks during dicing and to improve flatness in the CMP process performed when forming each wiring layer.

In this specification, the term “main component” refers to a material component that is the most contained among constituent materials constituting a member (layer or film). ” means that the material of the pad PD contains the largest amount of aluminum (Al). The purpose of using the term “main component” in this specification is to express that, for example, the pad PD is basically made of aluminum, but does not exclude the case where other impurities are included. are using.

For example, focusing on a pad PD generally used in a semiconductor device, this pad PD normally has a structure in which an aluminum film is sandwiched between barrier conductor films made of titanium/titanium nitride films. That is, the pad PD is composed of a first barrier conductor film, an aluminum film formed on the first barrier conductor film, and a second barrier conductor film formed on the aluminum film. In this case, when the pad PD is composed of a laminated film including the first barrier conductor film, the aluminum film, and the second barrier conductor film, the aluminum film occupies most of the pad PD. is the main component.

Further, the aluminum film referred to in this specification includes not only a pure aluminum film but also an aluminum alloy film (AlSi film) in which silicon is added to aluminum, and an aluminum alloy film in which silicon and copper are added to aluminum. It is used in a broad concept including a film (AlSiCu film). Therefore, the pads PD containing these aluminum alloy films are also included in the "pads PD containing aluminum as the main component". In other words, the term "pad PD containing aluminum as a main component" used in this specification includes a pad PD including an aluminum film and a barrier conductor film, and a pad PD in which the aluminum film itself is an aluminum alloy film. will also be used.

<Features of the embodiment>
Next, feature points in the first embodiment will be described. In FIG. 6, a characteristic point of the first embodiment is that a sloped portion SLP as a reinforcing pattern is provided at a connecting portion between the pad PD and the lead-out wiring portion DWU. Thus, according to the first embodiment, it is possible to suppress the occurrence of cracks CLK in the covered region where a portion of pad PD is covered with surface protective film PAS. The reason for this will be described below with reference to the drawings.

FIG. 7 is an enlarged view showing a part of the pad PD where the inclined portion SLP, which is a feature of the first embodiment, is not provided. In FIG. 7, the pad PD and the lead-out wiring portion DWU are integrally connected, and the inclined portion SLP is not provided at the connection portion between the pad PD and the lead-out wiring portion DWU. That is, in FIG. 7, the connection angle of the connection portion between the pad PD and the lead-out wiring portion DWU is vertical (right angle). Therefore, as shown in FIG. 7, a discontinuous region SM (seam region) indicated by a dotted line during film formation is concentrated in one place in the surface protective film PAS covering the connecting portion between the pad PD and the lead-out wiring portion DWU. formed by As a result, in the pad PD shown in FIG. 7, the stress concentrates on the discontinuous region SM with low stress resistance, and cracks are likely to occur in the surface protective film PAS at the connecting portion between the pad PD and the lead-out wiring portion DWU. Become.

On the other hand, FIG. 8 is an enlarged view showing a part of the pad PD provided with the inclined portion SLP as a reinforcement pattern that is a feature of the first embodiment. In FIG. 8, the pad PD and the lead-out wiring portion DWU are integrally connected, and a sloped portion SLP is provided at the connection portion between the pad PD and the lead-out wiring portion DWU. At this time, the shape of the inclined portion SLP is, for example, a right-angled triangular shape. As a result, in FIG. 8, the connection angle of the connection portion between the pad PD and the lead-out wiring portion DWU is an obtuse angle larger than 90 degrees.

In this case, since the pad PD shown in FIG. 7 does not have the inclined portion SLP, the connection angle of the connection portion between the pad PD and the lead wiring portion DWU is composed of one right angle. On the other hand, in the pad PD shown in FIG. 8, due to the presence of the inclined portion SLP, the connection angle of the connection portion between the pad PD and the lead-out wiring portion DWU is composed of two obtuse angles. This means that one discontinuous region SM is formed corresponding to one right angle in the pad PD shown in FIG. 7, whereas two obtuse angles are formed in the pad PD shown in FIG. This means that two discontinuous regions SM1 and SM2 are formed corresponding to . That is, in the pad PD shown in FIG. 7, the surface protective film PAS covering the connecting portion between the pad PD and the lead-out wiring portion DWU has one discontinuous region SM (seam region) during film formation indicated by a dotted line. Formed in a concentrated manner. On the other hand, in the pad PD shown in FIG. 8, the surface protective film PAS covering the connecting portion between the pad PD and the lead-out wiring portion DWU has two discontinuous regions SM1 and SM2 at the time of film formation indicated by dotted lines. It will be formed in a distributed manner. As a result, in the pad PD according to the first embodiment having the inclined portion SLP, there are two discontinuous regions SM1 and SM2 with low stress resistance. can be suppressed from concentrating on In other words, in the pad PD according to the first embodiment having the sloped portion SLP, the discontinuous region SM1 and the discontinuous region SM2 with low stress resistance are present at two locations. area SM2. As a result, according to the first embodiment, since the stress is dispersed in the two discontinuous regions SM1 and SM2, the stress applied to each of the discontinuous regions SM1 and SM2 is reduced. be able to. Therefore, according to the first embodiment, by providing the inclined portion SLP at the connection portion between the pad PD and the lead-out wiring portion DWU, cracks are generated in the surface protective film PAS at the connection portion between the pad PD and the lead-out wiring portion DWU. It is possible to effectively suppress what occurs. Therefore, according to the semiconductor device of the first embodiment, it is possible to suppress deterioration in reliability due to cracks occurring in the surface protective film PAS. In other words, according to the first embodiment, reliability of the semiconductor device can be improved.

In particular, in the first embodiment, the width (the width in the X direction) of the lead-out wiring portion DWU is greater than the length of the side to which the lead-out wiring portion DWU is connected, among the plurality of sides forming each of the plurality of pads PD. is also shortened, and the inclined portions SLP are provided on both sides of the lead-out wiring portion DWU. For this reason, according to the present embodiment, by providing the inclined portions SLP on both sides of the connecting portion between the pad PD and the lead-out wiring portion DWU, surface protection is provided on both sides of the connecting portion between the pad PD and the lead-out wiring portion DWU. It is possible to effectively suppress the occurrence of cracks in the film PAS.

Here, for example, the pad PD, the lead-out wiring portion DWU, and the inclined portion SLP are integrally formed from a film containing aluminum as a main component. Then, as shown in FIG. 6, the lead wiring portion DWU is connected to the side furthest from the edge side ES of the semiconductor chip CHP among the plurality of sides forming each of the plurality of pads PD.

This is because, of the plurality of sides forming each of the plurality of pads PD, the side furthest from the edge side ES of the semiconductor chip CHP is the closest to the integrated circuit region formed inside the semiconductor chip CHP. By providing the lead-out wiring part DWU on the farthest side from the end side ES of the CHP, it is possible to shorten the connection distance between the integrated circuit formed in the integrated circuit region and the lead-out wiring part DWU. . That is, by providing the lead wiring portion DWU on the farthest side from the edge side ES of the semiconductor chip CHP, it is possible to reduce the parasitic resistance of the wiring that connects the integrated circuit and the lead wiring portion DWU. Device performance can be improved.

Furthermore, in the configuration shown in FIG. 6 in which the lead wiring portion DWU is provided on the farthest side from the edge side ES of the semiconductor chip CHP, cracks occur in the surface protective film PAS at the connecting portion between the pad PD and the lead wiring portion DWU. It can be said that the configuration is desirable also from the viewpoint of suppressing this. This is because, according to the study of the present inventor, for example, in FIG. This is because they tend to be large. That is, in FIG. 6, when the lead wiring portion DWU is provided on the side closest to the edge ES of the semiconductor chip CHP among the plurality of sides forming the pad PD, A connection portion between the pad PD and the lead-out wiring portion DWU, where cracks are likely to occur, is provided on the side, and it is thought that cracks are likely to occur in the surface protective film PAS at the connection portion between the pad PD and the lead-out wiring portion DWU. because it will be

In the semiconductor device according to the first embodiment, even when the lead-out wiring portion DWU is provided on the farthest side from the end side ES, the possibility of crack generation is minimized. That is, by providing the inclined portion SLP at the connection portion between the pad PD and the lead-out wiring portion DWU (first configuration), the stress is dispersed in the two discontinuous regions SM1 and SM2 shown in FIG. As a result, the stress applied to each of the discontinuous regions SM1 and SM2 can be reduced (stress reduction effect by the first configuration). At the same time, in the semiconductor device according to the first embodiment, by providing the lead wiring portion DWU on the farthest side from the edge side ES of the semiconductor chip CHP (second configuration), the connection between the pad PD and the lead wiring portion DWU is achieved. It is possible to reduce the magnitude of the stress applied to the connection portion (stress reduction effect by the second configuration).

As described above, in the semiconductor device according to the first embodiment, due to the synergistic effect of the first configuration and the second configuration described above, cracks occur in the surface protective film PAS at the connection portion between the pad PD and the lead wiring portion DWU. can be effectively suppressed.

Furthermore, according to the first embodiment, with the second configuration described above, the connection distance between the integrated circuit formed in the inner region of the semiconductor chip CHP and the lead wiring unit DWU can be shortened. It is also possible to obtain the advantage of being able to reduce the parasitic resistance of the wiring that connects the circuit and the lead wiring unit DWU.

As described above, according to the first embodiment, it is possible to obtain a remarkable effect that the reliability can be improved while improving the performance of the semiconductor device.

Next, FIG. 9 is a cross-sectional view taken along line AA of FIG. As shown in FIG. 9, a field effect transistor Q, which is an example of a semiconductor element, is formed on a semiconductor substrate 1S made of, for example, silicon. A fine layer FL is formed. A global layer GL made of copper wiring having a width larger than that of the copper wiring forming the fine layer FL is formed above the fine layer FL. A plurality of pads PD are formed on the global layer GL. The pads PD and the global layers GL are connected to the lead wiring portions DWU shown in FIG. 7 and the like through contact holes. Then, as shown in FIG. 9, the pad PD is electrically connected to the field effect transistor Q formed on the semiconductor substrate 1S via the global layer GL and the fine layer FL.

Subsequently, a surface protective film PAS is formed so as to cover the pads PD and to fill the gaps between the pads PD. An opening OP is formed in the surface protective film PAS, and a part of the surface of the pad PD is exposed from the bottom of the opening OP. A wire W made of, for example, a gold wire is connected to the surface of the pad PD exposed from the opening OP. It is covered with resin MR.

Here, one of the characteristic points in Embodiment 1 will be described with reference to FIGS. 10 and 11. FIG. FIG. 10 is a diagram schematically showing the configuration between a plurality of pads PD in related art, and FIG. 11 is a diagram schematically showing the configuration between a plurality of pads PD in the first embodiment. First, as shown in FIG. 10, a surface protective film PAS is formed in the gap between the pads PD. It is composed of a silicon nitride film SNF formed by a method. At this time, the film thickness of the pad PD is formed to be 1000 to 2000 nm, for example, about 1600 nm. The thickness of the silicon oxide film OXF1 is approximately 200 nm, and the thickness of the silicon nitride film SNF is approximately 600 nm. Therefore, the film thickness of the pad PD is greater than the sum of the film thickness of the silicon oxide film OXF1 and the film thickness of the silicon nitride film SNF (1600 nm>200 nm+600 nm=800 nm). Therefore, as shown in FIG. 10, the gaps between the pads PD are not completely filled with the surface protective film PAS made up of the silicon oxide film OXF1 and the silicon nitride film SNF. As a result, for example, when the resin (not shown) covering the pads PD expands and contracts due to temperature changes in the temperature cycle test, the pads PD tend to move laterally (horizontally). This is because the pad PD shown in the related art shown in FIG. This means that cracks are likely to occur in the surface protective film PAS due to a synergistic factor of the fact that a large stress is likely to be applied to the PAS and the thin film thickness of the surface protective film PAS. In other words, it can be said that the configuration of the pad PD and the surface protective film PAS shown in FIG. 10 has room for improvement from the viewpoint of suppressing the occurrence of "aluminum slide" and the occurrence of cracks.

Incidentally, in the first embodiment, the film thickness of the pad PD is made considerably thick as described above. This is mainly for the purpose of lowering the resistance when the wiring in the same layer as the pad PD is routed, and for alleviating the stress caused by probe contact under the pad PD during inspection using a probe. There is. However, as the volume of aluminum increases, the above-mentioned "aluminum slide" becomes more likely to occur.

In contrast, in Embodiment 1, as shown in FIG. 11, the surface protective film PAS is formed so as to completely fill the gaps between the pads PD. Specifically, the surface protective film PAS is made of a silicon oxide film OXF1 formed by plasma CVD, a silicon oxide film OXF2 formed by high density plasma CVD (HDP), and TEOS as raw materials. It is composed of a silicon oxide film OXF3 formed by plasma CVD and a silicon nitride film SNF formed by CVD.

At this time, the film thickness of the pad PD is 1000 to 2000 nm, for example, about 1700 nm, and the film thickness of the silicon oxide film OXF1 is about 200 nm. The thickness of the silicon oxide film OXF2 is approximately 900 nm, and the thickness of the silicon oxide film OXF3 is approximately 800 nm. Furthermore, the film thickness of the silicon nitride film SNF is, for example, about 600 nm. Therefore, the thickness of the pad PD is smaller than the sum of the thickness of the silicon oxide film OXF1, the thickness of the silicon oxide film OXF2, the silicon oxide film OXF3, and the silicon nitride film SNF (1700 nm<200 nm+900 nm+800 nm+600 nm= 2500 nm). Therefore, as shown in FIG. 11, the gaps between the pads PD are completely filled with the surface protective film PAS composed of the silicon oxide film OXF1, the silicon oxide film OXF2, the silicon oxide film OXF3, and the silicon nitride film SNF. Become. As a result, for example, even if the resin (not shown) covering the pad PD expands and contracts due to temperature changes in the temperature cycle test, the pad PD is firmly fixed by the surface protective film PAS that fills the gap. , the pad PD becomes difficult to move laterally (horizontally). This is because in the pad PD shown in the first embodiment shown in FIG. 11, the "aluminum slide" caused by the temperature change is less likely to occur, and the stress acting on the surface protective film PAS caused by the "aluminum slide" is reduced. means that it will also be relaxed. Therefore, according to the first embodiment, the feature that the thickness of the surface protective film PAS is thick enough to completely fill the gaps between the pads PD causes "aluminum slide" of the pads PD. In addition, cracks are less likely to occur in the surface protective film PAS. In other words, the configuration of the pad PD and the surface protection film PAS in the first embodiment as shown in FIG. 11 is superior from the viewpoint of suppressing the occurrence of "aluminum slide" and the occurrence of cracks.

As described above, one of the features of the first embodiment is that the surface protective film PAS is formed so as to completely fill the gaps between the pads PD. According to the method, it is possible to effectively suppress the occurrence of "aluminum slide" and the occurrence of cracks, thereby improving the reliability of the semiconductor device.

Next, FIG. 12 is a schematic cross-sectional view taken along line BB of FIG. As shown in FIG. 12, a seal ring region SRR is provided inside the edge ES of the semiconductor chip CHP, and a seal ring SRG is formed in the seal ring region SRR. Further, the inner region of the seal ring region SRR is an integrated circuit region ICR, and in this integrated circuit region ICR, a pad PD and a lead-out wiring portion DWU formed integrally with the pad PD are formed. At this time, in the first embodiment, no dummy region is provided outside the seal ring SRG. may

The seal ring SRG disclosed in this embodiment is formed by connecting multiple wiring layers, and is connected to the semiconductor substrate 1S. Although not shown in detail, it is connected to a well formed in the semiconductor substrate 1S and has a fixed potential such as a ground potential. On the other hand, the dummy pattern can be formed of multiple wiring layers like the seal ring SRG. The wiring layers may be connected or separated. Unlike the seal ring SRG, this dummy pattern is often not connected to a fixed potential and is in a floating state.

Further, as shown in FIG. 12, a surface protective film PAS is formed to cover the integrally formed pad PD1 and lead-out wiring portion DWU. An opening OP is formed in the surface protective film PAS, and a part of the surface of the pad PD is exposed from the bottom of the opening OP. Covered with PAS. The surface protective film PAS covers the seal ring region SRR formed outside the integrated circuit region ICR and extends to the edge ES of the semiconductor chip CHP.

In FIG. 12, the pad PD formed in the integrated circuit region ICR and the wiring structure and device structure formed in the lower layer of the lead-out wiring portion DWU are basically the same as those in FIG. there is In addition, in FIG. 12, the wires connected to the pads PD and the resin covering the surface protection film PAS are also omitted.

<Modification>
The semiconductor device according to the first embodiment is configured as described above, and a modification of the first embodiment will be described below.

FIG. 13 is a plan view showing an enlarged part of the semiconductor chip CHP in this modification. In FIG. 13, the characteristic point of this modification is that the lead wiring portion DWU is connected to the side closest to the edge side ES of the semiconductor chip CHP among the plurality of sides forming each of the plurality of pads PD. In addition, a sloped portion SLP is provided at the connecting portion between the lead-out wiring portion DWU and the pad PD. Thus, according to this modification, as in the first embodiment, it is possible to effectively suppress the occurrence of cracks in the surface protective film PAS at the connection portion between the pad PD and the lead wiring portion DWU.

For example, according to the study of the present inventor, the stress applied to the covering region covering the side closest to the edge ES of the semiconductor chip CHP among the plurality of sides forming the pad PD tends to be relatively large. That is, as shown in FIG. 13, when the lead wiring portion DWU is provided on the side closest to the edge ES of the semiconductor chip CHP among the plurality of sides forming the pad PD, the edge ES of the semiconductor chip CHP A connection portion between the pad PD and the lead-out wiring portion DWU, where cracks are likely to occur, is provided on the side closest to . In this case, cracks are likely to occur in the surface protective film PAS at the connection portion between the pad PD and the lead-out wiring portion DWU. From the viewpoint of suppressing the occurrence of cracks, it can be considered that the configuration in which the lead-out wiring portion DWU is provided on the side closest to the edge side ES is difficult to adopt.

However, in this modification, as a result of providing the inclined portion SLP at the connection portion between the lead-out wiring portion DWU and the pad PD, the side closest to the edge side ES of the semiconductor chip CHP among the plurality of sides forming the pad PD Even if the lead-out wiring portion DWU is provided in the lead-out wiring portion DWU, it is possible to suppress cracks that are likely to occur at the connecting portion between the pad PD and the lead-out wire portion DWU. That is, in this modified example, the configuration in which the inclined portion SLP is provided at the connection portion between the lead wiring portion DWU and the pad PD suppresses the occurrence of cracks at the connection portion between the pad PD and the lead wiring portion DWU. A configuration in which the lead-out wiring portion DWU is provided on the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides constituting the semiconductor chip CHP is also allowed. In other words, in this modified example, from the viewpoint of preventing cracks, the technique of providing the inclined portion SLP at the connection portion between the lead-out wiring portion DWU and the pad PD even if the lead-out wiring portion DWU is not originally arranged. It is possible by adopting the concept of

As a result, according to this modified example, it is possible to improve the degree of freedom in arranging the lead-out wiring part DWU while suppressing the occurrence of cracks at the connecting portion between the lead-out wiring part DWU and the pad PD. In other words, according to this modification, the degree of freedom in the layout position of the lead wiring portion DWU formed integrally with the pad PD can be improved, and as a result, the degree of freedom in the layout arrangement of the entire semiconductor chip CHP can also be improved. This means that, according to this modification, it is possible to design a novel layout arrangement that is not bound by conventional restrictions, thereby improving the degree of freedom in designing the semiconductor device.

<Method for manufacturing a semiconductor device>
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings. FIG. 14 is a plan view showing the layout configuration of the semiconductor wafer WF. As shown in FIG. 14, the semiconductor wafer WF has a substantially disc shape and has a plurality of chip regions CR in the inner region. Semiconductor elements represented by field effect transistors and multilayer wiring layers are formed in each of the plurality of chip regions CR, and the plurality of chip regions CR are partitioned by scribe regions SCR. In the first embodiment, as shown in FIG. 14, a semiconductor wafer (semiconductor substrate) WF having rectangular chip regions CR and scribe regions SCR that define the chip regions CR is prepared. At this stage, semiconductor elements typified by field effect transistors are formed in each of the plurality of chip regions CR of the semiconductor wafer WF. layers are formed. In the following steps, a step of forming pads on the uppermost layer of the multilayer wiring layer in each of the plurality of chip regions CR will be described.

First, as shown in FIG. 15, a barrier conductor film BCF1, an aluminum film AF formed over the barrier conductor film BCF1, and a barrier conductor film BCF2 formed over the aluminum film AF are formed over the interlayer insulating film IL. A laminated film is formed. The barrier conductor film BCF1 is formed of, for example, a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method. Also, the aluminum film AF is formed of a film containing aluminum as a main component, and can be formed by using, for example, a sputtering method. Furthermore, the barrier conductor film BCF2 is made of, for example, a titanium nitride film, and can be formed by using, for example, a sputtering method. Note that a laminated film of titanium and titanium nitride may be used. Here, for example, the thickness of the barrier conductor film BCF1 is about 110 nm (the thickness of the titanium film (50 nm)+the thickness of the titanium nitride film (60 nm)), and the thickness of the aluminum film AF is about 1500 nm. be. The thickness of the barrier conductor film BCF2 (thickness of the titanium nitride film) is approximately 75 nm.

Subsequently, as shown in FIGS. 16A and 16B, photolithography technology and etching technology are used to form a laminated film including a barrier conductor film BCF1, an aluminum film AF, and a barrier conductor film BCF2. Patterning. By patterning this laminated film, a rectangular pad PD, a lead-out wiring portion DWU provided in the pad PD, a pad PD and a lead-out wiring portion are formed in the chip region along the boundary line between the chip region and the scribe region. It is integrally formed with the inclined portion SLP provided at the connecting portion with the DWU. At this time, since the pad PD, the lead-out wiring part DWU, and the inclined part SLP are formed from the same laminated film, the height of the pad PD, the height of the lead-out wiring part DWU, and the height of the inclined part SLP are almost the same height.

Next, as shown in FIGS. 17A and 17B, a silicon oxide film OXF1 is formed over the interlayer insulating film IL so as to cover the pad PD, the lead wiring portion DWU, and the slope portion SLP. This silicon oxide film OXF1 can be formed by plasma CVD (Chemical Vapor Deposition), for example, and the film thickness of the silicon oxide film OXF1 is about 200 nm. Subsequently, a silicon oxide film OXF2 is formed over the silicon oxide film OXF1. The silicon oxide film OXF2 can be formed, for example, by a high-density plasma CVD method that has the characteristic that film etching and film formation proceed simultaneously, and the film thickness of the silicon oxide film OXF2 is about 900 nm. After that, a silicon oxide film OXF3 is formed over the silicon oxide film OXF2. The silicon oxide film OXF3 can be formed, for example, by a plasma CVD method using TEOS as a raw material, and the film thickness of the silicon oxide film OXF3 is about 800 nm. Then, a silicon nitride film SNF is formed over the silicon oxide film OXF3. The silicon nitride film SNF can be formed, for example, by using the CVD method. In this manner, a surface protection film PAS composed of the silicon oxide film OXF1, the silicon oxide film OXF2, the silicon oxide film OXF3, and the silicon nitride film SNF is formed so as to cover the pad PD, the lead-out wiring portion DWU, and the slope portion SLP. be able to.

At this time, in Embodiment 1, since the surface protective film PAS is thicker than the pad PD, the gap between the pads PD is the silicon oxide film OXF1, the silicon oxide film OXF2, and the silicon oxide film OXF2. It is completely buried with the surface protection film PAS composed of the film OXF3 and the silicon nitride film SNF.

Subsequently, as shown in FIGS. 18A and 18B, photolithography and etching are used to form an opening OP exposing a portion of the surface of the pad PD in the surface protective film PAS. Form. On the other hand, no opening is formed to expose lead-out wiring portion DWU and inclined portion SLP, and the surface of lead-out wiring portion DWU and the surface of inclined portion SLP remain covered with surface protective film PAS. Thereafter, as shown in FIGS. 19A and 19B, the surface of the pad PD exposed from the opening OP is etched to remove the barrier formed on the surface of the pad PD exposed from the opening OP. The conductor film (titanium nitride film) is removed. As a result, the aluminum film is exposed from the opening OP.

As described above, the pads PD can be formed in the uppermost layer of the multilayer wiring layer. Specifically, FIG. 20 is a diagram after the pads PD are formed, and is a schematic cross-sectional view showing the vicinity of the boundary region of the edge ES (the boundary line at this stage). In FIG. 20, a seal ring region SRR and an integrated circuit region ICR are formed inside the scribe region SCR. A seal ring SRG is formed in the seal ring region SRR. This seal ring SRG is formed in the same process as the multilayer wiring (not shown in FIG. 20) formed in the integrated circuit region ICR. A pad PD is formed in the uppermost layer in the integrated circuit region ICR.

Next, subsequent steps will be described with reference to a flow chart. FIG. 21 is a flow chart showing the flow of steps for manufacturing a semiconductor device, for example, a QFP package after forming an integrated circuit on a semiconductor wafer.

First, after forming an integrated circuit in each of a plurality of chip regions of a semiconductor wafer, the semiconductor wafer is diced along the scribe regions (S101 in FIG. 21). As a result, a plurality of chip regions are separated into individual pieces, and a semiconductor chip on which an integrated circuit is formed can be obtained. After the semiconductor chip is mounted on the chip mounting portion formed on the lead frame (S102 in FIG. 21), the pads formed on the semiconductor chip and the inner leads are connected with wires (S103 in FIG. 21). Thereafter, the chip mounting portion, semiconductor chip, wires, and inner leads are sealed with resin (S104 in FIG. 21). Then, after cutting the dam formed on the lead frame (S105 in FIG. 21), a plating film is formed on the surface of the outer lead exposed from the resin (S106 in FIG. 21). Subsequently, after forming marks on the surface of the resin (S107 in FIG. 21), outer leads projecting from the resin are molded (S108 in FIG. 21). After manufacturing the semiconductor device in this manner, an electrical characteristic test is performed (S109 in FIG. 21). Then, the semiconductor device is subjected to a temperature cycle test (S110 in FIG. 21), and the semiconductor device determined to be non-defective is shipped as a product.

(Embodiment 2)
In the first embodiment, the first factor that cracks CLK are generated in the surface protective film PAS at the connecting portion due to the fact that the connecting portion between the pad PD and the lead-out wiring portion DWU is perpendicular has been devised. I explained the technical idea. In the second embodiment, in addition to the technical idea described in the first embodiment, the width of the covering region of the pad PD covered with the surface protective film PAS is small. A technical idea that is devised for the second factor that cracks CLK are likely to occur in the PAS will be described.

FIG. 22 is a plan view showing an enlarged part of the semiconductor chip CHP in the second embodiment. In FIG. 22, the characteristic point of the second embodiment is that the center position of the opening OP is displaced toward the inside (center direction) of the semiconductor chip CHP from the respective center positions of the plurality of pads PD. It is in.

As a result, as shown in FIG. 22, the width of the covering region CVR2 of the surface protective film PAS covering the side closest to the edge side ES of the semiconductor chip CHP among the plurality of sides forming each of the plurality of pads PD is It is wider than the width of the covering region CVR1 of the surface protective film PAS covering the side farthest from the edge ES of the semiconductor chip CHP. This is because of the plurality of sides forming the pad PD, the side (the side closest to the edge ES of the semiconductor chip CHP) that is most likely to receive stress due to expansion and contraction of resin (not shown) caused by temperature changes. ) can be made relatively wide (width in the Y direction). Relatively widening the width (the width in the Y direction) of the covering region CVR2 means that crack resistance to stress is improved. It is possible to suppress the occurrence of cracks in the covering region CVR2 of the surface protective film PAS covering the side closest to the edge ES of the chip CHP. That is, according to the second embodiment, by providing the inclined portion SLP at the connection portion between the lead-out wiring portion DWU and the pad PD, it is possible to suppress the occurrence of cracks at the connection portion, and at the edge side ES of the semiconductor chip CHP. It is possible to obtain the effect of being able to suppress the occurrence of cracks in the covering region CVR2 of the surface protective film PAS covering the nearest side. In other words, the technical idea in the second embodiment is a device for the first factor and the second factor described above, and as a result of being able to effectively suppress the synergistic factor of the first factor and the second factor, excellent crack resistance can provide a highly reliable semiconductor device having

Furthermore, as shown in FIG. 22, in the second embodiment, attention is focused on the pad PD1 closest to the corner CNR of the semiconductor chip CHP among the plurality of pads PD. Specifically, as shown in FIG. 22, in the pad PD1 closest to the corner CNR of the semiconductor chip CHP, the side closest to the corner of the semiconductor chip CHP among the plurality of sides forming the pad PD1 is covered. The width of the covering region CVR3 of the surface protective film PAS is also made wider than the width of the covering region CVR1 of the surface protective film PAS covering the side farthest from the edge side ES of the semiconductor chip CHP.

As a result, in the second embodiment, in the pad PD1 closest to the corner CNR of the semiconductor chip CHP, the side (semiconductor chip The width (the width in the Y direction) of the covering region CVR2 covering the side closest to the end side ES of the CHP can be relatively widened. Furthermore, in the second embodiment, the width of the covering region CVR3 that covers the side closest to the corner CNR where stress tends to increase can be relatively widened. As a result, in the second embodiment, the crack resistance is particularly improved in the pad PD1 arranged at the position closest to the corner CNR of the semiconductor chip CHP.

As means for realizing a configuration in which the center position of the opening OP is shifted inward (center direction) of the semiconductor chip CHP with respect to the center position of each of the plurality of pads PD, the size (area) of the pad PD A first means for reducing the size of the opening OP while maintaining the , and a second means for increasing the size of the pad PD while maintaining the size (area) of the opening OP can be considered. For example, as an advantage of the first means, since the size of the pads PD is maintained, the technical idea of the second embodiment can be realized without increasing the interval (pitch) for arranging the plurality of pads PD. Points can be raised. In this case, for example, it is possible to obtain the advantage of being able to realize the technical idea of the second embodiment while suppressing an increase in the number of semiconductor chips.

On the other hand, as an advantage of the second means, since the size of the opening OP is maintained, the connection reliability of the wire connected to the surface of the pad PD exposed from the opening OP is not deteriorated. The point that the technical idea in 2 can be realized can be mentioned. In this case, for example, it is possible to obtain the advantage that the technical idea in the second embodiment can be realized without affecting the reliability of the semiconductor device (especially, wire connection reliability).

The method of manufacturing the semiconductor device in the second embodiment is basically the same as the method of manufacturing the semiconductor device in the first embodiment. However, in the method of manufacturing a semiconductor device according to the second embodiment, in the step of forming the opening OP exposing a part of the surface of each of the plurality of pads PD in the surface protection film PAS, the photolithography technique and the etching technique are used. patterning using is modified. Specifically, the patterning process of the opening OP is performed so that the center position of the opening OP is shifted inward (center direction) of the chip region with respect to the center positions of the plurality of pads PD. . That is, in the patterning step of the opening OP, the width of the covering region CVR2 of the surface protective film PAS covering the side closest to the boundary among the plurality of sides forming each of the plurality of pads PD is the most distant from the boundary. It is made wider than the width of the covering region CVR1 of the surface protective film PAS covering the other side.

Further, in the patterning step of the opening OP in the second embodiment, the pad PD1 closest to the corner CNR of the chip region among the plurality of pads PD has the edge of the chip region among the plurality of sides forming the pad PD1. The width of the covering region CVR3 of the surface protective film PAS covering the side closest to the corner CNR is also made wider than the width of the covering region CVR1 of the surface protective film PAS covering the side farthest from the boundary line.

(Embodiment 3)
In the first and second embodiments, a configuration example in which a plurality of pads PD are arranged in a row along the edge ES of the semiconductor chip CHP has been described. A configuration example in which a plurality of pads PD are arranged in multiple rows (for example, two rows) along the edge ES of the semiconductor chip CHP will be described.

FIG. 23 is a plan view showing an enlarged part of the semiconductor chip CHP in the third embodiment. In FIG. 23, a plurality of pads are arranged in two rows along the edge ES of the semiconductor chip CHP. Specifically, the plurality of pads includes a plurality of outer pads OPD arranged along the edge ES on the side closer to the edge ES of the semiconductor chip CHP and a plurality of outer pads OPD arranged along the edge ES on the side farther from the edge ES of the semiconductor chip CHP. It includes a plurality of inner pads IPD arranged along side ES. For example, FIG. 23 shows an example in which outer pads OPD and inner pads IPD arranged in two rows are arranged in a so-called staggered arrangement. Here, the outer pads OPD are arranged in the first row closer to the edge ES, and the inner pads IPD are arranged in the second row farther from the edge ES.

As shown in FIG. 23, in the plurality of inner pads IPD, the lead wiring portion is connected to the side closest to the end side ES of the semiconductor chip CHP among the plurality of sides forming each of the plurality of inner pads IPD. DWU is provided, and a sloped portion SLP (IN) is provided at a connecting portion between each of the plurality of inner pads IPD and the lead-out wiring portion DWU.

On the other hand, in the plurality of outer pads OPD, a lead wiring portion DWU is provided so as to be connected to the side furthest from the edge side ES of the semiconductor chip CHP among the plurality of sides forming each of the plurality of outer pads OPD. ing. A sloped portion SLP (OUT) is provided at a connection portion between each of the plurality of outer pads OPD and the lead wiring portion DWU.

Here, for example, the shape and size of the inclined portion SLP(IN) provided integrally with the inner pad IPD are the same as the shape and size of the inclined portion SLP(OUT) provided integrally with the outer pad OPD. are identical.

As described above, in the third embodiment, both the outer pads OPD and the inner pads IPD arranged in a zigzag arrangement have inclined portions SLP(OUT) or inclined portions SLP(IN) at the connecting portions with the lead-out wiring portion DWU. is provided. As a result, even in the third embodiment, cracks do not occur in the covered region where a portion of the outer pad OPD is covered with the surface protective film PAS or the covered region where a portion of the inner pad IPD is covered with the surface protective film PAS. can be suppressed. In other words, the technical idea described in the first embodiment can be applied not only to a plurality of pads PD arranged in one row, but also to a plurality of rows of pads PD, such as a staggered arrangement, as in the third embodiment. It can also be applied to a plurality of inner pads IPD and a plurality of outer pads OPD arranged in parallel.

<Modification 1>
In the third embodiment, as shown in FIG. 23, the shape and size of the inclined portion SLP (IN) provided integrally with the inner pad IPD are the same as those of the inclined portion SLP provided integrally with the outer pad OPD. Although an example in which the shape and size are the same as those of (OUT) has been described, in Modification 1, an example in which the size of the slant portion SLP(IN) and the size of the slant portion SLP(OUT) are different will be described.

FIG. 24 is a plan view showing an enlarged part of the semiconductor chip CHP in Modification 1. As shown in FIG. In FIG. 24, in Modification 1, the size (area) of the inclined portion SLP(IN) provided integrally with the inner pad IPD is equal to the size (area) of the inclined portion SLP(OUT) provided integrally with the outer pad OPD. ) is larger than the size (area) of In other words, the size of the inclined portion SLP(OUT) provided integrally with the outer pad OPD is smaller than the size of the inclined portion SLP(IN) provided integrally with the inner pad IPD.

The reason for this will be explained below. According to studies by the present inventors, it has been found that the stress applied to the covering region covering the side closest to the edge side ES of the semiconductor chip CHP among the plurality of sides forming the pad tends to be relatively large. there is Focusing on the inner pad IPD shown in FIG. 24 based on this point, in the inner pad IPD, among the plurality of sides forming the inner pad IPD, the lead wiring portion is located on the side closest to the end side ES of the semiconductor chip CHP. A DWU is provided. Therefore, in the inner pad IPD, the connection portion between the inner pad IPD and the lead-out wiring portion DWU is present on the side closest to the edge ES of the semiconductor chip CHP where stress tends to increase. This means that, in the inner pad IPD, there is a connection portion between the inner pad IPD and the lead wiring portion DWU at a location where the stress is relatively large. Cracks are more likely to occur in the coated area. Therefore, in Modification 1, from the viewpoint of sufficiently suppressing the occurrence of cracks at the connection portion between the inner pad IPD and the lead-out wiring portion DWU, a large-sized inclined portion SLP (IN) is provided at this connection portion. . That is, the larger the size of the inclined portion SLP(IN) is, the more likely it is that the occurrence of cracks at the connecting portion between the inner pad IPD and the lead-out wiring portion DWU can be suppressed. A large slanted portion SLP (IN) is provided at the connection site with the . As a result, even when a relatively large stress is applied to the connecting portion between the inner pad IPD and the lead-out wiring portion DWU, the occurrence of cracks at this connecting portion can be sufficiently suppressed.

On the other hand, focusing on the outer pad OPD shown in FIG. 24, in the outer pad OPD, the lead wiring portion DWU is provided on the side furthest from the edge side ES of the semiconductor chip CHP among the plurality of sides forming the outer pad OPD. It is Therefore, in the outer pad OPD, the connection portion between the outer pad OPD and the lead-out wiring portion DWU is present on the farthest side from the edge side ES of the semiconductor chip CHP where the stress is assumed to be relatively small. Become. This means that, in the outer pad OPD, there is a connection portion between the outer pad OPD and the lead-out wiring portion DWU at a location where the stress is relatively less likely to increase. It can be considered that cracks are less likely to occur in the covered area of . Therefore, in Modification 1, the occurrence of cracks at the connecting portion between the outer pad OPD and the lead-out wiring portion DWU is less likely to cause a problem than the crack at the connecting portion between the inner pad IPD and the lead-out wiring portion DWU. In consideration of this, a small-sized inclined portion SLP(OUT) is provided at the connecting portion between the outer pad OPD and the lead-out wiring portion DWU. That is, even if the size of the inclined portion SLP(OUT) is small, it is possible to suppress the occurrence of cracks at the connecting portion between the outer pad OPD and the lead-out wiring portion DWU. A small-sized slant portion SLP(OUT) is provided at the connection portion of the . As a result, in Modification 1, the size of the inclined portion SLP(IN) provided integrally with the inner pad IPD is larger than the size of the inclined portion SLP(OUT) provided integrally with the outer pad OPD. is realized. Also in this configuration, it is possible to suppress the occurrence of cracks at the connecting portion between the inner pad IPD and the lead-out wiring portion DWU, and suppress the occurrence of cracks at the connecting portion between the outer pad OPD and the lead-out wiring portion DWU. be able to.

<Modification 2>
In Modification 2, an example will be described in which the inclined portion SLP (IN) is provided integrally with the inner pad IPD, but no inclined portion is provided at the connecting portion between the outer pad OPD and the lead-out wiring portion DWU.

FIG. 25 is a plan view showing an enlarged part of the semiconductor chip CHP in Modification 2. As shown in FIG. For example, as described in Modification 1 above, in the outer pad OPD, the lead wiring portion DWU is provided on the side furthest from the edge side ES of the semiconductor chip CHP among the plurality of sides forming the outer pad OPD. It is In this case, in the outer pad OPD, since the magnitude of the stress applied to the connection portion between the outer pad OPD and the lead-out wiring portion DWU is considered to be relatively small, the covering region of the surface protective film PAS covering this connection portion. It can be assumed that cracks are less likely to occur in Therefore, in Modified Example 2, the occurrence of cracks at the connecting portion between the outer pad OPD and the lead-out wiring portion DWU is less likely to cause a problem than the crack at the connecting portion between the inner pad IPD and the lead-out wiring portion DWU. In consideration of this point, the connecting portion between the outer pad OPD and the lead-out wiring portion DWU is configured so as not to have an inclined portion. Also in the present modification 2 configured in this manner, since the inner pad IPD is integrally provided with the inclined portion SLP (IN), cracks do not occur at the connecting portion between the inner pad IPD and the lead-out wiring portion DWU. The occurrence can be sufficiently suppressed.

(Embodiment 4)
In the fourth embodiment, as in the third embodiment, a configuration example is assumed in which a plurality of pads are arranged in a staggered arrangement along the edge ES of the semiconductor chip CHP. Description will be made of a technical idea incorporating a device for the second factor that cracks are likely to occur in the surface protective film PAS due to the small width of the covering area of the pad covered with .

FIG. 26 is a plan view showing an enlarged part of the semiconductor chip CHP in the fourth embodiment. In FIG. 26, in the fourth embodiment, on the premise of the zigzag arrangement, the center positions of the openings OP of the plurality of inner pads IPD forming the zigzag arrangement match the respective center positions of the plurality of inner pads IPD. ing. On the other hand, in the plurality of outer pads OPD forming the staggered arrangement, the center position of the opening OP is displaced toward the inside (center direction) of the semiconductor chip CHP from the respective center positions of the plurality of outer pads OPD. ing.

As a result, as shown in FIG. 26, the width of the covering region CVR2 of the surface protective film PAS covering the side closest to the edge ES of the semiconductor chip CHP among the plurality of sides forming each of the plurality of outer pads OPD is , wider than the width of the covering region CVR1 of the surface protective film PAS covering the side farthest from the edge ES of the semiconductor chip CHP. This is because of the plurality of sides forming the outer pad OPD, the side (closest to the edge ES of the semiconductor chip CHP) that is most susceptible to stress due to expansion and contraction of the resin (not shown) caused by temperature changes. This means that the width (width in the Y direction) of the covering region CVR2 that covers the edge) can be made relatively wide. Relatively widening the width (the width in the Y direction) of the covering region CVR2 means that crack resistance to stress is improved. In the pad OPD, the occurrence of cracks in the covering region CVR2 of the surface protective film PAS covering the side closest to the edge ES of the semiconductor chip CHP can be suppressed. That is, according to the fourth embodiment, as in the third embodiment, the inclined portion SLP (OUT) is provided at the connection portion between the outer pad OPD and the lead wiring portion DWU, and the inner pad IPD and the lead wiring are provided. By providing the inclined portion SLP(IN) at the connection portion with the portion DWU, it is possible to suppress the occurrence of cracks at the connection portion. Furthermore, in the fourth embodiment, as shown in FIG. 26, the width (the width in the Y direction) of the covering region CVR2 of the outer pad OPD can be relatively widened. It is also possible to suppress the occurrence of cracks in the covering region CVR2 of the surface protective film PAS covering the nearest side.

Furthermore, as shown in FIG. 26, in the fourth embodiment, attention is focused on the outer pad OPD1 closest to the corner CNR of the semiconductor chip CHP among the plurality of outer pads OPD. Specifically, as shown in FIG. 26, in the outer pad OPD1 closest to the corner CNR of the semiconductor chip CHP, among the plurality of sides forming the outer pad OPD1, the side closest to the corner of the semiconductor chip CHP The width of the covering region CVR3 of the surface protective film PAS covering the edge ES of the semiconductor chip CHP is also wider than the width of the covering region CVR1 of the surface protective film PAS covering the side farthest from the edge ES of the semiconductor chip CHP.

As a result, in the fourth embodiment, in the outer pad OPD1 closest to the corner CNR of the semiconductor chip CHP, the side (semiconductor The width (the width in the Y direction) of the covering region CVR2 covering the side closest to the end side ES of the chip CHP can be relatively widened. Furthermore, in the fourth embodiment, it is possible to relatively widen the width of the covering region CVR3 covering the side closest to the corner CNR where stress tends to increase. As a result, in the fourth embodiment, crack resistance can be improved particularly in the outer pad OPD1 arranged closest to the corner CNR of the semiconductor chip CHP.

<Modification>
Next, a modification of Embodiment 4 will be described. In the fourth embodiment, focusing on the outer pad OPD, it is said that cracks are likely to occur in the surface protective film PAS due to the small width of the covered region of the outer pad OPD covered with the surface protective film PAS. An example in which a device for the second factor is also incorporated has been described. In this modified example, further attention is paid to the inner pad IPD, and an example in which the inner pad IPD is also devised for the second factor will be described. That is, in the fourth embodiment, since it is considered that the above-described second factor becomes apparent in the outer pads OPD near the edge ES of the semiconductor chip CHP, first, the outer pads OPD are devised to address the second factor. explained an example of incorporating Furthermore, in this modification, since the inner pads IPD are farther from the edge ES of the semiconductor chip CHP than the outer pads OPD, it is considered that the second factor is less affected than the outer pads OPD. , considers the possibility of being slightly affected by the second factor. That is, in this modified example, from the viewpoint of further improving the reliability of the semiconductor device, the inner pad IPD is also devised for the second factor.

FIG. 27 is a plan view showing an enlarged part of the semiconductor chip CHP in this modification. In FIG. 27, in this modification, on the premise of the zigzag arrangement, not only the plurality of outer pads OPD forming the zigzag arrangement, but also the inner pads IPD, the center position of the opening OP is set to each of the plurality of inner pads IPD. The characteristic point is that the center position of the semiconductor chip CHP is displaced toward the inner side (center direction) of the semiconductor chip CHP.

As a result, as shown in FIG. 27, the width of the covering region CVR2 of the surface protective film PAS covering the side closest to the edge side ES of the semiconductor chip CHP among the plurality of sides forming each of the plurality of inner pads IPD is , wider than the width of the covering region CVR1 of the surface protective film PAS covering the side farthest from the edge ES of the semiconductor chip CHP. This is because of the plurality of sides forming the inner pad IPD, the side (closest to the edge ES of the semiconductor chip CHP) that is most susceptible to stress due to expansion and contraction of resin (not shown) caused by temperature changes. This means that the width (width in the Y direction) of the covering region CVR2 that covers the edge) can be made relatively wide. Relatively increasing the width (the width in the Y direction) of the covering region CVR2 means that the crack resistance to stress is improved. , it is possible to suppress the occurrence of cracks in the covering region CVR2 of the surface protective film PAS covering the side closest to the edge ES of the semiconductor chip CHP.

Furthermore, as shown in FIG. 27, among the plurality of inner pads IPD, attention is focused on the inner pad IPD1 closest to the corner CNR of the semiconductor chip CHP in this modification. Specifically, as shown in FIG. 27, in the inner pad IPD1 closest to the corner CNR of the semiconductor chip CHP, among the plurality of sides forming the inner pad IPD1, the side closest to the corner of the semiconductor chip CHP The width of the covering region CVR3 of the surface protective film PAS covering the edge ES of the semiconductor chip CHP is also wider than the width of the covering region CVR1 of the surface protective film PAS covering the side farthest from the edge ES of the semiconductor chip CHP.

As a result, in this modification, in the inner pad IPD1 closest to the corner CNR of the semiconductor chip CHP, the side (semiconductor chip CHP The width (the width in the Y direction) of the covering region CVR2 covering the side closest to the end side ES of the CVR2 can be relatively widened. Furthermore, in this modification, the width of the covered region CVR3 that covers the side closest to the corner CNR where stress tends to increase can be relatively widened. As a result, in this modification, crack resistance can be improved particularly in the inner pad IPD1 arranged closest to the corner CNR of the semiconductor chip CHP.

As described above, according to this modification, not only the outer pads OPD but also the inner pads IPD are designed to address the second factor. As a result, according to this modification, both the plurality of outer pads OPD and the plurality of inner pads IPD arranged in a staggered arrangement can improve the crack resistance against the first factor and the second factor. , the reliability of the semiconductor device can be further improved.

(Embodiment 5)
In the fifth embodiment, a technical idea that has been devised for the above-mentioned third factor will be described. That is, in the fifth embodiment, a line segment (1 Due to the increase in the length (the length in the X direction) of a part of the side, the "aluminum slide" in which a part of the pad PD shifts, and the crack CLK in the surface protective film PAS are likely to occur. I will explain the device for

FIG. 28 is a plan view showing a schematic configuration of the pad PD according to the fifth embodiment. In FIG. 28, a lead wiring portion DWU is provided integrally with the pad PD. At this time, the width (the width in the X direction) of the lead-out wiring portion DWU is shorter than the length of the side to which the lead-out wiring portion DWU is connected, among the plurality of sides forming the pad PD. The center position of the width of the lead-out wiring part DWU is shifted from the center position of the side to which the lead-out wiring part DWU is connected, among the plurality of sides forming the pad PD.

In the pad PD according to the fifth embodiment configured as described above, as shown in FIG. The length of the non-contacting line segment is the long side (long line segment side) (the left side of the lead wiring portion DWU in FIG. 28). On the other hand, the other side of the lead-out wiring part DWU is the short side (short line segment side) of the side to which the lead-out wiring part DWU is connected, which does not contact the lead-out wiring part DWU (the lead-out wiring in FIG. 28). on the right side of the part DWU).

In the pad PD according to the fifth embodiment configured in this manner, the expansion and contraction of the resin (not shown) caused by temperature changes causes the sides to flex particularly on the long line segment side. As a result, there is an increased possibility that "aluminum slide" or cracks will occur on the long line segment side.

Therefore, in the fifth embodiment, on the premise that the inclined portions are provided on both sides of the lead-out wiring portion DWU, the shape of the inclined portion SLP1 provided on one side (long line segment side) of the lead-out wiring portion DWU, The shape of the inclined portion SLP2 provided on the other side (short line segment side) of the lead wiring portion DWU is made asymmetrical.

Specifically, as shown in FIG. 28, the size of the inclined portion SLP1 provided on one side (long line segment side) of the lead wiring portion DWU is the same as that on the other side (short line segment side) of the lead wire portion. It is larger than the size of the provided inclined portion SLP2. Then, for example, as shown in FIG. 28, the shape of the inclined portion SLP1 provided on one side (long line segment side) of the lead-out wiring portion DWU is trapezoidal. The shape of the inclined portion SLP2 provided on one side (short line segment side) is triangular.

As a result, since the size of the inclined portion SLP provided on the long line segment side, where the bending of the side is considered to be large, is increased, it is possible to suppress the bending on the long line side. As a result, according to the fifth embodiment, it is possible to effectively suppress the occurrence of "aluminum slide" and cracks that are actualized by bending on the long line segment side.

In particular, according to the inventor's study, in FIG. 28, the width of the covering region of the surface protective film PAS covering the side to which the lead-out wiring portion DWU is connected among the plurality of sides forming the pad PD (the width in the Y direction) ) is a1, and the width (width in the X direction) of the covered region of the surface protective film PAS is b1. It has been found that the bending of the sides of the pad PD can be sufficiently suppressed. Further, when the height (Y direction) of the trapezoidal shape that is the inclined portion SLP1 is a2 and the length of the base of the trapezoidal shape that is the inclined portion SLP1 is b2, the relationship b2/a2<3 is satisfied. desirable for similar reasons. Furthermore, it is more desirable to satisfy (b2/a2)+(b1/a1)<3.

<Modification 1>
As described in the fifth embodiment, the size of the inclined portion SLP1 provided on one side (long line segment side) of the lead wiring portion DWU is changed to the size of the inclined portion SLP1 provided on the other side (short line segment side) of the lead wiring portion. From the viewpoint of preventing "aluminum slide" and cracks that become obvious due to bending on the long line segment side, it is desirable to make the size larger than the size of the inclined portion SLP2.

However, the trapezoidal shape of the inclined portion SLP1 and the triangular shape of the inclined portion SLP2 are merely examples. For example, as shown in FIG. The inclined portion SLP1 provided on the long line segment side) has a first triangular shape, and the inclined portion SLP2 provided on the other side (short line segment side) of the lead wiring portion DWU has a second triangular shape. It may be of any shape.

At this time, the width (the width in the Y direction) of the covered region of the surface protective film PAS covering the side to which the lead-out wiring portion DWU is connected among the plurality of sides forming the pad PD is set to a1, and the coverage of the surface protective film PAS When the width of the region (the width in the X direction) is b1, satisfying the relationship b1/a1<3 is from the viewpoint of reliably preventing the occurrence of "aluminum slide" and cracks that become apparent due to bending on the long line side. desirable. Further, when the height (Y direction) of the first triangular shape that is the inclined portion SLP1 is a2 and the length of the base (X direction) of the first triangular shape that is the inclined portion SLP1 is b2, b2/a2< 3 is desirable for similar reasons. Furthermore, it is more desirable to satisfy (b2/a2)+(b1/a1)<3.

<Modification 2>
28 and 29 can also be applied to FIGS. 23, 24 and 25 described in the third embodiment. That is, as shown in FIG. 23, the above-described sloped portions SLP1 and sloped portions SLP2 may be formed in the first and second rows of the zigzag arrangement. Further, as shown in FIG. 24, the sizes of the inclined portions SLP1 and SLP2 formed in the second row of the staggered arrangement are larger than the sizes of the inclined portions SLP1 and SLP2 formed in the first row of the staggered arrangement. It may be formed to be Alternatively, as shown in FIG. 25, the inclined portions SLP1 and SLP2 may be formed only in the second row of the zigzag arrangement and not formed in the first row. Also, the technique disclosed in FIGS. 28 and 29 described above can be applied to the fourth embodiment described above.

(Embodiment 6)
In the sixth embodiment, on the premise that there are a plurality of lead-out wiring portions DWU provided integrally with the pad PD, an example of applying a technical idea in which the first factor is devised to the premised configuration. will be explained.

FIG. 30 is a plan view showing an enlarged part of the semiconductor chip CHP in the sixth embodiment. In FIG. 30, for example, among the plurality of outer pads OPD and the plurality of inner pads IPD arranged in a staggered arrangement, the outer pad OPD2 of the plurality of outer pads OPD has a lead-out wiring portion DWU1 integrated with the outer pad OPD2. and a lead-out wiring portion DWU2 are provided. This is an example of a layout configuration that is implemented, for example, to ensure the amount of current flowing through the outer pad OPD2. That is, for example, when the amount of current flowing through the outer pad OPD2 is large and it is difficult to deal with it with only a single lead-out wiring part DWU1, the lead-out wiring part DWU1 and the lead-out wiring part DWU2 are provided integrally with the outer pad OPD2. Therefore, even when the amount of current is large, it can be handled. Although not shown, the lead-out wiring portion DWU2 is provided with a contact to the lower layer wiring in the same way as the lead-out wiring portion DWU1, and is electrically connected to the field effect transistor Q provided in the integrated circuit region. is doing.

In addition, such a lead-out wiring portion DWU2 is used when there is no space for further pads between the two outer pads OPD, or when two pads OPD having the same function such as power supply need to be arranged side by side. It is effective in terms of reduction.

Specifically, as shown in FIG. 30, the outer pad OPD2 has a rectangular shape, and the plurality of lead wiring portions connected to the outer pad OPD2 are lead wires connected to the short sides of the outer pad OPD2. It is composed of a wiring portion DWU1 and a lead-out wiring portion DWU2 connected to the long side of the outer pad OPD2. In this case, an inclined portion SLP (OUT) is provided at the connection portion between the outer pad OPD2 and the lead-out wiring portion DWU1, and an inclined portion SLP (OUT) is also provided at the connection portion between the outer pad OPD2 and the lead-out wiring portion DWU2. .

In the outer pad OPD2 according to the sixth embodiment configured in this way, it is possible to suppress the occurrence of cracks at the connecting portion between the outer pad OPD2 and the lead-out wiring portion DWU1, and at the same time, the outer pad OPD2 and the lead-out wiring portion DWU2 can be prevented from being cracked. It is possible to suppress the occurrence of cracks even at the connecting portion.

In addition, in the sixth embodiment, the case where both the lead-out wiring portion DWU1 and the lead-out wiring portion DWU2 are formed in the outer pad OPD2 was exemplified. A similar effect can be obtained even if it is formed.

In addition, in the sixth embodiment, an example of a staggered arrangement is shown, but it is also possible to apply even if the pads are arranged in only one row as in the first and second embodiments described above. . That is, the technique disclosed in the sixth embodiment can also be applied to the first to fifth embodiments described above.

(Embodiment 7)
In the seventh embodiment, an example of changing the position of the opening of the silicon nitride film SNF in the surface protective film PAS disclosed in FIG. 11 will be described.

FIG. 31 is a plan view of the pad PD, and FIG. 32 is a cross-sectional view of the pad PD. In Embodiment 7, after forming the silicon oxide film OXF1, the silicon oxide film OXF2, and the silicon oxide film OXF3, the opening OP1 is formed by patterning using a photoresist film as a mask. Note that the barrier conductor film BCF2 is also etched in the same process, and the aluminum film AF is exposed from the opening OP1. Thereafter, a silicon nitride film SNF is formed and patterned separately to form an opening OP2 inside the opening OP1.

In the seventh embodiment, in the opening OP1, the side surfaces of the silicon oxide film OXF1, the silicon oxide film OXF2, the silicon oxide film OXF3, and the barrier conductor film BCF2 can be covered with the silicon nitride film SNF. Therefore, when titanium nitride is used as the barrier conductor film BCF2, it is possible to prevent the titanium nitride from being oxidized. When titanium nitride is oxidized, its volume expands and stress is applied to the surface protective film PAS thereon. As a result, there is concern that cracks are more likely to occur in the silicon nitride film SNF. Therefore, in the seventh embodiment, by covering the side surface of the barrier conductor film BCF2 with the silicon nitride film SNF, it is possible to further prevent cracks from occurring.

It is needless to say that the technique disclosed in the seventh embodiment can be applied to the first to sixth embodiments described above. In that case, the opening OP2 of the seventh embodiment corresponds to the opening OP shown in the first to sixth embodiments.

The invention made by the present inventor has been specifically described above based on the embodiment, but the present invention is not limited to the above embodiment, and can be implemented by combining each without departing from the scope of the invention. It goes without saying that it is possible to

The embodiment includes the following modes.

(Appendix 1)
Equipped with a rectangular semiconductor chip,
The semiconductor chip is
(a) a plurality of pads arranged along an edge of the semiconductor chip;
(b) a lead-out wiring portion provided for each of the plurality of pads;
(c) an inclined portion provided at a connection portion between each of the plurality of pads and the lead wiring portion;
has
the width of the lead-out wiring portion is shorter than the length of a side to which the lead-out wiring portion is connected, out of the plurality of sides forming each of the plurality of pads;
The semiconductor device according to claim 1, wherein the center position of the width of the lead-out wiring portion is displaced from the center position of the side to which the lead-out wire portion is connected, among the plurality of sides forming each of the plurality of pads.

(Appendix 2)
In the semiconductor device according to Supplementary Note 1,
The semiconductor device, wherein the inclined portions are provided on both sides of the lead wiring portion.

(Appendix 3)
In the semiconductor device according to Supplementary Note 2,
The semiconductor device, wherein the shape of the inclined portion provided on one side of the lead wiring portion and the shape of the inclined portion provided on the other side of the lead wire portion are asymmetrical.

(Appendix 4)
In the semiconductor device according to Appendix 3,
one side of the lead-out wiring portion is a side with a longer line segment not in contact with the lead-out wiring portion among the sides to which the lead-out wiring portion is connected;
the other side of the lead-out wiring portion is a side with a short line segment not in contact with the lead-out wiring portion among the sides to which the lead-out wiring portion is connected;
The semiconductor device according to claim 1, wherein the inclined portion provided on one side of the lead-out wiring portion is larger in size than the inclined portion provided on the other side of the lead-out wiring portion.

(Appendix 5)
In the semiconductor device according to Appendix 4,
The inclined portion provided on one side of the lead-out wiring portion has a trapezoidal shape, and the inclined portion provided on the other side of the lead-out wiring portion has a triangular shape. semiconductor device.

(Appendix 6)
In the semiconductor device according to Appendix 5,
(d) having a surface protective film covering each of the plurality of pads, the lead-out wiring portion, and the inclined portion;
the surface protection film is provided with openings that expose a part of the surface of each of the plurality of pads;
Let the height of the trapezoidal shape be a2,
A semiconductor device that satisfies a relationship of b2/a2<3, where b2 is the length of the base of the trapezoidal shape.

(Appendix 7)
In the semiconductor device according to Appendix 4,
The inclined portion provided on one side of the lead-out wiring portion has a first triangular shape, and the inclined portion provided on the other side of the lead-out wiring portion has a second triangular shape. A semiconductor device having a shape.

(Appendix 8)
In the semiconductor device according to appendix 7,
(d) having a surface protective film covering each of the plurality of pads, the lead-out wiring portion, and the inclined portion;
the surface protection film is provided with openings that expose a part of the surface of each of the plurality of pads;
Let the height of the first triangular shape be a2,
The semiconductor device satisfies the relationship b2/a2<3, where b2 is the length of the base of the first triangular shape.

(Appendix 9)
Equipped with a rectangular semiconductor chip,
The semiconductor chip is
(a) a plurality of pads arranged along an edge of the semiconductor chip;
(b) a lead-out wiring portion provided for each of the plurality of pads;
(c) an inclined portion provided at a connection portion between each of the plurality of pads and the lead wiring portion;
has
a plurality of lead wiring portions are connected to a first pad among the plurality of pads;
The semiconductor device according to claim 1, wherein the inclined portion is provided at a connection portion of each of a plurality of lead wiring portions connected to the first pad.

(Appendix 10)
In the semiconductor device according to Appendix 9,
each of the plurality of pads has a rectangular shape,
The plurality of lead-out wiring portions connected to the first pad include a first lead-out wiring portion connected to the short side of the first pad and a second lead-out wiring portion connected to the long side of the first pad. A semiconductor device, comprising:

(Appendix 11)
(a) preparing a semiconductor substrate having a rectangular chip area and a scribe area defining the chip area;
(b) a plurality of rectangular pads and lead-out wiring portions provided in each of the plurality of pads in the chip region along a boundary line between the chip region and the scribe region;
forming an inclined portion provided at a connection portion between each of the plurality of pads and the lead-out wiring portion;
A method of manufacturing a semiconductor device, comprising:

(Appendix 12)
In the method for manufacturing a semiconductor device according to Appendix 11,
(c) forming a surface protective film covering the plurality of pads, the lead-out wiring portion, and the inclined portion;
(d) forming an opening in the surface protection film to expose a part of the surface of each of the plurality of pads;
(e) obtaining semiconductor chips by dicing the semiconductor substrate along the scribe region after the step (d);
(f) connecting a wire to each surface of the plurality of pads exposed from the opening after the step (e);
(g) a step of sealing the semiconductor chip after the step (f);
A method of manufacturing a semiconductor device, comprising:

(Appendix 13)
In the method for manufacturing a semiconductor device according to Appendix 12,
(g) A method of manufacturing a semiconductor device, comprising a step of conducting a temperature cycle test after the step.

(Appendix 14)
In the method for manufacturing a semiconductor device according to Appendix 12,
In the step (d), the opening is formed such that the central position of the opening is shifted toward the inside of the chip region with respect to the central position of each of the plurality of pads. Method.

(Appendix 15)
In the method for manufacturing a semiconductor device according to Appendix 12,
In the step (d), among the plurality of sides forming each of the plurality of pads, the width of the covering region of the surface protective film covering the side closest to the boundary line is the side farthest from the boundary line. forming the opening so as to be wider than the width of the covered region of the surface protective film covering the surface protection film.

(Appendix 16)
In the method for manufacturing a semiconductor device according to appendix 15,
In the step (d), the first pad closest to the corner of the chip region among the plurality of pads further includes the corner of the chip region among the plurality of sides forming the first pad. The opening is formed so that the width of the covered area of the surface protective film covering the side closest to is also wider than the width of the covered area of the surface protective film covering the side farthest from the boundary line. A method of manufacturing a semiconductor device.

1S Semiconductor substrate AF Aluminum film BCF1 Barrier conductor film BCF2 Barrier conductor film CHP Semiconductor chip CLK Crack CNR Corner CR Chip region CVR1 Covering region CVR2 Covering region CVR3 Covering region DWU Lead wiring DWU1 Lead wiring DWU2 Lead wiring ES Edge FL Fine layer GL Global layer ICR Integrated circuit region IL Interlayer insulating film IL1 Inner lead IPD Inner pad IPD1 Inner pad MR Resin OL Outer lead OP Opening OPD Outer pad OPD1 Outer pad OPD2 Outer pad OXF1 Silicon oxide film OXF2 Silicon oxide film OXF3 Silicon oxide Film PAS Surface protective film PD Pad PD1 Pad PF Plating film Q Field effect transistor SA1 Semiconductor device SCR Scribe region SLP Slanted portion SLP (IN) Slanted portion SLP (OUT) Slanted portion SLP1 Slanted portion SLP2 Slanted portion SM Discontinuous region SM1 Discontinuous Region SM2 Discontinuous Region SNF Silicon Nitride Film SRG Seal Ring SRR Seal Ring Region TAB Chip Mounting Area W Wire WF Semiconductor Wafer

Claims (21)

A rectangular semiconductor chip,
a first pad;
a first lead-out wiring portion integrally formed with the first pad and connected to an underlying wiring via a first contact;
an inclined portion provided at a connecting portion between the first pad and the first lead-out wiring portion;
a surface protection film having a first opening covering the first lead-out wiring portion and exposing a portion of the surface of the first pad;
has
a center position of a width of the first lead-out wiring portion is shifted from a center position of a side to which the first lead-out wiring portion is connected, among a plurality of sides forming the first pad;
A connection angle of a connection portion between the first pad and the first lead-out wiring portion is composed of two obtuse angles,
The semiconductor chip further has a second pad formed adjacent to the first pad along an edge of the semiconductor chip,
a second opening exposing a part of the surface of the second pad is formed in the surface protection film;
The size of the first pad is different from the size of the second pad in plan view,
The semiconductor chip, wherein the size of the first opening is the same as the size of the second opening in plan view. A rectangular semiconductor chip,
The semiconductor chip is
A first pad having a first side extending along a first direction and a second side extending along the first direction and positioned on an extension line of the first side When,
A third side extending along a second direction orthogonal to the first direction in plan view, and a fourth side extending along the second direction and facing the third side a first lead-out wiring portion formed integrally with the first pad and connected to a lower layer wiring via a first contact;
a surface protection film having a first opening covering the first lead-out wiring portion and exposing a portion of the surface of the first pad;
has
In the first direction, the length of the first side is longer than the length of the second side,
The first side and the third side are different from the first direction and the second direction in plan view and extend along a third direction from one of the first side and the third side to the other. are connected to each other via existing fifth sides,
The second side and the fourth side are different from the first direction and the second direction in plan view and extend along a fourth direction from one of the second side and the fourth side to the other. are connected to each other via existing sixth sides,
an exterior angle formed by the first side and the fifth side is greater than 90 degrees,
an exterior angle formed by the second side and the sixth side is greater than 90 degrees,
The semiconductor chip further has a second pad formed adjacent to the first pad along an edge of the semiconductor chip,
a second opening exposing a part of the surface of the second pad is formed in the surface protection film;
The size of the first pad is different from the size of the second pad in plan view,
The semiconductor chip, wherein the size of the first opening is the same as the size of the second opening in plan view. A rectangular semiconductor chip,
The semiconductor chip is
a first pad;
a first lead-out wiring portion integrally formed with the first pad and connected to an underlying wiring via a first contact;
an inclined portion provided at a connecting portion between the first pad and the first lead-out wiring portion;
a surface protection film having a first opening covering the first lead-out wiring portion and exposing a portion of the surface of the first pad;
has
a center position of a width of the first lead-out wiring portion is shifted from a center position of a side to which the first lead-out wiring portion is connected, among a plurality of sides forming the first pad;
A connection angle of a connection portion between the first pad and the first lead-out wiring portion is composed of two obtuse angles,
The first pad has a rectangular shape in plan view,
Among the plurality of sides forming the first pad, the width of the covered region of the surface protective film covering one side of the first pad is the width of the other side of the first pad which is the farthest from the edge of the semiconductor chip. A semiconductor chip having a width larger than the width of the covered area of the surface protective film covering one side. A rectangular semiconductor chip,
The semiconductor chip is
A first pad having a first side extending along a first direction and a second side extending along the first direction and positioned on an extension line of the first side When,
A third side extending along a second direction orthogonal to the first direction in plan view, and a fourth side extending along the second direction and facing the third side a first lead-out wiring portion formed integrally with the first pad and connected to a lower layer wiring via a first contact;
a surface protection film having a first opening covering the first lead-out wiring portion and exposing a portion of the surface of the first pad;
has
In the first direction, the length of the first side is longer than the length of the second side,
The first side and the third side are different from the first direction and the second direction in plan view and extend along a third direction from one of the first side and the third side to the other. are connected to each other via existing fifth sides,
The second side and the fourth side are different from the first direction and the second direction in plan view and extend along a fourth direction from one of the second side and the fourth side to the other. are connected to each other via existing sixth sides,
an exterior angle formed by the first side and the fifth side is greater than 90 degrees,
an exterior angle formed by the second side and the sixth side is greater than 90 degrees,
The first pad has a rectangular shape in plan view,
Among the plurality of sides forming the first pad, the width of the covered region of the surface protective film covering one side of the first pad is the width of the other side of the first pad which is the farthest from the edge of the semiconductor chip. A semiconductor chip having a width larger than the width of the covered area of the surface protective film covering one side. The semiconductor chip according to claim 2 or 4,
an external angle formed by the third side and the fifth side is greater than 90 degrees,
The semiconductor chip, wherein an exterior angle formed by the fourth side and the sixth side is greater than 90 degrees. In the semiconductor chip according to any one of claims 2, 4 and 5,
The semiconductor chip, wherein the length of the fifth side is longer than the length of the sixth side. In the semiconductor chip according to any one of claims 2 and 4 to 6,
The semiconductor chip, wherein the width of the first lead-out wiring portion is shorter than the length of the first side. In the semiconductor chip according to any one of claims 2 and 4 to 7,
The semiconductor chip, wherein the width of the first lead-out wiring portion is longer than the length of the second side. In the semiconductor chip according to any one of claims 1 to 8,
The semiconductor chip, wherein the first pad is located between the edge of the semiconductor chip and the first lead wiring portion in a plan view. In the semiconductor chip according to any one of claims 1 to 9,
A semiconductor chip in which no other pad is formed between a corner portion of the semiconductor chip and the first pad in plan view. In the semiconductor chip according to claim 2 ,
a third pad formed adjacent to the second pad along an edge of the semiconductor chip;
a third opening exposing a part of the surface of the third pad is formed in the surface protective film;
The size of the third opening is the same as the size of the first opening and the size of the second opening in plan view,
The semiconductor device, wherein the distance between the first opening and the second opening in the first direction is the same as the distance between the second opening and the third opening in the first direction in a plan view. chips. In the semiconductor chip according to any one of claims 1 to 11,
A semiconductor chip, further comprising a second lead-out wiring section formed integrally with the first pad and connected to a lower layer wiring via a second contact. 13. The semiconductor chip of claim 12,
The semiconductor chip, wherein the second lead wiring portion extends along the edge of the semiconductor chip. In the semiconductor chip according to any one of claims 1 to 13,
The semiconductor chip, wherein the film thickness of the first pad is thicker than the film thickness of the surface protection film in a cross-sectional view. 15. The semiconductor chip of claim 14,
The surface protective film is
a silicon oxide film;
a silicon nitride film formed on the silicon oxide film;
has
The film thickness of the first pad is thicker than the sum of the film thickness of the silicon oxide film and the film thickness of the silicon nitride film in a cross-sectional view.
semiconductor chip. 16. The semiconductor chip of claim 15,
The first pad is
a first barrier conductor film;
an aluminum film formed on the first barrier conductor film;
a second barrier conductor film formed on the aluminum film;
has
the second barrier conductor film has a titanium nitride film,
The semiconductor chip, wherein the aluminum film is exposed from the first opening. 17. The semiconductor chip of claim 16,
The semiconductor chip, wherein the silicon nitride film covers the side surface of the silicon oxide film and the side surface of the second barrier conductor film in the first opening. In the semiconductor chip according to any one of claims 1 to 17,
a seal ring formed inside an edge of the semiconductor chip in plan view;
a dummy pattern formed outside the seal ring and on the edge side of the semiconductor chip;
A semiconductor chip, further comprising: 19. The semiconductor chip of claim 18,
The semiconductor chip, wherein the dummy pattern is not connected to a fixed potential. 20. The semiconductor chip according to claim 18 or 19,
The semiconductor chip, wherein the surface protection film covers the seal ring. In the semiconductor chip according to any one of claims 1 to 20,
The semiconductor chip, wherein the width of the first lead-out wiring section is shorter than the length of the side to which the first lead-out wiring section is connected, among the plurality of sides forming the first pad.

Images