JPH01298731A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01298731A JPH01298731A JP63129754A JP12975488A JPH01298731A JP H01298731 A JPH01298731 A JP H01298731A JP 63129754 A JP63129754 A JP 63129754A JP 12975488 A JP12975488 A JP 12975488A JP H01298731 A JPH01298731 A JP H01298731A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pads
- row
- rows
- bonding
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000008188 pellet Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
- H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は半導体装置に関し、特に、ペレットと外部リー
ドとを電気的に接続するためのボンティングパッドの形
状を改良した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which the shape of a bonding pad for electrically connecting a pellet to an external lead is improved.
［従来の技術］
半導体装置は、例えば、シリコン基板に多数の回路素子
を作り込み、これらの回路素子を、基板上に形成された
金属配線層により相互に接続して所定の回路機能を有す
るように構成されたペレット及びこのペレットを納める
パッケージにより構成されている。また、ペレットとパ
ッケージの外部リードとを電気的に接続するために、ペ
レット上に多数のボンディングパッドを設け、これらの
ボンディングパッドとパッケージの対応する外部リード
とをアルミニウム線又は金線等の金属細線で接続してい
る。[Prior Art] Semiconductor devices are manufactured by, for example, fabricating a large number of circuit elements on a silicon substrate and interconnecting these circuit elements with a metal wiring layer formed on the substrate to have a predetermined circuit function. It consists of pellets and a package containing the pellets. In addition, in order to electrically connect the pellet and the external lead of the package, a large number of bonding pads are provided on the pellet, and these bonding pads and the corresponding external lead of the package are connected using thin metal wires such as aluminum wire or gold wire. It is connected with
第５図に示すように、半導体装置はその平面形状が正方
形をなしており、その表面近傍に回路素子及び回路素子
を相互に接続する金属細線が形成され、またその周辺に
は多数のボンディングパッドが形成されている。なお、
第５図ではこれらの構成要素の図示を省略し、ペレット
の外形のみを示しである。As shown in FIG. 5, a semiconductor device has a square planar shape, and near its surface are formed circuit elements and thin metal wires that interconnect the circuit elements, and around these are many bonding pads. is formed. In addition,
In FIG. 5, illustration of these components is omitted and only the external shape of the pellet is shown.
第６図は、第５図において１点鎖線Ａで示す領域中のボ
ンディングパッドの配列状態を示す平面図である。以下
に、第６図を参照して、第１の従来例について説明する
。FIG. 6 is a plan view showing the arrangement of bonding pads in the area indicated by the dashed line A in FIG. The first conventional example will be described below with reference to FIG.
半導体基板１１は、その表面近傍に多数の回路素子が形
成され、且つ、その表面がパッシベーション膜で覆われ
ている。そして、ペレット上面の外縁部においては、ペ
レット端辺１２に沿って矩形（例えば、正方形）のボン
ディングパッド６２が所定間隔を置いて１列に設けられ
ている。また、各ボンディングパッド６２からは、この
ボンディングパッド６２とペレット内部の対応する回路
素子等とを接続する帯状の内部接線配線６３がペレット
内方へと延びている。A large number of circuit elements are formed near the surface of the semiconductor substrate 11, and the surface is covered with a passivation film. At the outer edge of the upper surface of the pellet, rectangular (for example, square) bonding pads 62 are provided in a row at predetermined intervals along the pellet edge 12. Further, from each bonding pad 62, a band-shaped internal tangential wiring 63 that connects this bonding pad 62 and a corresponding circuit element, etc. inside the pellet extends inside the pellet.
ところで、近時の半導体装置の大規模化及び多機能化に
伴い、必要とされるボンディングパッドの数が格段に増
加する傾向にある。この場合、上述した第１の従来例の
ようなボンディングパッドを１列に並べる方式を採ると
、ボンディングパッド数の増加に応じてペレットサイズ
が必然的に大きくなる。このため、ペレットサイズを決
定する要因に対して、内部の回路素子数よりもボンディ
ングパッド数が支配的となるので、極めて不経済となる
。Incidentally, as semiconductor devices have recently become larger in scale and more multifunctional, the number of required bonding pads has tended to increase significantly. In this case, if a method of arranging bonding pads in a row as in the first conventional example described above is adopted, the pellet size will inevitably increase as the number of bonding pads increases. For this reason, the number of bonding pads becomes more dominant than the number of internal circuit elements as a factor in determining the pellet size, which is extremely uneconomical.
そこで、最近は、上述のような回路設計上の不都合を回
避するために、ボンディングパッドを複数列に並べる方
式が採用されつつある。第７図はボンディングパッドを
２列構成とした第２の従来例を示す平面図であり、同図
を参照して第２の従来例について説明する。なお、第７
図において第６図と同一物には同一符号を付してその説
明を省略する。Therefore, recently, in order to avoid the above-mentioned inconveniences in circuit design, a method of arranging bonding pads in multiple rows is being adopted. FIG. 7 is a plan view showing a second conventional example in which bonding pads are arranged in two rows, and the second conventional example will be explained with reference to this figure. In addition, the seventh
Components in the figure that are the same as those in FIG. 6 are designated by the same reference numerals, and their explanations will be omitted.
半導体基板１１の上面外縁部には、ペレット端辺１２に
沿って、正方形状の１列目のボンディングパッド７３が
所定間隔を置いて配設されている。On the outer edge of the upper surface of the semiconductor substrate 11, a first row of square bonding pads 73 are arranged at predetermined intervals along the pellet edge 12.
また、１タリ目のボンディングパッド７３よりもペレッ
ト内側には所定間隔を置いて、この１列目のボンディン
グパッド７３に対して千鳥状に、２列目のボンディング
パッド７５が設けられている。Further, a second row of bonding pads 75 are provided in a staggered manner with respect to the first row of bonding pads 73 at a predetermined interval inside the pellet from the first row of bonding pads 73.
そして、これらの１列目及び２列目のボンディングパッ
ド７３．７５からは、夫々内部接続配線７４．７６がペ
レット内方へと延びている。Internal connection wiring lines 74.76 extend inward from the bonding pads 73.75 in the first and second rows, respectively.
第８図は第７図に示した第２の従来例における１列目及
び２列目のボンディングパッドの相互の位置関係を具体
的に示す平面図である。FIG. 8 is a plan view specifically showing the mutual positional relationship of the bonding pads in the first and second rows in the second conventional example shown in FIG.
このボンディングパッドを複数列に並べる場合において
は、各列のボンディングパッドの面積及び前後のボンデ
ィングパッド間の間隔は、信頼性、ボンディング装置能
力及びその他の条件を考慮して、次のように設定されて
いる。即ち、１列目及び２タリ目のボンディングパッド
７３．７５はいずれも１辺の長さが約１００μｍである
こと前提としている。また、１タリ目のボンディングパ
ッド７３同士並びに１列目及び２列目のボンディングパ
ッド７３．７５間の間隔はいずれも約５０μｍであるこ
とを前提としている。When these bonding pads are arranged in multiple rows, the area of the bonding pads in each row and the spacing between the front and rear bonding pads are set as follows, taking into consideration reliability, bonding equipment capacity, and other conditions. ing. That is, it is assumed that each side of the bonding pads 73 and 75 in the first and second rows has a length of approximately 100 μm. Further, it is assumed that the distance between the first bonding pads 73 and between the bonding pads 73 and 75 in the first and second rows is approximately 50 μm.
このため、１列目のボンディングパッド７３の中心０３
間の距Ｈｂは約１５０μｍであり、また、１タリ目のボ
ンディングパッド７３と、２列目のホ゛ンディングパッ
ド７５との中心Ｏ９，０４間の距離Ｃは約１６８μｍと
なる。従って、１列目のボンディングパッド７３の配列
方向の中心線と２列目のボンディングパッド７５の配列
方向の中心線との間の距ｔｌｌｉ Ｌ ２は約１５０μ
ｍとなる。Therefore, the center 03 of the bonding pad 73 in the first row
The distance Hb between them is approximately 150 μm, and the distance C between the centers O9 and 04 of the first bonding pad 73 and the second row bonding pad 75 is approximately 168 μm. Therefore, the distance tlli L 2 between the center line in the arrangement direction of the bonding pads 73 in the first row and the center line in the arrangement direction of the bonding pads 75 in the second row is approximately 150μ.
m.
［発明が解決しようとする課題１
しかしながら、ボンディングパッドを複数列に並べた従
来の半導体装置においては、次のような問題点がある。[Problem to be Solved by the Invention 1] However, conventional semiconductor devices in which bonding pads are arranged in multiple rows have the following problems.
即ち、１列目及び２列目のボンディングパッド７３．７
５はいずれも矩形の形状を有するので、所定のボンディ
ング特性を満たす必要上、１列目及び２列目のボンディ
ングパッド７３．７５間に前述の如く約５０μｍ以上の
間隔を設ける必要がある。従って、半導体装置の大規模
化及び多機能化に伴い、ボンディングパッド数が増加し
た場合に、そのボンディングパッドを２列に配置しても
、ボンディングパッドが配置されるべき領域の面積はボ
ンディングパッドを１列に並べた場合と略々同一であり
、この従来技術においてもペレットサイズの大型化を阻
止し得ない。That is, the first and second row bonding pads 73.7
Since both pads 5 have a rectangular shape, it is necessary to provide a gap of about 50 μm or more between the bonding pads 73 and 75 in the first and second rows, as described above, in order to satisfy predetermined bonding characteristics. Therefore, when the number of bonding pads increases as semiconductor devices become larger and more multifunctional, even if the bonding pads are arranged in two rows, the area where the bonding pads should be arranged is smaller than that of the bonding pads. This is almost the same as when the pellets are arranged in one row, and even in this conventional technique, the pellet size cannot be prevented from increasing.
本発明はかかる問題点に鑑みてなされたものであって、
ボンディングパッド領域を縮小させることができ、これ
に伴いペレット面積の減少を実現し得る。半導体装置を
提供することを目的とする。The present invention has been made in view of such problems, and includes:
The bonding pad area can be reduced, and the pellet area can accordingly be reduced. The purpose is to provide semiconductor devices.
［課題を解決するための手段１
本発明に係る半導体装置は、ペレットと外部リードとを
電気的に接続するためのボンディングパッドを有する半
導体装置において、前記ボンディングパッドは前記ペレ
ットの端辺に沿ってその少なくとも一部の領域で複数列
設けられ、列を異ならせて対向するボンディングパッド
はその対向縁側が対向方向に突出し、一方の列のボンデ
ィングパッドの突出部と他方の列のボンディングパッド
の突出部とを列の延長方向に交互に位置させてボンディ
ングパッドを配置してあることを特徴とする。[Means for Solving the Problems 1] A semiconductor device according to the present invention has a bonding pad for electrically connecting a pellet and an external lead, wherein the bonding pad is formed along an edge of the pellet. A plurality of rows are provided in at least a part of the area, and opposing edges of the bonding pads that are arranged in different rows protrude in opposite directions, and the protrusions of the bonding pads in one row and the protrusions of the bonding pads in the other row The bonding pads are arranged alternately in the extending direction of the rows.
［作用］
以Ｐのように構成された本発明によれば、ボンディング
パッドはペレットの端辺に沿ってその少なくとも一部の
領域で複数列設けられ、列を異ならせて対向するボンデ
ィングパッドはその対向縁側が対向方向に突出し、一方
の列のボンディングパッドの突出部と他方の列のボンデ
ィングパッドの突出部とを列の延長方向に交互に位置さ
せてボンディングパッドを配置しているので、所望のボ
ンディング特性を得るための所定間隔を維持した状態で
、ボンディングパッドの列間の間隔を小さくすることが
でき、ボンディングパッド領域を縮小させることができ
る。[Function] According to the present invention configured as described below, the bonding pads are provided in multiple rows in at least a part of the edge of the pellet, and the bonding pads facing each other in different rows The bonding pads are arranged such that the opposing edges protrude in opposite directions, and the protruding parts of the bonding pads in one row and the protruding parts of the bonding pads in the other row are alternately positioned in the extending direction of the rows, so that the desired While maintaining a predetermined spacing for obtaining bonding characteristics, the spacing between the rows of bonding pads can be reduced, and the bonding pad area can be reduced.
［実施例］
以下、添付の図面を参照して、本発明の実施例について
具体的に説明する。[Examples] Examples of the present invention will be specifically described below with reference to the accompanying drawings.
第１図は本発明を２列構成のボンディングパッドを有す
る半導体装置に適用した第１の実施例を示す要部の平面
図である。なお、第１図において第６図と同一物には同
一符号を付してその説明を省略する。FIG. 1 is a plan view of essential parts showing a first embodiment in which the present invention is applied to a semiconductor device having two rows of bonding pads. Components in FIG. 1 that are the same as those in FIG. 6 are designated by the same reference numerals, and their explanations will be omitted.
半導体基板１１上の上面外縁部には、ペレット端辺１２
に沿ってボンディングパッドが２列に所定間隔を置いて
多数設けられている。即ち、ペレット端辺１２側には１
列目のボンディングパッド１３が所定間隔を置いて所定
散設けられ、また、この１列目のボンディングパッド１
３の後方には２列目のボンディングパッド１５が所定数
形成されている。A pellet edge 12 is formed on the outer edge of the upper surface of the semiconductor substrate 11.
A large number of bonding pads are provided in two rows along the line at predetermined intervals. That is, 1 on the pellet edge 12 side.
The bonding pads 13 in the row are provided at a predetermined distance at predetermined intervals, and the bonding pads 13 in the first row
A predetermined number of bonding pads 15 in the second row are formed behind the pads 3.
これらの１列目及び２列目のボンディングパッド１３．
１５はいずれも相対する側が対向方向に向けて略々楔形
に突出しており、いずれも同一形状の五角形を成してい
る。These first and second row bonding pads 13.
15, the opposite sides thereof protrude in a substantially wedge shape toward the opposite direction, and all of them form the same pentagonal shape.
そして、一方の列のボンディングパッド１３又は１５の
楔形突出部は、他方の列のボンディングパッド１５又は
１３間に延出しており、従って、１列目のボンディング
パッド１３の突出部と２列目のボンディングパッド１５
の突出部とは、その列の延長方向に沿って交互に位置し
ている。The wedge-shaped protrusions of the bonding pads 13 or 15 in one row extend between the bonding pads 15 or 13 in the other row, so that the protrusions of the bonding pads 13 in the first row and the wedge-shaped protrusions in the second row Bonding pad 15
The protrusions are located alternately along the extending direction of the row.
また、１列目及び２列目のボンディングパッド１３．１
５のペレット内側縁部からは、これらのボンディングパ
ッド１３．１５と夫々ペレット内部の対応する回路素子
等とを接続する帯状の内部接続配線１４．１６がペレッ
ト内方へと延びている。Also, bonding pads 13.1 in the first and second rows
From the inner edge of the pellet No. 5, band-shaped internal connection wiring lines 14.16 which connect these bonding pads 13.15 and corresponding circuit elements inside the pellet, respectively, extend into the pellet.
このように、本実施例によれば、１列目及び２夕り目の
ボンディングパッド１３．１５において、相対する側が
いずれも略楔形の形状を成しているので、所望のボンデ
ィング特性を得るための所定間隔（約５０μｍ）を維持
した状態で、１列目及び２列目のボンディングパッド１
３．１５を前述の第２の従来例（第７図参照）に比して
、近接して配置することができる。As described above, according to this embodiment, since the opposing sides of the bonding pads 13.15 in the first row and the second row each have a substantially wedge-shaped shape, it is possible to obtain the desired bonding characteristics. bonding pads 1 in the first and second rows while maintaining a predetermined interval (approximately 50 μm).
3.15 can be arranged closer to each other than in the second conventional example (see FIG. 7).
第２図は第１図に示した第１の実施例における１列目及
び２列目のボンディングパッド１３．１５の相互の位置
関係を具体的に示す平面図である。FIG. 2 is a plan view specifically showing the mutual positional relationship of the bonding pads 13, 15 in the first and second rows in the first embodiment shown in FIG.
前述のように、信頼性、ボンディング装置能力及びその
他の条件を考慮する必要上、１列目及び２列目のボンデ
ィングパッド１３．１５の面積はいずれも実質的に１０
０ＪＪ、ｍＸ １００μｍに、また、１列目のボンディ
ングパッド１３同士並びに１列目及び２列目のボンディ
ングパッド１３．１５間の間隔はいずれも約５０ ノ１
ｍに設定される。As mentioned above, due to the need to consider reliability, bonding equipment capacity, and other conditions, the areas of the bonding pads 13 and 15 in the first and second rows are both substantially 10.
0JJ, mX 100 μm, and the spacing between the bonding pads 13 in the first row and between the bonding pads 13 and 15 in the first and second rows is about 50 mm.
m.
このため、１列目のボンディングパッド１３の中心０１
間の距離ａ及び１列目のボンディングパッド１３の中心
０１と２列目のボンディングバッド１５の中心０□との
間の距離ａは約１５０μｍとなる。この場合に、本実施
例においては、１列目のボンデインクパッド１３の中心
０１を相互に結ぶ線と２列目のボンディングパッド１５
の中心０２を相互に結ぶ線との間の距離Ｌｌ （列間
の間隔）は約１３０μｍとなる。故に、第７図及び第８
図に示した第２の従来例に比して１列目及び２列目のボ
ンディングパッド１３．１５間の間隔を約２０μｍ短く
することでき、これにより、ホンディングパッドを配設
すべき領域をその分たけ縮小することができる。Therefore, the center 01 of the bonding pad 13 in the first row
The distance a between the center 01 of the bonding pad 13 in the first row and the center 0□ of the bonding pad 15 in the second row is about 150 μm. In this case, in this embodiment, a line connecting the centers 01 of the bonding ink pads 13 in the first row and the bonding pads 15 in the second row are connected to each other.
The distance Ll (distance between rows) between the lines connecting the centers 02 of the rows 02 to each other is approximately 130 μm. Therefore, Figures 7 and 8
Compared to the second conventional example shown in the figure, the distance between the bonding pads 13. It can be reduced by that amount.
第３図は本発明を２列構成のボンデイングパ・ンドを有
する半導体装置に適用した第２の実施例を示す要部の平
面図である。なお、第３図において、第１図と同一物に
は同一符号を付してその説明を省略する。FIG. 3 is a plan view of a main part showing a second embodiment in which the present invention is applied to a semiconductor device having bonding pads arranged in two rows. In FIG. 3, the same components as those in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.
本実施例において、１列目及び２列目のボンディングパ
ッド２３．２５は相対する側の形状がいずれも略台形で
あり、且つ、相反する側の形状がいずれも矩形状である
。このため、１列目及び２列目のボンディングパッド２
３．２５は実質的に同一の六角形をなす。In this embodiment, the bonding pads 23 and 25 in the first and second rows have substantially trapezoidal shapes on opposing sides, and rectangular shapes on opposite sides. Therefore, the bonding pads 2 of the first and second rows
3.25 form substantially identical hexagons.
また、これらの１列目及び２列目のボンディングパッド
２３．２５の後側からは、夫々帯状の内部接続配線２４
．２６がペレット内方へと延びており、ペレット端辺１
２側のボンディングパッド２３の内部接続配線２４は内
側のボンディングベツド２５間の間隙を通るように形成
されている。Further, from the rear side of the bonding pads 23 and 25 in the first and second rows, respectively, strip-shaped internal connection wirings 24 are connected.
．． 26 extends inward to the pellet edge 1.
The internal connection wiring 24 of the bonding pad 23 on the second side is formed to pass through the gap between the bonding pads 25 on the inside.
本実施例の場合、１列目及び２列目のボンディングパッ
ド２３．２５において、相対する側がいずれも略台形と
なっているので、前述の第１の実施例の場合と同様に、
所定間隔を維持した状態で、１列目及び２列目のボンデ
ィングパッド２３，２５を相互に一層近接して配置する
ことができる。In the case of this embodiment, since the opposing sides of the bonding pads 23 and 25 in the first and second rows are both substantially trapezoidal, as in the case of the first embodiment described above,
The bonding pads 23, 25 in the first and second rows can be arranged closer to each other while maintaining a predetermined spacing.
第４図は本発明を３列構成のボンディングパッドを有す
る半導体装置に適用した第３の実施例を示す要部の平面
図である。なお、第４図において、第１図及び第３図と
同一物には同一符号を付してその説明を省略する。FIG. 4 is a plan view of essential parts showing a third embodiment in which the present invention is applied to a semiconductor device having three rows of bonding pads. Note that in FIG. 4, the same parts as in FIGS. 1 and 3 are given the same reference numerals, and their explanations will be omitted.
本実施例においては、１列目のボンディングパッド３３
と、２列目のボンディングパッド３５とが、また２タリ
目のボンデインクパッド３５と、３列目のボンディング
パッド３７とが、いずれも相互に千鳥状に配置されてお
り、従って、１列目及び３列目のボンディングパッド３
３．３７は端辺に沿う方向に整列している。そして、１
列目のボンディングパッド３３は前半分が矩形状である
と共に後半分が略楔形である。また、２列目及び３夕り
目のボンディングパッド３５．３７はいずれも前半分及
び後半分が夫々楔形で実質的に正六角形を成している。In this embodiment, the bonding pad 33 in the first row is
The bonding pads 35 in the second row, the bonding pads 35 in the second row, and the bonding pads 37 in the third row are all arranged in a staggered manner. and third row bonding pad 3
3.37 are aligned in the direction along the edge. And 1
The bonding pad 33 in the row has a front half in a rectangular shape and a rear half in a substantially wedge shape. Further, the bonding pads 35 and 37 in the second and third rows each have a wedge-shaped front half and a rear half, respectively, and form a substantially regular hexagon.
このため、１列目及び２列目のボンディングパッド３３
．３５並びに２列目及び３列目のボンディングパッド３
５．３７において、相対する側の形状は夫々略楔形を成
している。Therefore, the bonding pads 33 in the first and second rows
．． 35 and second and third row bonding pads 3
5.37, the shapes of the opposing sides are each substantially wedge-shaped.
また、これらの１列目、２列目及び３列目のボンディン
グパッド３３，３５．３７の後側からは、夫々帯状の内
部接続配線３４，３６．３８がペレット内方へと延びて
いる。Further, from the rear sides of the bonding pads 33, 35, 37 in the first, second, and third rows, band-shaped internal connection wirings 34, 36, 38 extend inward to the pellet, respectively.
従って、本実施例によれば、１列目及び２列目のボンデ
インクパッド３３．３５並びに２列目及び３タリ目のボ
ンディングパッド３５．３７は、いずれも所定間隔（約
５０μｍ）を維持した状態で、相互に近接して配置する
ことができる。Therefore, according to this embodiment, the bonding ink pads 33.35 in the first and second rows and the bonding pads 35.37 in the second and third rows maintain a predetermined interval (approximately 50 μm). can be placed in close proximity to each other.
［発明の効果］
以上説明したように、本発明によれば、ボンディングパ
ッドはペレットの端辺に沿ってその少なくとも一部の領
域で複数列設けられ、列を異ならせて対向するボンディ
ングパッドはその対向縁側が対向方向に突出し、一方の
列のボンディングパッドの突出部と他方の列のボンディ
ングパッドの突出部とを列の延長方向に交互に位置させ
てボンディングパッドを配置しているので、所望のボン
ディング特性を得るための所定間隔を維持した状態で、
列間の間隔を小さくし、ホンディングパッド列を相互に
近接して配置することができる。このため、ボンディン
グパッドを形成する領域を縮小することができ、また同
時に、ペレット面積を小さくすることができる。[Effects of the Invention] As explained above, according to the present invention, bonding pads are provided in multiple rows along the edge of the pellet in at least a part of the region, and the bonding pads facing each other in different rows are The bonding pads are arranged such that the opposing edges protrude in opposite directions, and the protruding parts of the bonding pads in one row and the protruding parts of the bonding pads in the other row are alternately positioned in the extending direction of the rows, so that the desired While maintaining the predetermined spacing to obtain bonding characteristics,
The spacing between rows can be reduced and the rows of bonding pads can be placed closer to each other. Therefore, the area in which the bonding pads are formed can be reduced, and at the same time, the area of the pellet can be reduced.
更に、ボンディングパッドの形状、面積及びボンディン
グパッド間の間隔等に関する設計上の制約は、信頼性、
素子構造、ボンディング方法（ＮＴＣ，ＵＳＢ等）及び
ボンディング装置の性能等によって種々に変更されるが
、本発明の場合は、ボンディングパッドの突出部が、例
えば、楔形又は台形等の種々の変形が可能であるので、
従来例に比して、より柔軟性があり、適応性が優れてい
る。Furthermore, design constraints regarding bonding pad shape, area, spacing between bonding pads, etc.
Although various modifications may be made depending on the element structure, bonding method (NTC, USB, etc.), performance of the bonding device, etc., in the case of the present invention, the protrusion of the bonding pad can be modified in various ways, such as wedge-shaped or trapezoidal. So,
It is more flexible and adaptable than conventional methods.
第１図は本発明を２列構成のボンディングパッドを有す
る半導体装置に適用した第１の実施例を示す要部の平面
図、第２図は第１の実施例における１列目及び２列目の
ボンディングパッドの相互の位置関係を具体的に示す平
面図、第３図は本発明を２列構成のボンディングパッド
を有する半導体装置に適用した第２の実施例を示す要部
の平面図、第４図は本発明を３列構成のボンディングパ
ッドを有する半導体装置に適用した第３の実施例を示す
要部の平面図、第５図は従来の半導体装置のペレットを
模式的に示す平面図、第６図は第５図においてＡで示す
領域中の１列構成のボンディングパッドを示す平面図、
第７図は従来の２列構成のボンディングパッドを示す要
部の平面図、第８図は第７図における１列目及び２列目
のボンディングパッドの相互の位置関係を具体的に示す
平面図である。
１１−半導体基板、１２；ペレット端辺、１３゜２３．
３３，７３．１タリ目のボンディングパッド、１４．１
６，２４，２６，３４，３６，３８，６３．７４，７６
、内部接続配線、１５，２５，３５．７５；２夕ＩＩ
目のボンディングパッド、３７；３列目のボンディング
パッド、６２；ボンディングパッドFIG. 1 is a plan view of a main part showing a first embodiment in which the present invention is applied to a semiconductor device having two rows of bonding pads, and FIG. 2 is a plan view of the first and second rows in the first embodiment. FIG. 3 is a plan view specifically showing the mutual positional relationship of the bonding pads in FIG. FIG. 4 is a plan view of a main part showing a third embodiment in which the present invention is applied to a semiconductor device having three rows of bonding pads, and FIG. 5 is a plan view schematically showing a pellet of a conventional semiconductor device. FIG. 6 is a plan view showing a single row of bonding pads in the area indicated by A in FIG.
FIG. 7 is a plan view of essential parts showing a conventional two-row configuration of bonding pads, and FIG. 8 is a plan view specifically showing the mutual positional relationship of the bonding pads in the first and second rows in FIG. It is. 11-Semiconductor substrate, 12; Pellet edge, 13°23.
33, 73.1st bonding pad, 14.1
6, 24, 26, 34, 36, 38, 63. 74, 76
, Internal connection wiring, 15, 25, 35.75; 2 evening II
Eye bonding pad, 37; 3rd row bonding pad, 62; Bonding pad
Claims (1)
のボンディングパッドを有する半導体装置において、前
記ボンディングパッドは前記ペレットの端辺に沿ってそ
の少なくとも一部の領域で複数列設けられ、列を異なら
せて対向するボンディングパッドはその対向縁側が対向
方向に突出し一方の列のボンディングパッドの突出部と
他方の列のボンディングパッドの突出部とを列の延長方
向に交互に位置させてボンディングパッドを配置してあ
ることを特徴とする半導体装置。(1) In a semiconductor device having bonding pads for electrically connecting a pellet and an external lead, the bonding pads are provided in a plurality of rows in at least a part of the edge of the pellet, and The opposing edge sides of the bonding pads that are different and opposite to each other protrude in opposite directions, and the protrusions of the bonding pads in one row and the protrusions of the bonding pads in the other row are alternately positioned in the extending direction of the rows to form the bonding pads. A semiconductor device characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63129754A JPH01298731A (en) | 1988-05-27 | 1988-05-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63129754A JPH01298731A (en) | 1988-05-27 | 1988-05-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01298731A true JPH01298731A (en) | 1989-12-01 |
Family
ID=15017368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63129754A Pending JPH01298731A (en) | 1988-05-27 | 1988-05-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01298731A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04364051A (en) * | 1991-06-11 | 1992-12-16 | Rohm Co Ltd | Semiconductor device |
| US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
| US5834849A (en) * | 1996-02-13 | 1998-11-10 | Altera Corporation | High density integrated circuit pad structures |
| US5925935A (en) * | 1996-10-01 | 1999-07-20 | Samsung Electronics Co., Ltd. | Semiconductor chip with shaped bonding pads |
| EP0966031A3 (en) * | 1998-06-16 | 2000-05-10 | Shinko Electric Industries Co. Ltd. | Substrate for mounting a semiconductor chip |
| US6784558B2 (en) * | 1999-12-30 | 2004-08-31 | Intel Corporation | Semiconductor device inlcluding optimized driver layout for integrated circuit with staggered bond pads |
| US7317244B2 (en) | 2002-01-15 | 2008-01-08 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method thereof |
| EP2942809A1 (en) * | 2014-04-14 | 2015-11-11 | Renesas Electronics Corporation | Semiconductor device with a plurality of pads and method of manufacturing the same |
| JP2018029193A (en) * | 2017-09-21 | 2018-02-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
1988
- 1988-05-27 JP JP63129754A patent/JPH01298731A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04364051A (en) * | 1991-06-11 | 1992-12-16 | Rohm Co Ltd | Semiconductor device |
| US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
| US5834849A (en) * | 1996-02-13 | 1998-11-10 | Altera Corporation | High density integrated circuit pad structures |
| US5925935A (en) * | 1996-10-01 | 1999-07-20 | Samsung Electronics Co., Ltd. | Semiconductor chip with shaped bonding pads |
| EP0966031A3 (en) * | 1998-06-16 | 2000-05-10 | Shinko Electric Industries Co. Ltd. | Substrate for mounting a semiconductor chip |
| US6281567B1 (en) | 1998-06-16 | 2001-08-28 | Shinko Electric Industries Co., Ltd. | Substrate for mounting semiconductor chip with parallel conductive lines |
| US6784558B2 (en) * | 1999-12-30 | 2004-08-31 | Intel Corporation | Semiconductor device inlcluding optimized driver layout for integrated circuit with staggered bond pads |
| US7317244B2 (en) | 2002-01-15 | 2008-01-08 | Oki Electric Industry Co., Ltd. | Semiconductor device and manufacturing method thereof |
| EP2942809A1 (en) * | 2014-04-14 | 2015-11-11 | Renesas Electronics Corporation | Semiconductor device with a plurality of pads and method of manufacturing the same |
| US9391035B2 (en) | 2014-04-14 | 2016-07-12 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US9761541B2 (en) | 2014-04-14 | 2017-09-12 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US10283458B2 (en) | 2014-04-14 | 2019-05-07 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US10923437B2 (en) | 2014-04-14 | 2021-02-16 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US11482498B2 (en) | 2014-04-14 | 2022-10-25 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US11810869B2 (en) | 2014-04-14 | 2023-11-07 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| JP2018029193A (en) * | 2017-09-21 | 2018-02-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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