JPS6286744A - Lsi chip - Google Patents

Abstract

PURPOSE:To realize miniaturization by a method wherein a conductive, auxiliary wiring pattern is provided on a passivation film formed on the top surface of an element. CONSTITUTION:A the ends of wiring patterns 5 on a substrate 6 whereto an LSI chip 1 is to be bonded, bonding sections 51 are provided corresponding to bump sections 3. At both ends of an auxiliary wiring pattern 4 on the LSI chip 1, bump section 41 are built and, on a substrate 6, bonding sections 51a and 51b are formed at the ends of wiring patterns 5a and 5b, corresponding to the bump sections 41. The bump sections 3 are respectively connected to the bonding sections 51 when the LSI chip 1 is installed on the substrate 6. In this process, the bump sections 41 of the auxiliary wiring pattern 4 are also connected to the bonding sections 51a and 51b. With the chip designed as such, a steric wiring can be made without using a rear-side wiring or jumper, facilitating the miniaturization of an electronic part incorporating an LSI chip.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an LSI chip in which a wiring pattern is provided on a passivation film.

<Conventional technology> As parts become smaller and thinner, the integration density of LSIs increases, and the wiring patterns of the substrates on which LSI chips are mounted are also becoming thinner, and there are various issues regarding how to route as many wires in a narrow space. No attempt has been made. If routing is not possible, backside wiring patterns using through-holes on the board or jumper wires are generally used, but measures such as changing the circuit configuration of the LSI or making the board larger are sometimes taken. .

<Problems to be Solved by the Invention> Backside wiring and jumper wires may not be possible due to space limitations, and even if possible, they require space and tend to increase the size of the board. Furthermore, changing the circuit configuration of the LSI itself is not easy and cannot be said to be an appropriate countermeasure.

The present invention focuses on such problems, and aims to make it possible to perform predetermined independent connections even when wiring cannot be routed on the board side by modifying the LSI chip side. It has been done.

<Means for Solving the Problems> In order to achieve the above object, the LSI chip of the present invention has a conductive layer on the surface of a passivation film such as a silicon dioxide film formed on the surface of the element to prevent moisture and impurities. Since the passivation film is insulating, this auxiliary wiring pattern is formed regardless of the circuit of the element.

FIG. 1 shows an example of the relationship between the auxiliary wiring pattern and the wiring pattern on the substrate side, in which 1 is a 7-lip chip LSI chip with a passivation film 2 formed on its surface, 3 is a bump portion thereof, 4 is an auxiliary wiring pattern provided on the passivation film 2; 5, indicated by a chain line, is a wiring pattern on the substrate side to which each bump portion 3 is bonded;
Reference numerals a, 5b, and 5c are other wiring patterns that are also formed on the substrate side.

<Function> In the case of a wiring pattern as shown in Figure 1, pattern 4 was conventionally used.
Even if it were necessary to connect between a and 4b, since the pattern 4c is located between them, the connection could not be made as is, and the connection was made separately via back wiring or a blank wire. On the other hand, in the case of the LSI chip 1 of the present invention, by providing the auxiliary wiring pattern 4 corresponding to the wiring patterns 5a, 5b, the wiring patterns 5a, 5b are bonded.
b are connected via the auxiliary wiring pattern 4. That is,
Insufficient or impossible portions of the wiring pattern on the board side are compensated for, and the auxiliary wiring pattern t acts as a three-dimensional connection just like a jumper wire.

<Example> An example shown in FIGS. 2 and 3 will be described below.

Note that the same parts as in FIG. 1 are designated by the same reference numerals.

In FIG. 2, reference numeral 6 denotes a substrate to which the LSI chip 1 is bonded, and bonding portions 51 are formed at the ends of each wiring pattern 5 in correspondence with the bump portions 3. Also, auxiliary wiring pattern 4 of LSI chip 1
Bump portions 41 are formed at both ends of the bump portion 41, and correspondingly,
Bonding portions 51a and 51b are formed at the ends of the wiring patterns 5a and 5b of the substrate 6, respectively. Because of this configuration, the LSI
By stacking the chip 1 on the substrate 6 and bonding it, each bump portion 3 is connected to each bonding portion 51, and the bump portion 41 of the auxiliary wiring pattern 4 is connected to the bonding portion 51a.

51b, and the predetermined connection is completed. In addition, L.S.
A constant distance corresponding to the height of the bump portions 3 and 41 is ensured between the I-chip 1 and the substrate 6, and the auxiliary wiring pattern 4 and the wiring pattern 5c do not come into contact with each other at the intersection.

(,) to (c) in Figure 3 are a-a'' in Figure 2, respectively.
FIG. 4 is a cross-sectional view taken along the line, bb' line, and e-C' line, showing the main part enlarged in the thickness direction, and further showing a part thereof enlarged in FIG. 4. . In the figure, 11 is an LSI
The main body 12 is a pad section provided in the formation part of the bump section 3, and the upper surface of the pad section 12 is covered with a passivation film 2.
is of the form rI1. It has not been. The bump portion 3 is formed by forming a vapor deposited film 13 on the pad portion 12, further applying copper plating 14, and applying solder plating 15 thereon. Further, the auxiliary wiring pattern 4 is formed by forming a vapor deposited film 13 in a predetermined shape on the passivation film 2, and further, for the bump portion 41, copper plating 14 is applied on the vapor deposited film 13, and solder plating 15 is applied thereon. formed by. In this way, the auxiliary wiring pattern 4 and its bump portion 41 are
It can be formed using a pattern mask or the like in the same procedure as the bump part 3 is formed on the SI main body 11, and wiring pads can also be used if necessary.

It should be noted that the above embodiments relate to a 7-lip chip type LSI chip in which 7-eighth down bonding is performed, and the present invention is suitable for such a 7-lip chip/2-lip type. This is possible by applying it to an LSI chip. In addition, in the example, the auxiliary wiring pattern is 1
Although it is a book, a plurality of books can be formed in an appropriate routing pattern as necessary.

<Effects of the Invention> As is clear from the description of the above embodiments, the L of the present invention
The SI chip has an auxiliary wiring pattern on the badge thin film on the surface of the element, making it possible to perform three-dimensional wiring routing that is difficult with only the wiring pattern on the board side, without using backside wiring or jumper wiring. can. Therefore, there is no need for extra space due to jumper wires, etc.
Or, there is no need for solutions such as increasing the size of the board, and LS
There are advantages such as it is easier to miniaturize electronic components using I chips, and there are fewer restrictions on the wiring pattern of the board and the circuit configuration of the LSI chip itself, making it easier to design.

[Brief explanation of drawings]

FIG. 1 is a plan view of an example of an LSI chip of the present invention, FIG. 2 is an exploded perspective view of an embodiment, and FIGS.
'I line, bb' line, Ce' line sectional views; Figure 4 is an enlarged sectional view of the main parts6

Claims (1)

[Claims] 1.L characterized in that a conductive auxiliary wiring pattern is provided on the passivation film formed on the surface of the element.
SI chip.