JPH0719165Y2 - Multi-chip structure - Google Patents
Multi-chip structureInfo
- Publication number
- JPH0719165Y2 JPH0719165Y2 JP16410488U JP16410488U JPH0719165Y2 JP H0719165 Y2 JPH0719165 Y2 JP H0719165Y2 JP 16410488 U JP16410488 U JP 16410488U JP 16410488 U JP16410488 U JP 16410488U JP H0719165 Y2 JPH0719165 Y2 JP H0719165Y2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- bumps
- bump
- chips
- printed board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Description
【考案の詳細な説明】 〔概要〕 第１と第２のチップを重ね合わせ、第１と第２のチップ
との接続が可撓性のプリント板のパターン配線によって
行うように形成されたマルチチップ構造に関し、 基板に於けるチップの実装効率を向上させると共に、軽
量化を図ることを目的とし、 第１のバンプが形成された第１のチップと、第２のバン
プが形成され、該第１のチップより外形の小さい第２の
チップと、パターン配線を有する可撓性のプリント板と
を備え、該第１のバンプと該第２のバンプとが同一方向
に配列されるよう該第１のチップの中央部に該第２のチ
ップが重ね合わせられると共に、該プリント板が該第２
のチップに重ね合わせられ、該第１と第２のバンプ間の
接続、および、該第１と第２のバンプのそれぞれに入出
力される信号の接続を行うリードが該パターン配線によ
って形成されるようにする。DETAILED DESCRIPTION OF THE INVENTION [Outline] A multi-chip formed by stacking first and second chips and connecting the first and second chips by pattern wiring of a flexible printed board. Regarding the structure, for the purpose of improving the mounting efficiency of a chip on a substrate and reducing the weight thereof, a first chip having a first bump formed thereon and a second bump are formed. Second chip having an outer shape smaller than that of the first chip and a flexible printed board having a pattern wiring, and the first bump and the second bump are arranged so as to be arranged in the same direction. The second chip is superposed on the central part of the chip, and the printed board is
Formed by the pattern wiring, the leads being overlaid on the chip and connecting the first and second bumps and connecting the signals input to and output from the first and second bumps respectively. To do so.
本考案は第１と第２のチップを重ね合わせ、第１と第２
のチップとの接続が可撓性のプリント板のパターン配線
によって行うように形成されたマルチチップ構造に関す
る。According to the present invention, the first and second chips are stacked and the first and second chips are stacked.
The present invention relates to a multi-chip structure formed such that the connection with the chip is performed by pattern wiring of a flexible printed board.
電子機器の構成に広く用いられている半導体回路網が形
成されたチップは、最近では、高密度実装化により小型
化が図られるようになった。Chips having a semiconductor circuit network, which are widely used in the construction of electronic devices, have recently been reduced in size by high-density mounting.
したがって、これらのチップを基板に実装する場合は、
チップの実装効率を良くすることで電子機器の構成が極
力小型化されるように形成されることが望まれる。Therefore, when mounting these chips on the board,
It is desired that the structure of the electronic device be formed as small as possible by improving the chip mounting efficiency.
従来は第４図の従来の説明図に示すように構成されてい
た。第４図の（ａ）（ｂ）は側面断面図である。Conventionally, it is configured as shown in the conventional explanatory view of FIG. 4A and 4B are side cross-sectional views.
第４図の（ａ）に示すように、パッケージ12にチップ１
が埋設され、ワイヤ13によってチップ１に接続されたリ
ード端子14が基板10に形成されたパッド10Aに半田付け
されることで実装されるように構成されていた。As shown in FIG. 4A, the chip 1 is placed in the package 12.
And the lead terminals 14 connected to the chip 1 by the wires 13 are soldered to the pads 10A formed on the substrate 10 to be mounted.
また、（ｂ）に示すように、チップ１にはバンプ３を設
け、バンプ３が基板11に形成されたパッド11Aに半田付
けされることで実装されるように形成される場合もあ
る。Further, as shown in (b), bumps 3 may be provided on the chip 1 and the bumps 3 may be mounted by being soldered to the pads 11A formed on the substrate 11.
この場合は、基板11がセラミック材によって形成され、
通常、熱膨張係数がチップ１とほぼ同等になるように形
成されている。In this case, the substrate 11 is made of a ceramic material,
Usually, the thermal expansion coefficient is formed to be substantially the same as that of the chip 1.
したがって、（ａ）（ｂ）のいづれの場合も、基板10,1
1には各々のチップ１に対応したパッド10A,11Aの配設が
必要となる。Therefore, in either case (a) or (b), the substrate 10,1
1 requires pads 10A and 11A corresponding to each chip 1 to be provided.
しかし、このような各々のチップ１に対応したパッド10
A,11Aの配設を基板10,11に形成し、基板10,11にチップ
１を併設する平面的な実装では基板10,11に多数のチッ
プ１を実装する場合、実装密度の向上を図るには限界が
あり、高実装密度化が得られない。However, such a pad 10 corresponding to each chip 1
In the planar mounting in which the arrangement of A and 11A is formed on the substrates 10 and 11 and the chips 1 are provided on the substrates 10 and 11, when a large number of chips 1 are mounted on the substrates 10 and 11, the mounting density is improved. There is a limit to this, and high packing density cannot be obtained.
特に、（ａ）に示すようなパッケージ12によって実装を
行う場合は、外形が大きくなり、かつ、重量が増加する
ことになる問題を有していた。In particular, when mounting is performed by the package 12 as shown in (a), there are problems that the outer shape becomes large and the weight increases.
そこで、本考案では、基板に於けるチップの実装効率を
向上させると共に、軽量化を図ることを目的とする。Therefore, an object of the present invention is to improve the mounting efficiency of the chip on the substrate and to reduce the weight.
第１図は本考案の原理説明図である。 FIG. 1 is an explanatory view of the principle of the present invention.
第１図に示すように、第１のバンプ３が形成された第１
のチップ１と、第２のバンプ４が形成され、該第１のチ
ップ１より外形の小さい第２のチップ２と、パターン配
線を有する可撓性のプリント板５とを備え、該第１のバ
ンプ３と該第２のバンプ４とが同一方向に配列されるよ
う該第１のチップ１の中央部に該第２のチップ２が重ね
合わせられると共に、該プリント板５が該第２のチップ
２に重ね合わせられ、該第１と第２のバンプ3,4間の接
続、および、該第１と第２のバンプ3,4のそれぞれに入
出力される信号の接続を行うリード６が該パターン配線
によって形成されるようにする。As shown in FIG. 1, a first bump 3 having a first bump 3 is formed.
Of the first chip 1, the second bump 4 is formed, the second chip 2 having a smaller outer shape than the first chip 1, and the flexible printed board 5 having the pattern wiring are provided. The second chip 2 is superposed on the central portion of the first chip 1 so that the bumps 3 and the second bumps 4 are arranged in the same direction, and the printed board 5 is the second chip. A lead 6 that is overlapped with the second bump 2 and that connects the first and second bumps 3 and 4 and connects signals input to and output from the first and second bumps 3 and 4, respectively. It is formed by pattern wiring.
このように構成することによって前述の課題は解決され
る。With this configuration, the above-mentioned problems can be solved.
即ち、第１のチップ１に形成された第１のバンプ３と、
第２のチップ２に形成された第２のバンプ４とが同一方
向に配列されるよう該第１のチップ１の中央部に該第２
のチップ２を重ね合わせ、更に、該第２のチップ２には
パターン配線を有する可撓性のプリント基板５を重ね合
わせることで該パターン配線によって該第１と第２のバ
ンプ3,4間の接続、および、該第１と第２のバンプ3,4の
それぞれに外部からの信号の接続を行うリードが形成さ
れるようにしたものである。That is, the first bumps 3 formed on the first chip 1,
The second bumps 4 formed on the second chip 2 are arranged in the same direction as the second bumps 4 on the central portion of the first chip 1.
Of the first and second bumps 3 and 4 are overlapped by the pattern wiring by stacking the chip 2 of the above, and further stacking the flexible printed circuit board 5 having the pattern wiring on the second chip 2. Leads are formed for connection and for connection of signals from the outside to the first and second bumps 3 and 4, respectively.
したがって、実装すべき基板には第１と第２のチップ1,
2が重ねられることで行われることになり、従来のチッ
プが実装面に併設することで平面に実装される場合に比
較して、実装スペースが約1/2となり、かつ、パッケー
ジなどが不要となり、軽量化および高密度実装化が図れ
ることになる。Therefore, the board to be mounted has the first and second chips 1, 2.
It will be done by stacking two, and compared to the case where a conventional chip is mounted side by side on the mounting surface and mounted on a flat surface, the mounting space will be about half and the package etc. will be unnecessary. Therefore, it is possible to achieve weight reduction and high-density mounting.
以下本考案を第２図および第３図を参考に詳細に説明す
る。第２図は本考案による一実施例の説明図で、（ａ）
は平面図，（ｂ）は（ａ）のA-A′断面図，（ｃ）は基
板に実装した時の要部側面図，第３図の（ａ）〜（ｃ）
は本考案のプリント板の製造工程図である。全図を通じ
て、同一符号は同一対象物を示す。Hereinafter, the present invention will be described in detail with reference to FIGS. 2 and 3. FIG. 2 is an explanatory view of an embodiment according to the present invention, (a)
Is a plan view, (b) is a cross-sectional view taken along the line AA 'of (a), (c) is a side view of essential parts when mounted on a substrate, and (a) to (c) of FIG.
FIG. 3 is a manufacturing process diagram of the printed board of the present invention. Throughout the drawings, the same reference numerals denote the same objects.
第２図の（ａ）に示すように、第１のバンプ３が設けら
れた第１のチップ１の中央部に第２のバンプ４が設けら
れた第２のチップ２を重ね合わせ、更に、ポリカーボ材
より成るフィルム5Dにリード６が形成された可撓性を有
するプリント板５が重ね合わせることで構成されたもの
である。As shown in FIG. 2A, the second chip 2 having the second bumps 4 is stacked on the central portion of the first chip 1 having the first bumps 3, and further, A flexible printed board 5 having leads 6 formed thereon is superposed on a film 5D made of a polycarbonate material.
また、フィルム5Dには第２のチップ２の外周に合致し、
第２のバンプ４を露出させる貫通穴5Aと、第１のチップ
１に配列された第１のバンプ３を露出させる貫通穴5B
と、それぞれのリード６を露出させる貫通穴5Cとが設け
られている。Also, the film 5D matches the outer periphery of the second chip 2,
Through holes 5A exposing the second bumps 4 and through holes 5B exposing the first bumps 3 arranged on the first chip 1
And a through hole 5C for exposing the respective leads 6 are provided.
そこで、第１と第２のチップ1,2間を接続する場合は６
−１に示すリード６が（ｂ）に示すように、貫通穴5Bを
通して第１のバンプ３に、貫通穴5Aを通して第２のバン
プ４にそれぞれボンディングされることで行われる。Therefore, when connecting the first and second chips 1 and 2, 6
The lead 6 shown by -1 is bonded to the first bump 3 through the through hole 5B and to the second bump 4 through the through hole 5A, as shown in (b).
また、第１と第２のチップ1,2間を接続し、更に、外部
に接続する場合は６−２に示すリード６が前述のように
第１と第２のバンプ3,4にボンディングされることで行
われ、第１のチップ１または、第２のチップ２を外部に
接続する場合は６−３または６−４に示すリード６がそ
れぞれ同様に第１と第２のバンプ3,4にボンディングさ
れることで行われる。When connecting the first and second chips 1 and 2, and further connecting to the outside, the lead 6 shown in 6-2 is bonded to the first and second bumps 3 and 4 as described above. When connecting the first chip 1 or the second chip 2 to the outside, the leads 6 shown at 6-3 or 6-4 are similarly provided to the first and second bumps 3 and 4, respectively. It is done by being bonded to.
このような６−２〜６−４に示すリード６は（ｃ）に示
すように貫通穴5Cを通して実装すべき基板10,11のパッ
ド10A,11Aに半田付けすることが行われる。The leads 6 shown in 6-2 to 6-4 are soldered to the pads 10A and 11A of the substrates 10 and 11 to be mounted through the through holes 5C as shown in (c).
したがって、重ね合わせられた第１と第２のチップ1,2
のそれぞれの第１と第２のバンプ3,4を６−１〜６−４
に示すリードによって接続し、６−２〜６−４に示すリ
ード６がパッド10A,11Aに半田付けされることで基板10,
11には第１と第２のチップ1,2を重ね合わせることで実
装させることができる。Therefore, the first and second chips 1, 2 which are superposed on each other
The respective first and second bumps 3 and 4 of 6-1 to 6-4
The lead 6 shown in 6-2 to 6-4 is connected to the pads 10A and 11A by soldering to the substrate 10,
11 can be mounted by stacking the first and second chips 1 and 2.
尚、このような構成では、チップを構成するテクノロジ
ーが異なったり、または、チップのサイズの制限によっ
て同一のシリコンチップ上に組み込みが行えないような
複数のチップを１チップ化相当に構成することができ、
例えば、メモリとロジック、アナログとロジックなどを
構成することが行える。In such a configuration, it is possible to configure a plurality of chips into a single chip that cannot be embedded on the same silicon chip due to different technologies for forming the chips or due to the chip size limitation. You can
For example, memory and logic, analog and logic, etc. can be configured.
更に、第１と第２のチップ1,2間の接続路が短く形成さ
れることになり、高速化による電気特性の向上が図れ
る。Furthermore, since the connection path between the first and second chips 1 and 2 is formed short, the electrical characteristics can be improved by increasing the speed.
また、このようなプリント板５は第３図の（ａ）〜
（ｃ）に示す工程によって容易に製造することができ
る。Further, such a printed board 5 is shown in FIG.
It can be easily manufactured by the step shown in (c).
（ａ）に示すように、先づ、ポリイミド材のフィルム5D
にはパンチングによって貫通穴5A,5B,5Cを加工する。As shown in (a), first, the polyimide film 5D
The through holes 5A, 5B, 5C are machined by punching.
次に、（ｂ）に示すように、フィルム5Dの一面に銅箔７
を接着などによって張架し、張架した銅箔７に対しては
エッチング加工によって（ｃ）に示すパターンを形成
し、リード６を設けるようにすることでプリント板５の
製造を行うことができる。Next, as shown in (b), a copper foil 7 is formed on one surface of the film 5D.
The printed board 5 can be manufactured by stretching the copper foil 7 by adhesion or the like and forming the pattern (c) on the stretched copper foil 7 by etching and providing the leads 6. .
以上説明したように、本考案によれば、第１と第２のチ
ップを重ね合わせ、更に、可撓性のプリント板を重ね合
わせることで、実装すべき基板には第１と第２のチップ
を重ね合わせた状態で実装させることができる。As described above, according to the present invention, the first and second chips are superposed on each other, and the flexible printed board is superposed on the first and second chips. Can be mounted in a stacked state.
したがって、従来のパッケージによる実装に比較して軽
量化、小型化および高速化が図れ、実用的効果は大であ
る。Therefore, it is possible to reduce the weight, reduce the size, and increase the speed as compared with the conventional packaging, and the practical effect is great.
第１図は本考案の原理説明図， 第２図は本考案による一実施例の説明図で、（ａ）は平
面図，（ｂ）は（ａ）のA-A′断面図，（ｃ）は基板に
実装した時の要部側面図， 第３図の（ａ）〜（ｃ）は本考案のプリント板の製造工
程図， 第４図は従来の説明図で、（ａ）（ｂ）は側面断面図を
示す。 図において、 １は第１のチップ,2は第２のチップ,3は第１のバンプ,4
は第２のバンプ,5はプリント板,6はリードを示す。1 is an explanatory view of the principle of the present invention, FIG. 2 is an explanatory view of an embodiment according to the present invention, (a) is a plan view, (b) is a sectional view taken along the line AA 'of (a), (c) is A side view of essential parts when mounted on a board, FIGS. 3 (a) to 3 (c) are manufacturing process diagrams of a printed board of the present invention, FIG. 4 is a conventional explanatory view, and FIGS. A side sectional view is shown. In the figure, 1 is the first chip, 2 is the second chip, 3 is the first bump, and 4
Is a second bump, 5 is a printed board, and 6 is a lead.
Claims (1)
ップ（１）と、第２のバンプ（４）が形成され、該第１
のチップ（１）より外形の小さい第２のチップ（２）
と、パターン配線を有する可撓性のプリント板（５）と
を備え、 該第１のバンプ（３）と該第２のバンプ（４）とが同一
方向に配列されるよう該第１のチップ（１）の中央部に
該第２のチップ（２）が重ね合わせられると共に、 該プリント板（５）が該第２のチップ（２）に重ね合わ
せられ、該第１と第２のバンプ（3,4）間の接続、およ
び、該第１と第２のバンプ（3,4）のそれぞれに入出力
される信号の接続を行うリード（６）が該パターン配線
によって形成されることを特徴とするマルチチップ構
造。1. A first chip (1) on which a first bump (3) is formed and a second bump (4) are formed.
Second chip (2), which has a smaller outer shape than the other chip (1)
And a flexible printed board (5) having a pattern wiring, the first chip (3) and the second bump (4) being arranged in the same direction. The second chip (2) is superposed on the central part of (1), and the printed board (5) is superposed on the second chip (2), so that the first and second bumps ( Leads (6) for connecting between 3, 4) and for connecting signals input / output to / from the first and second bumps (3, 4) are formed by the pattern wiring. And a multi-chip structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16410488U JPH0719165Y2 (en) | 1988-12-19 | 1988-12-19 | Multi-chip structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16410488U JPH0719165Y2 (en) | 1988-12-19 | 1988-12-19 | Multi-chip structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0284347U JPH0284347U (en) | 1990-06-29 |
| JPH0719165Y2 true JPH0719165Y2 (en) | 1995-05-01 |
Family
ID=31449420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16410488U Expired - Lifetime JPH0719165Y2 (en) | 1988-12-19 | 1988-12-19 | Multi-chip structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0719165Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009302212A (en) | 2008-06-11 | 2009-12-24 | Fujitsu Microelectronics Ltd | Semiconductor device and method of manufacturing the same |
| JP5678978B2 (en) * | 2013-03-11 | 2015-03-04 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
-
1988
- 1988-12-19 JP JP16410488U patent/JPH0719165Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0284347U (en) | 1990-06-29 |
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