JPS6127667A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6127667A JPS6127667A JP14820984A JP14820984A JPS6127667A JP S6127667 A JPS6127667 A JP S6127667A JP 14820984 A JP14820984 A JP 14820984A JP 14820984 A JP14820984 A JP 14820984A JP S6127667 A JPS6127667 A JP S6127667A
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- elements
- insulating base
- semiconductor device
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、同一の絶縁基板上に論理回路素子とメモリ
素子を実装し、かつ絶縁基板上の各素子の配置が任意に
選択可能である、高実装密度及び高信頼性の半導体装置
に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] This invention provides a method in which a logic circuit element and a memory element are mounted on the same insulating substrate, and the arrangement of each element on the insulating substrate can be arbitrarily selected. The present invention relates to a semiconductor device with high packaging density and high reliability.
近年、電子装置の小型化、高性能化の要求に対応するた
めに、集積回路の素子の高密度実装の必要性が高まって
きている。このためには、素子自体の集積度を上けるだ
けでなく、１個の半導体装置に複数個の集積回路の素子
を塔載する、いわゆるマルチチップモジュールという実
装が重要である。この中では、論理回路素子とメモリ素
子を同じ半導体装置に実装するということも当然に考慮
されなければならない。In recent years, in order to meet the demands for smaller size and higher performance of electronic devices, there has been an increasing need for high-density packaging of integrated circuit elements. To this end, it is important not only to increase the degree of integration of the elements themselves, but also to implement a so-called multi-chip module in which multiple integrated circuit elements are mounted on one semiconductor device. Of course, it must also be considered that the logic circuit element and the memory element are mounted on the same semiconductor device.
従来、論理回路素子とメモリ素子を同一の絶縁基板上に
塔載したマルチチップモジュール半導体装置としては、
第１図（ａ）及び（ｂ）に示すものがあった。第１図（
ａ）及び（ｂ）は、それぞれ従来の半導体装置の構成を
示す斜視図及び断面図である。各図において、１は論理
回路素子、２はメモリ素子、３はセラミック等の誘電体
から成る絶縁基板、４は外部リード、５は半田バンプ、
６は導電パｐ −７、７はスルーホール、８は各素子の
信号を相互に導通するための信号配線パターン形成層、
９は給電パターン層、１０は半導体装置である。Conventionally, multi-chip module semiconductor devices in which logic circuit elements and memory elements are mounted on the same insulating substrate,
There were those shown in FIGS. 1(a) and (b). Figure 1 (
1A and 2B are a perspective view and a cross-sectional view, respectively, showing the configuration of a conventional semiconductor device. In each figure, 1 is a logic circuit element, 2 is a memory element, 3 is an insulating substrate made of a dielectric material such as ceramic, 4 is an external lead, 5 is a solder bump,
6 is a conductive pad p-7, 7 is a through hole, 8 is a signal wiring pattern forming layer for mutually conducting signals of each element,
9 is a power supply pattern layer, and 10 is a semiconductor device.
次に、上記第１図（ａ）及び（ｂ）に示す従来の半導体
装置の具体的な構成について説明する。論理回路素子１
とメモリ素子２の信号は、絶縁基板３内にて格子の形状
に展開される（第１図（ｂ）の一点鎖線を参照）。この
格子のピッチは、塔載される素子の信号数、絶縁基板３
の外形寸法、外部リード４のピッチ等によって決定され
る。この様にして展開された信号は、信号配線パターン
形成層８で相互に導通され、外部リード４にも導通され
る。上述の様な構造にすると、信号配線パターン形成層
８の設計変更だけで、異なる半導体装置を構成すること
ができる。Next, the specific structure of the conventional semiconductor device shown in FIGS. 1(a) and 1(b) will be described. Logic circuit element 1
and the signals of the memory element 2 are developed in the shape of a lattice within the insulating substrate 3 (see the dashed-dotted line in FIG. 1(b)). The pitch of this grid is determined by the number of signals of the mounted elements, the number of signals on the insulating substrate 3
It is determined by the external dimensions of the external leads 4, the pitch of the external leads 4, etc. The signals developed in this manner are electrically connected to each other in the signal wiring pattern forming layer 8 and also to the external leads 4. With the structure described above, different semiconductor devices can be constructed by simply changing the design of the signal wiring pattern forming layer 8.
従来の半導体装置は以上の様に構成されているので、信
号配線パターン形成層８の設計変更にょシ信号配線パタ
ーンの変更は容易にできるが、論理回路素子１及びメモ
リ素子２の配置や搭載数は、絶縁基板３によシ特定して
固定されているため、その変更ができ々いという欠点が
あった。Since the conventional semiconductor device is configured as described above, it is easy to change the design of the signal wiring pattern forming layer 8 and change the signal wiring pattern. Since it is fixed to the insulating substrate 3 in a specific manner, it has the disadvantage that it is difficult to change it.
この発明は、上記の様な従来のものの欠点を改善する目
的でなされたもので、集積回路の素子を塔載し、この素
子と電気的に接続されている第１の導電パッドを格子状
に配置した第１の絶縁基板と、一方の面に外部リードを
設け、他方の面に前記第１の導電パッドと同一格子状に
第２の導電パッドを配置した第２の絶縁基板を備え、複
数個の第１の絶縁基板を第２の絶縁基板上の所望の位置
に配置し、前記第１と第２の導電パッドを互いに電気的
に接続することにより、半導体装置ごとに各素子の配置
を任意に選択できる半導体装置を提供するものである。This invention was made with the aim of improving the above-mentioned drawbacks of the conventional products, and includes an integrated circuit element mounted on a tower, and first conductive pads electrically connected to the element arranged in a grid pattern. a second insulating substrate having external leads provided on one surface and second conductive pads arranged in the same grid pattern as the first conductive pads on the other surface; By arranging the first insulating substrate at a desired position on the second insulating substrate and electrically connecting the first and second conductive pads to each other, the arrangement of each element can be adjusted for each semiconductor device. This provides a semiconductor device that can be selected arbitrarily.
以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第２図（ａ）及び（ｂ）は、それぞれこの発明の一実施
例である半導体装置の構成を示す斜視図及び断面図であ
る。各図において、１は論理回路素子、２はメモリ素子
、４は外部リード、５は半田パン”プ、６は導電パター
ン、７はスルーホール、８は信号配線パターン形成層、
９は給電パターン層、１１は素子塔載用のセラミック等
の誘電体から成る第１の絶縁基板、１２は同じくセラミ
ック等から成る第２の絶縁基板、１３は第１の絶縁基板
１１の素子接続点の展開位置に格子状に設けられた第１
の導電パッド、１４は第２の絶縁基板１２の表面に設け
られた信号配線格子を示す第２の導電パッドであり、第
１及び第２の各導電パッド１３．１４のピッチは同一で
ある。１５は第１及び第２の各絶縁基板１１．１２を互
いに接続する半田バンプである。この実施例では、メモ
リ素子はワイヤボンディング方式によシアセンブリされ
ているが、これは、半田バンプ５の成分である鉛から生
じるα線によるメモリのソフトエラ一対策のためである
。FIGS. 2(a) and 2(b) are a perspective view and a sectional view, respectively, showing the structure of a semiconductor device that is an embodiment of the present invention. In each figure, 1 is a logic circuit element, 2 is a memory element, 4 is an external lead, 5 is a solder pump, 6 is a conductive pattern, 7 is a through hole, 8 is a signal wiring pattern forming layer,
9 is a power supply pattern layer, 11 is a first insulating substrate made of a dielectric material such as ceramic for mounting an element, 12 is a second insulating substrate also made of ceramic or the like, and 13 is an element connection of the first insulating substrate 11. The first grid is provided in a grid pattern at the development position of the points.
The conductive pads 14 are second conductive pads representing a signal wiring grid provided on the surface of the second insulating substrate 12, and the pitches of the first and second conductive pads 13 and 14 are the same. Reference numeral 15 denotes a solder bump that connects the first and second insulating substrates 11 and 12 to each other. In this embodiment, the memory element is assembled by a wire bonding method, and this is to prevent soft errors in the memory due to alpha rays generated from lead, which is a component of the solder bumps 5.
第３図（ａ）及び（ｂ）は、それぞれ第２図（ｂ）の第
１の絶縁基板において、フリップチップボンディング方
式及びワイヤボンディング方式による上面図、底面図及
び断面図である。各図に示す様に、第１の絶縁基板１１
において、３１は７リツブチツプボンデイング用パツド
、３２はワイヤボンデインク用パッド、３３はダイボン
ドエリアである。FIGS. 3(a) and 3(b) are a top view, a bottom view, and a cross-sectional view, respectively, of the first insulating substrate of FIG. 2(b) by a flip chip bonding method and a wire bonding method. As shown in each figure, the first insulating substrate 11
In the figure, 31 is a seven-rib chip bonding pad, 32 is a wire bonding ink pad, and 33 is a die bonding area.
第４図（ａ）及び（ｂ）は、それぞれ第２図（ｂ）の第
２の絶縁基板の構成を示す斜視図及び断面図である。FIGS. 4(a) and 4(b) are a perspective view and a sectional view, respectively, showing the structure of the second insulating substrate shown in FIG. 2(b).
各図に示す様に、第２の絶縁基板１２において、４は外
部リード、６は導電パターン、７はスルーホール、８は
信号配線パターン形成層、９は給電パターン層、１４は
第２の導電パッドであシ、この第２の導電パッド１４は
、第４図（ａ）に示す様に格子状に配置されている。As shown in each figure, in the second insulating substrate 12, 4 is an external lead, 6 is a conductive pattern, 7 is a through hole, 8 is a signal wiring pattern formation layer, 9 is a power supply pattern layer, and 14 is a second conductive pattern. The second conductive pads 14 are arranged in a grid pattern as shown in FIG. 4(a).
次に、上記第２図（ａ）及び（ｂ）に示すこの発明の一
実施例である半導体装置の具体的な構成について説明す
る。７リップチップボンディング方式又はワイヤボンデ
ィング方式によって、第１の絶縁基板１１に塔載された
素子の信号は、第１の絶縁基板１１内に形成された導電
パターン６、スルーホール７により信号配線格子と同一
の格子の形状に展開され、第１の導電パッド１３に導通
される。Next, the specific structure of the semiconductor device shown in FIGS. 2(a) and 2(b), which is an embodiment of the present invention, will be described. 7. Signals from the elements mounted on the first insulating substrate 11 by the lip-chip bonding method or the wire bonding method are connected to the signal wiring grid by the conductive patterns 6 and through holes 7 formed in the first insulating substrate 11. They are developed into the same grid shape and electrically connected to the first conductive pad 13.
この様な素子を塔載した第１の絶縁基板１１を第２の絶
縁基板１２上の所望の位置に配置し、第１の導電パッド
１３と第２の導電パッド１４を半田バンプ１５を介して
互いに接続する。この様にして、第１及び第２の各絶縁
基板１１．１２を接続することにより、第２の絶縁基板
１２内の信号配線パターン形成層８に形成された導電パ
ターン６とスルーホール７によシ、各素子の相互の信号
は導通され、また、外部リード４にも導通される。The first insulating substrate 11 on which such an element is mounted is placed at a desired position on the second insulating substrate 12, and the first conductive pad 13 and the second conductive pad 14 are connected via solder bumps 15. Connect with each other. By connecting the first and second insulating substrates 11 and 12 in this manner, the conductive pattern 6 and through hole 7 formed in the signal wiring pattern forming layer 8 in the second insulating substrate 12 are connected. The signals of each element are electrically connected to each other, and also to the external lead 4.
なお、上記実施例では、第１及び第２の各絶縁基板１１
．１２の接続に半田バンプ１５を用いた場合について説
明したが、接続法はこれに限定されるものではない。Note that in the above embodiment, each of the first and second insulating substrates 11
．． Although a case has been described in which solder bumps 15 are used to connect 12, the connection method is not limited to this.
また、上記実施例では、第１の絶縁基板１１に素子を塔
載する方式として、フリップチップボンディング方式及
びワイヤボンディング方式を例として示したが、他の方
式、例えばテープキャリア方式であっても良い。Further, in the above embodiment, the flip-chip bonding method and the wire bonding method were shown as examples of methods for mounting the elements on the first insulating substrate 11, but other methods such as a tape carrier method may also be used. .
また、上記実施例では、素子を直接に第１の絶縁基板１
１に塔載した場合について説明したが、素子を他のパッ
ケージに塔載し、そのパッケージを第１の絶縁基板１１
に塔載する様にしても良い。Further, in the above embodiment, the element is directly connected to the first insulating substrate 1.
Although the description has been made regarding the case where the element is mounted on the first insulating substrate 11, the element is mounted on another package and the package is mounted on the first insulating substrate 11.
It is also possible to have it listed on the page.
この発明は以上説明した様に、半導体装置において、集
積回路の素子を塔載し、この素子と電気的に接続されて
いる第１の導電バットを格子状に配置した第１の絶縁基
板と、一方の面に外部リードを設け、他方の面に前記第
１の導電パッドと同一格子状に第２の導電パッドを配置
した第２の絶縁基板を備え、複数個の第１の絶縁基板を
第２の絶縁基板上の所望の位置に配置し、前記第１と第
２の導電パッドを互いに電気的に接続する様にしたので
、半導体装置ごとに各素子の配置を任意に選択すること
ができる効果がある。また、第１の絶縁基板への素子の
塔載は各々独立した工程で行うことが可能となり、一つ
の半導体装置内で素子により異なる素子の塔載方式が採
用でき、展開後の格子だけを統一すれば、塔載する素子
のピッチは任意に決定でき、さらに、展開後の導電パッ
ドを用いれば、素子の搭載後のテストも容易に行うこと
ができるなどの優れた効果を奏するものである。As explained above, the present invention provides a semiconductor device including: a first insulating substrate on which an integrated circuit element is mounted and first conductive bats electrically connected to the element are arranged in a grid pattern; A second insulating substrate has external leads provided on one surface and second conductive pads arranged in the same grid pattern as the first conductive pads on the other surface, and a plurality of first insulating substrates are connected to the first insulating substrate. Since the first and second conductive pads are arranged at desired positions on the second insulating substrate and the first and second conductive pads are electrically connected to each other, the arrangement of each element can be arbitrarily selected for each semiconductor device. effective. In addition, it is now possible to mount each element on the first insulating substrate in an independent process, allowing different mounting methods to be used depending on the element within one semiconductor device, and only the lattice after deployment is unified. In this way, the pitch of the mounted elements can be arbitrarily determined, and furthermore, by using the conductive pads after being developed, it is possible to easily perform tests after mounting the elements, which is an excellent effect.
第１図（ａ）及び（ｂ）は、それぞれ従来の半導体装置
の構成を示す斜視図及び断面図、第２図（ａ）及び（ｂ
）は、それぞれこの発明の一実施例である半導体装置の
構成を示す斜視図及び断面図、第３図（ａ）及び（ｂ）
は、それぞれ第２図（ｂ）の第１の絶縁基板において、
７リツプチツプボンデイング方式及びワイヤボンディン
グ方式による上面図、底面図及び断面図、第４図（ａ）
及び（ｂ）は、それぞれ第２図（ｂ）の第２の絶縁基板
の構成を示す斜視図及び断面図である。
図において、１・・・論理回路素子、２・・・メモリ素
子、３・・・絶縁基板、４・・・外部リード、５゜１５
・・・半田バンプ、６・・・導電パターン、７・・・・
スルーホール、８・・・信号配線パターン形底層、９・
・・給電パターン層、１ｏ・・・半導体装置、１１・・
・第１の絶縁基板、１２・・・第２の絶縁基板、１３・
・・第１の導電パッド、１４・・・第２の導電パッド、
３１・・・フリップチップボンディング用パッド、３２
・・・ワイヤボンディング用パッド、３３・・・グイボ
ンドエリアである。
なお、各図中、同一部分は同一、又は相当部分を示す。FIGS. 1(a) and (b) are a perspective view and a sectional view showing the structure of a conventional semiconductor device, respectively, and FIGS. 2(a) and (b) are
) are a perspective view and a sectional view, respectively, showing the structure of a semiconductor device which is an embodiment of the present invention, and FIGS. 3(a) and (b).
are respectively in the first insulating substrate of FIG. 2(b),
7 Top view, bottom view, and cross-sectional view of the lip-chip bonding method and wire bonding method, FIG. 4(a)
2(b) are a perspective view and a sectional view, respectively, showing the structure of the second insulating substrate of FIG. 2(b). In the figure, 1...logic circuit element, 2...memory element, 3...insulating substrate, 4...external lead, 5°15
... Solder bump, 6... Conductive pattern, 7...
Through hole, 8...Signal wiring pattern bottom layer, 9.
...Power supply pattern layer, 1o...Semiconductor device, 11...
・First insulating substrate, 12... Second insulating substrate, 13・
...first conductive pad, 14...second conductive pad,
31...Flip chip bonding pad, 32
. . . wire bonding pad, 33 . . . wire bonding area. Note that in each figure, the same parts indicate the same or equivalent parts.
Claims (1)
素子の塔載面と相対する面に、前記素子の接続点と電気
的に接続されている第１の導電パッドを格子状に配置し
、前記第１の絶縁基板を複数個塔載可能な外形寸法を有
する第２の絶縁基板には、その一方の面に外部と接続す
るための複数本のリードを設け、他方の面に前記第１の
絶縁基板の第１の導電パッドと同一格子状に第２の導電
パッドを配置し、複数個の前記第１の絶縁基板を前記第
２の絶縁基板上の所望の位置に配置し、前記第１と第２
の導電パッドを互いに電気的に接続して成ることを特徴
とする半導体装置。A first insulating substrate on which integrated circuit elements are mounted has first conductive pads electrically connected to connection points of the elements arranged in a grid pattern on a surface opposite to the surface on which the elements are mounted. A second insulating substrate having external dimensions that allows a plurality of the first insulating substrates to be mounted thereon is provided with a plurality of leads for connection to the outside on one surface thereof, and a plurality of leads for connection to the outside are provided on one surface thereof, and a plurality of leads are provided on the other surface thereof. A second conductive pad is arranged in the same grid as the first conductive pad of the first insulating substrate, and a plurality of the first insulating substrates are arranged at desired positions on the second insulating substrate. , said first and second
A semiconductor device comprising conductive pads electrically connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14820984A JPS6127667A (en) | 1984-07-17 | 1984-07-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14820984A JPS6127667A (en) | 1984-07-17 | 1984-07-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6127667A true JPS6127667A (en) | 1986-02-07 |
Family
ID=15447704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14820984A Pending JPS6127667A (en) | 1984-07-17 | 1984-07-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6127667A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0268111A2 (en) * | 1986-11-17 | 1988-05-25 | International Business Machines Corporation | Interposer chip technique for making engineering changes between interconnected semiconductor chips |
| EP0337686A2 (en) * | 1988-04-12 | 1989-10-18 | Hitachi, Ltd. | Semiconductor chip module |
| US4930002A (en) * | 1987-04-01 | 1990-05-29 | Hitachi, Ltd. | Multi-chip module structure |
| US5177594A (en) * | 1991-01-09 | 1993-01-05 | International Business Machines Corporation | Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance |
| US5293067A (en) * | 1991-05-23 | 1994-03-08 | Motorola, Inc. | Integrated circuit chip carrier |
| US5535101A (en) * | 1992-11-03 | 1996-07-09 | Motorola, Inc. | Leadless integrated circuit package |
-
1984
- 1984-07-17 JP JP14820984A patent/JPS6127667A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0268111A2 (en) * | 1986-11-17 | 1988-05-25 | International Business Machines Corporation | Interposer chip technique for making engineering changes between interconnected semiconductor chips |
| US4930002A (en) * | 1987-04-01 | 1990-05-29 | Hitachi, Ltd. | Multi-chip module structure |
| EP0337686A2 (en) * | 1988-04-12 | 1989-10-18 | Hitachi, Ltd. | Semiconductor chip module |
| US4970577A (en) * | 1988-04-12 | 1990-11-13 | Hitachi, Ltd. | Semiconductor chip module |
| US5177594A (en) * | 1991-01-09 | 1993-01-05 | International Business Machines Corporation | Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance |
| US5293067A (en) * | 1991-05-23 | 1994-03-08 | Motorola, Inc. | Integrated circuit chip carrier |
| US5535101A (en) * | 1992-11-03 | 1996-07-09 | Motorola, Inc. | Leadless integrated circuit package |
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