JPH0284347U - - Google Patents

Info

Publication number
JPH0284347U
JPH0284347U JP16410488U JP16410488U JPH0284347U JP H0284347 U JPH0284347 U JP H0284347U JP 16410488 U JP16410488 U JP 16410488U JP 16410488 U JP16410488 U JP 16410488U JP H0284347 U JPH0284347 U JP H0284347U
Authority
JP
Japan
Prior art keywords
chip
bump
printed board
bumps
superimposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16410488U
Other languages
Japanese (ja)
Other versions
JPH0719165Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16410488U priority Critical patent/JPH0719165Y2/en
Publication of JPH0284347U publication Critical patent/JPH0284347U/ja
Application granted granted Critical
Publication of JPH0719165Y2 publication Critical patent/JPH0719165Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の原理説明図、第２図は本考案
による一実施例の説明図で、ａは平面図、ｂはａ
のＡ―Ａ′断面図、ｃは基板に実装した時の要部
側面図、第３図のａ〜ｃは本考案のプリント板の
製造工程図、第４図は従来の説明図で、ａ，ｂは
側面断面図、を示す。 図において、１は第１のチツプ、２は第２のチ
ツプ、３は第１のバンプ、４は第２のバンプ、５
はプリント板、６はリードを示す。 Fig. 1 is an explanatory diagram of the principle of the present invention, and Fig. 2 is an explanatory diagram of an embodiment according to the present invention, where a is a plan view and b is a
c is a side view of the main part when mounted on a board, a to c in Fig. 3 is a manufacturing process diagram of the printed board of the present invention, and Fig. 4 is an explanatory diagram of the conventional method. ,b shows a side sectional view. In the figure, 1 is the first chip, 2 is the second chip, 3 is the first bump, 4 is the second bump, 5
indicates a printed board, and 6 indicates a lead.

Claims (1)

【実用新案登録請求の範囲】 第１のバンプ３が形成された第１のチツプ１と
、第２のバンプ４が形成され、該第１のチツプ１
より外形の小さい第２のチツプ２と、パターン配
線を有する可撓性のプリント板５とを備え、 該第１のバンプ３と該第２のバンプ４とが同一
方向に配列されるよう該第１のチツプ１の中央部
に該第２のチツプ２が重ね合わせられると共に、 該プリント板５が該第２のチツプ２に重ね合わ
せられ、該第１と第２のバンプ３，４間の接続、
および、該第１と第２のバンプ３，４のそれぞれ
に入出力される信号の接続を行うリード６が該パ
ターン配線によつて形成されることを特徴とする
マルチチツプ構造。[Claims for Utility Model Registration] A first chip 1 on which a first bump 3 is formed, and a first chip 1 on which a second bump 4 is formed.
It includes a second chip 2 with a smaller outer diameter and a flexible printed board 5 having pattern wiring, and the first bump 3 and the second bump 4 are arranged in the same direction. The second chip 2 is superimposed on the center of the first chip 1, and the printed board 5 is superimposed on the second chip 2, and the connection between the first and second bumps 3 and 4 is established. ,
and a multi-chip structure characterized in that leads 6 for connecting signals input and output to each of the first and second bumps 3 and 4 are formed by the pattern wiring.
JP16410488U 1988-12-19 1988-12-19 Multi-chip structure Expired - Lifetime JPH0719165Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16410488U JPH0719165Y2 (en) 1988-12-19 1988-12-19 Multi-chip structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16410488U JPH0719165Y2 (en) 1988-12-19 1988-12-19 Multi-chip structure

Publications (2)

Publication Number Publication Date
JPH0284347U true JPH0284347U (en) 1990-06-29
JPH0719165Y2 JPH0719165Y2 (en) 1995-05-01

Family

ID=31449420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16410488U Expired - Lifetime JPH0719165Y2 (en) 1988-12-19 1988-12-19 Multi-chip structure

Country Status (1)

Country Link
JP (1) JPH0719165Y2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013110442A (en) * 2013-03-11 2013-06-06 Fujitsu Semiconductor Ltd Method of manufacturing semiconductor device
US8748229B2 (en) 2008-06-11 2014-06-10 Fujitsu Semiconductor Limited Manufacturing method including deformation of supporting board to accommodate semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8748229B2 (en) 2008-06-11 2014-06-10 Fujitsu Semiconductor Limited Manufacturing method including deformation of supporting board to accommodate semiconductor device
JP2013110442A (en) * 2013-03-11 2013-06-06 Fujitsu Semiconductor Ltd Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
JPH0719165Y2 (en) 1995-05-01

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