JP2013110442A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that has a plurality of electronic components such as semiconductor elements and can be adapted to the requirements of reducing thickness, downsizing, and low manufacturing cost, and to provide a method of manufacturing the same.SOLUTION: A semiconductor device 100 comprises: a supporting substrate 11; a first semiconductor element 21 mounted on one primary surface of the supporting substrate 11; and an electronic component 31 disposed between the supporting substrate 11 and the first semiconductor element 21. The supporting substrate 11 has a recess S formed so as to be deformed in the direction apart from the first semiconductor element 21, and the electronic component 31 is mounted such that at least a part of its thickness is housed in the recess S.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device in which a plurality of semiconductor elements or semiconductor elements and electronic components such as passive elements are overlapped and mounted on a support substrate, and a manufacturing method thereof.

  Along with higher functionality and smaller size of electronic devices, semiconductor devices such as semiconductor integrated circuit devices mounted on the electronic devices are becoming smaller, thinner and lighter with higher functionality and higher speed. Is required.

  For this reason, for example, using a printed wiring board in which an insulating resin such as a glass epoxy resin is used as a base material and a conductive layer made of copper (Cu) or the like is selectively provided on one main surface and / or inside thereof, A semiconductor integrated circuit element (hereinafter referred to as a semiconductor element) is connected to the conductive layer in a so-called flip-chip (face-down) state using a convex (projection-shaped) external connection terminal disposed on the main surface. In addition, there has been proposed a semiconductor device in which an external connection terminal such as a spherical electrode terminal is disposed on an electrode formed on the other main surface of the printed wiring board.

  Also proposed is a form in which a plurality of electronic components such as semiconductor elements are stacked on a wiring board.

  Further, a so-called chip on chip (COC) structure in which a plurality of semiconductor elements having different functions are directly connected to each other through respective external connection terminals has been proposed.

  On the other hand, in order to reduce the thickness of the package (container) in which the semiconductor element is accommodated, an opening is selectively formed through the printed wiring board, and a silicon (Si) or ceramic substrate is formed in the opening. There has been proposed a semiconductor device that accommodates a chip mounted on a flip chip and is provided with a cup-shaped cover that covers the chip protruding from the opening. (See Patent Document 1)

JP-A-8-250653

  However, in the aspect described in Patent Document 1, an opening corresponding to a chip is formed through the printed wiring board. For this reason, the manufacturing cost of the printed wiring board is increased, and the arrangement of the internal wirings in the printed wiring board is restricted, resulting in a decrease in the degree of freedom of design.

  If the number of wiring layers is increased in order to increase the degree of freedom of wiring, the manufacturing cost increases, the thickness of the printed wiring board also increases, and the size of the printed wiring board increases. For this reason, the semiconductor device is increased in size and cannot meet the demands for downsizing and thinning.

  The present invention has been made in view of the above points, and a plurality of semiconductor elements or semiconductor elements and electronic components are arranged on a supporting substrate such as a wiring board so as to overlap each other. An object of the present invention is to provide a semiconductor device structure that can be miniaturized and that does not increase the manufacturing cost thereof, and a manufacturing method thereof.

  According to an embodiment of the present invention, a support substrate, a first semiconductor element mounted on one main surface of the support substrate, and between the support substrate and the first semiconductor element. And the support substrate has a recess formed by being deformed in a direction away from the first semiconductor element, and the electronic component has at least a part of its thickness. Is provided to be accommodated and mounted in the recess.

  According to another aspect of the embodiment of the present invention, an electronic component is pressed through a first semiconductor element against one main surface of the support substrate, and the support substrate is pressed into the first semiconductor element. There is provided a method of manufacturing a semiconductor device, comprising: a step of deforming in a direction away from the housing, and housing at least a part of the electronic component in a recess formed in the support substrate by the deformation.

  According to another aspect of the embodiment of the present invention, the second semiconductor element is disposed between the support substrate and the first semiconductor element, and the second substrate is heated in the state where the support substrate is heated. Pressing the semiconductor element against the support substrate via the first semiconductor element to locally bend the support substrate; and bending the support substrate to the first support substrate. There is provided a method for manufacturing a semiconductor device, comprising the step of fixing the semiconductor element.

  According to the present invention, a semiconductor device having a plurality of functional elements such as a plurality of semiconductor elements or a semiconductor element and a passive element, which is thinned and miniaturized, and the semiconductor device are manufactured at a low manufacturing cost. The manufacturing method which can be provided can be provided.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the circuit formation surface of the 1st semiconductor element shown in FIG. FIG. 3 is a diagram showing a modification of the circuit formation surface of the first semiconductor element shown in FIG. 2. It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which shows the circuit formation surface of the 1st semiconductor element shown in FIG. It is a figure which shows the modification of the circuit formation surface of the 1st semiconductor element shown in FIG. It is sectional drawing of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 4th Embodiment of this invention. FIG. 6 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device according to the first embodiment of the invention; FIG. 8 is a diagram (part 2) for illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention; It is FIG. (The 3) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a graph which shows the time passage of the height position of a bonding tool, and the load of a bonding tool. FIG. 11 is an enlarged view of a portion surrounded by a dotted line A in FIG. It is a figure which shows the modification of the recessed part formed in the bonding stage. FIG. 12 is a view (No. 1) showing a modification of the step shown in FIG. 10 and FIG. FIG. 12 is a diagram (No. 2) illustrating a modified example of the process illustrated in FIGS. It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (3) which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (The 3) which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is FIG. (1) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. It is FIG. (3) which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention.

  Embodiments of the present invention will be described below.

  First, a structure of a semiconductor device according to an embodiment of the present invention will be described, and then a method for manufacturing the semiconductor device will be described.

[Semiconductor device]
(First embodiment)
The configuration of the semiconductor device 100 according to the first embodiment of the present invention is shown in FIG.

  In the semiconductor device 100, a first semiconductor integrated circuit element (hereinafter referred to as a first semiconductor element) 21 is provided on one main surface (upper surface) of the support substrate 11 so-called flip chip (face-down). ) Method is installed.

  In the support substrate 11, a region facing one main surface (electronic circuit formation surface) of the first semiconductor element 21 is selectively moved away from the first semiconductor element 21. A region in which the gap between the first semiconductor element 21 and the support substrate 11 is enlarged in the vertical direction, that is, in the direction perpendicular to the main surface of the first semiconductor element 21 (hereinafter, the portion is referred to as a “recessed portion”). S ”). The recess S is provided at a substantially central portion of the support substrate 11.

  Then, in the recess S, a second semiconductor integrated circuit element (hereinafter referred to as a second semiconductor element) 31 mounted and fixed to the first semiconductor element 21 by a flip chip method is received. ing.

  The support substrate 11 is also referred to as a wiring substrate, an interposer, or a circuit substrate. The substrate 11 is made of an organic insulating resin such as glass epoxy resin, glass-BT (bismaleimide triazine), or polyimide. Alternatively, a wiring layer made of copper (Cu) or the like is disposed inside with a surface layer wiring structure or a multilayer wiring structure.

  The support substrate 11 may be a so-called rigid substrate in addition to a flexible printed circuit (FPC) substrate that is flexible even at room temperature, as long as it expands when heated and generates flexibility. For example, a glass epoxy substrate having a four-layer wiring structure with a thickness of about 0.3 mm can be applied.

  As described above, the support substrate 11 has a thickness substantially the same as that of other portions at the substantially central portion thereof, and protrudes in a direction opposite to the mounting surface of the first semiconductor element 21. A concave portion S whose planar shape has a substantially rectangular shape (not shown) is disposed.

  As will be described later, the concave portion S is formed by deformation (bending) of the support substrate 11 itself, and receives a functional element such as a semiconductor element or a passive element.

  In the support substrate 11, a conductive layer (not shown) connected to the wiring layer is selectively disposed on the main surface on which the first semiconductor element 21 is mounted. The conductive resist layer is selectively covered, that is, the solder resist layer (insulating resin film) is selectively covered except for the portion where the external connection terminal of the first semiconductor element 21 is connected and its periphery (see FIG. Not shown). In the opening provided in the solder resist layer, a part of the conductive layer is exposed and arranged as the electrode terminal 12.

  The concave portion S is disposed inside the portion where the electrode terminal 12 is disposed, that is, corresponding to a region surrounded or sandwiched by the electrode terminal 12, and the upper opening width W1 of the concave portion S is an opposing electrode. The distance WS between the terminals 12 is smaller than the distance WS.

  On the other hand, the opening width W2 at the lower part (bottom part) of the recess S is set to be larger than the external dimensions of the second semiconductor element 31 received in the recess S.

  In addition, the depth DS1 of the recess S cooperates with the height of the external connection terminal 24 of the first semiconductor element 21 and the thickness of the electrode terminal 12, and is at least a second depth received in the recess S. The thickness of the semiconductor element 31 and the electrode 33 that connects the second semiconductor element 31 and the first semiconductor element 21 between the second semiconductor element 31 and the first semiconductor element 21. It is the depth that can absorb the height of.

  Therefore, the total value of the height of the external connection terminal 24 and the thickness of the electrode terminal 12 of the first semiconductor element 21 is the thickness of the second semiconductor element 31 received in the recess S and the second value. This is smaller than the total height of the electrodes 33 disposed between the semiconductor element 31 and the first semiconductor element 21.

  In addition, on the surface of the electrode terminal 12 on the support substrate 11, a two-layer plating layer of nickel (Ni) / gold (Au) in order from the lower layer by an electrolytic plating method or an electroless plating method, if necessary, Alternatively, a three-layer plating layer of copper (Cu) / nickel (Ni) / gold (Au) is coated. Instead of the plating layer, a solder coating such as tin (Sn) or tin (Sn) alloy may be applied.

  In addition, a plurality of conductive layers are selectively disposed on the other main surface (back surface) of the support substrate 11, and the conductive layers (not shown) are formed from spherical electrode terminals mainly composed of solder. An external connection terminal 13 is provided.

  The height H of the external connection terminal 13 has a value (H> h) exceeding the position (height h) of the lower surface US of the support substrate 11 formed corresponding to the recess S.

  The first semiconductor element 21 and the second semiconductor element 31 are each a known semiconductor manufacturing process (so-called wafer) for a semiconductor substrate made of a semiconductor such as silicon (Si) or a compound semiconductor such as gallium arsenide (GaAs). Process) is applied, and an electronic circuit portion is formed on one main surface thereof. Here, active elements such as transistors and / or passive elements such as capacitive elements constituting the electronic circuit section, and a multilayer wiring layer for connecting these functional elements or between the functional elements and electrode terminals In addition, illustration of the rewiring layer and the like is omitted.

  The thickness of the first semiconductor element 21 is set to, for example, 100 μm to 300 μm, and the thickness of the second semiconductor element 31 is set to, for example, 25 μm to 200 μm.

  FIG. 2 shows the arrangement of terminal pads on the surface of the first semiconductor element 21 facing the support substrate 11, that is, on the electronic circuit formation surface.

  On the electronic circuit formation surface of the first semiconductor element 21 having a substantially rectangular shape, a plurality of first external connection terminal pads 22 are arranged in a row along each edge of the four sides. .

  In addition, a plurality of second external connection terminal pads 23 are arranged in a rectangular shape substantially at the center of the electronic circuit formation surface, corresponding to the arrangement of the electrode terminals in the second semiconductor element 31. Has been.

  Each first external connection terminal pad 22 of the first semiconductor element 21 is provided with a convex external connection terminal 24, and the first external connection terminal pad 22 and the support substrate 11 are connected to each other. The electrode terminal 12 is mechanically and electrically connected via the external connection terminal 24.

  The first external connection terminal pad 22 and the second external connection terminal pad 23 are made of, for example, aluminum (Al), copper (Cu), or an alloy thereof.

  The convex external connection terminals 24 arranged on the first external connection terminal pads 22 are, for example, gold (Au), copper (Cu), or alloys thereof, or tin (Sn) -silver ( It is formed from a metal such as Ag) solder or tin (Sn) -silver (Ag) -copper (Cu) solder.

  When a metal bump made of gold (Au), copper (Cu), or an alloy thereof is applied as the convex external connection terminal 24, the external connection terminal 24 is a so-called ball using, for example, a wire bonding technique. It can be formed by a bonding method.

  Moreover, these metal bumps can be formed by electrolytic plating. When the metal bump is formed by the plating method, for example, titanium (Ti) / tungsten (W), titanium (Ti) / palladium (Pd), or titanium (Ti) is formed on the first external connection terminal pad 18. ) / Nickel (Ni) / Palladium (Pd) or other base metal layer (UBM: Under Bump Metal) may be formed.

  When solder bumps are employed as the external connection terminals 24, the external connection terminals 14 can be formed by, for example, electrolytic plating, transfer, printing, or the like. In this case, for example, nickel (Ni), titanium (Ti) / copper (Cu) / nickel (Ni), titanium (Ti) / chromium (Cr) / copper (Cu) is formed on the first external connection terminal pad 18. / An under metal layer (UBM) such as nickel (Ni) may be formed.

  On the other hand, the external connection terminal 33 of the second semiconductor element 31 is connected to the second external connection terminal pad 23.

  In the second semiconductor element 31, a plurality of external connection terminal pads 32 are arranged in a row along each of the four edge portions of the electronic circuit forming surface having a substantially rectangular shape. A convex external connection terminal 33 is disposed on the external connection terminal pad 32. That is, the second external connection terminal pad 23 of the first semiconductor element 21 and the external connection terminal pad 32 of the second semiconductor element 31 are electrically connected via the convex external connection terminal 33. Is done.

  The external connection terminal pad 32 in the second semiconductor element 31 is similar to the first external connection terminal pad 22 and the second external connection terminal pad 23 in the first semiconductor element 21, for example. It is formed with aluminum (Al), copper (Cu), or an alloy thereof.

  Further, the convex external connection terminal 33 arranged on the external connection terminal pad 32 is, for example, gold (Au), copper, like the convex external connection terminal 24 in the first semiconductor element 21. (Cu), or an alloy thereof, or a metal such as tin (Sn) -silver (Ag) solder, tin (Sn) -silver (Ag) -copper (Cu) solder.

  When a bump made of gold (Au), copper (Cu), or an alloy thereof is applied as the external connection terminal 33, a so-called ball bonding method or electrolytic plating method can be applied as the formation method. . Further, when solder bumps are applied as the external connection terminals 33, an electrolytic plating method, a transfer method, a printing method, or the like can be applied as the formation method.

  Further, the surface of the second external connection terminal pad 23 of the first semiconductor element 21 to which the external connection terminal 33 in the second semiconductor element 31 is connected is formed by electrolytic plating or electroless plating. In order from the lower layer, a nickel (Ni) / gold (Au) two-layer plating layer or a solder coating such as tin (Sn) or tin (Sn) alloy may be applied.

  The convex external connection terminal 24 in the first semiconductor element 21 may be provided on the first electrode terminal 12 of the support substrate 11 which is the terminal on the flip chip mounting side, or the second The convex external connection terminal 33 in the semiconductor element 31 may be provided on the terminal on the flip chip mounting side, that is, on the second external connection terminal pad 23 of the first semiconductor element 21.

  Incidentally, the arrangement of the first external connection terminal pads 22 and the second external connection terminal pads 23 arranged on the main surface (electronic circuit formation surface) of the first semiconductor element 21 is shown in FIG. ) Or the form shown in FIG. 3B can also be applied.

  In the embodiment shown in FIG. 3A, the first external connection terminal pad 22 is along a pair of two sides facing each other among the four sides of the electronic circuit formation surface of the first semiconductor element 21A. Are arranged in a row. On the other hand, the second external connection terminal pads 23 are arranged in the same manner as in the embodiment shown in FIG.

  On the other hand, in the configuration shown in FIG. 3B, the first external connection terminal pads 22 are arranged in a plurality of rows along each of the four sides of the electronic circuit formation surface of the first semiconductor element 21B. It is installed. According to this configuration, since the first external connection terminal pads 22 are arranged in a plurality of rows, the first semiconductor element 21 and the support substrate 11 are connected via the external connection terminal pads 22. Easy to conduct heat.

  In such a configuration, the second external connection terminal pads 23 are arranged in a grid in the substantially central portion of the electronic circuit formation surface.

  In the semiconductor device 100, the cured first adhesive is provided between the main surface of the support substrate 11 and the main surface (electronic circuit forming surface) of the first semiconductor element 21 facing the support substrate 11. The cured second adhesive is disposed between the main surface of the first semiconductor element 12 and the main surface (electronic circuit forming surface) of the second semiconductor element 31 opposite to the main surface of the first semiconductor element 12. 42 is disposed.

  The first adhesive 41 and the second adhesive 42 are appropriately selected according to the flip chip method. For example, a thermosetting adhesive made of a material mainly composed of an epoxy resin can be used. In the adhesives 41 and 42, conductive fine particles such as silver (Ag), gold (Au), copper (Cu) or nickel (Ni) may be added.

  As described above, in the semiconductor device 100 according to the first embodiment of the present invention, the first semiconductor element of the support substrate 11 on which the first semiconductor element 21 is mounted and fixed by the flip-chip method. 21 selectively protrudes in a direction away from the first semiconductor element 21, that is, between the first semiconductor element 21 and the support substrate 11. A recess S that is enlarged in a direction perpendicular to the main surface is formed.

  In the recess S, the second semiconductor element 31 mounted and fixed to the first semiconductor element 21 by a flip chip method is received. That is, the semiconductor device 100 has a so-called chip-on-chip structure including a first semiconductor element 21 mounted on the support substrate 11 and a second semiconductor element 31 mounted on the first semiconductor element 21. However, the second semiconductor element 31 has a configuration in which the second semiconductor element 31 is accommodated and disposed in the recess S between the first semiconductor element 21 and the support substrate 11.

  Therefore, in the semiconductor device 100, an increase in thickness corresponding to substantially the entire thickness of the second semiconductor element 31 is not brought about. Therefore, by combining a plurality of semiconductor elements as a chip-on-chip structure, it is possible to realize a semiconductor device that has higher functions and is thinner and smaller.

  Further, a cured adhesive 41 is disposed between the support substrate 11 and the first semiconductor element 21 and between the support substrate 11 and the second semiconductor element 31, while the first semiconductor element A cured adhesive 42 is disposed between 21 and the second semiconductor element 31.

  For this reason, the connection part of the main surface (electronic circuit formation surface) of the 1st semiconductor element 21 and the support substrate 11 is protected by the adhesive agent 41, and the main surface of the said 1st semiconductor element 21 and 2nd A connection portion with the main surface (electronic circuit forming surface) of the semiconductor element 31 is protected by an adhesive 42. Therefore, the connection between the support substrate 11 and the first semiconductor element 21 is maintained by the adhesive 41, while the connection between the first semiconductor element 21 and the second semiconductor element 31 is maintained by the adhesive 42. The bent shape of the support substrate 11 can be fixed and held. Thereby, a highly reliable semiconductor device can be realized.

(Second Embodiment)
A semiconductor device 200 according to the second embodiment of the present invention is shown in FIG. In FIG. 4, the same reference numerals are given to the parts corresponding to the parts shown in FIG. 1, and the description thereof is omitted.

  In the semiconductor device 200, the first semiconductor element 21 is mounted and fixed on one main surface (upper surface) of the support substrate 11 by a flip chip method.

  The first semiconductor element 21 is similar to the first semiconductor element in the first embodiment with respect to a semiconductor substrate made of a semiconductor such as silicon (Si) or a compound semiconductor such as gallium arsenide (GaAs). A known semiconductor manufacturing process (so-called wafer process) is applied, and an electronic circuit portion is formed on one main surface thereof.

  A region of the support substrate 11 facing one main surface (electronic circuit forming surface) of the first semiconductor element 21 selectively protrudes in a direction away from the first semiconductor element 21. The gap between the first semiconductor element 21 and the support substrate 11 is expanded in the vertical direction, that is, in the direction perpendicular to the main surface of the first semiconductor element 21, so that a recess S is formed. The concave portion S is located at a substantially central portion of the support substrate 11.

  In the semiconductor device 200, the second semiconductor element 31 is mounted and fixed to the electrode on the support substrate 11 in a flip chip manner in the recess S.

  That is, in the recess S of the support substrate 11, the electrode terminal 14 is disposed as a part of the conductive layer of the support substrate 11, and the external connection terminal of the second semiconductor element 31 is connected to the electrode terminal 14. Yes.

  Each of the external connection terminal pads 32 formed on the main surface (electronic circuit formation surface) of the second semiconductor element 31 is provided with a convex external connection terminal 33. The electrode terminals 14 of the support substrate 11 are electrically and mechanically connected via the convex external connection terminals 33. In such a configuration, an insulating layer 25 is selectively disposed in an electronic circuit forming region on the main surface of the first semiconductor element 21 at a portion facing the second semiconductor element 31. . The arrangement of the insulating layer 25 is shown in FIG.

  That is, in the region surrounded by the external connection terminal pads 22 arranged in the vicinity of the four sides of the electronic circuit formation surface of the first semiconductor element 21, the electronic circuit formation portion is covered and the insulating layer 25 is arranged.

  The insulating layer 25 is selected from a material mainly composed of, for example, polyimide resin, silicon resin, or epoxy resin, and has elasticity. The thickness is set to 1 μm to 15 μm, for example.

  By disposing the insulating layer 25, the first semiconductor element 21 and the second semiconductor element 31 can be reliably insulated and separated, and malfunction caused by contact between the two semiconductor elements can be prevented. .

  In addition, since the insulating layer 25 has elasticity, the first semiconductor element is applied by a load applied when the first semiconductor element 21 is flip-chip mounted on the support substrate 11 in the manufacturing process of the semiconductor device 200. It is possible to prevent the electronic circuit forming portion 21 from being damaged. That is, when the first semiconductor element 21 is flip-chip mounted, the insulating layer 25 relieves stress acting on the first semiconductor element 21 by the second semiconductor element 31 mounted on the support substrate 11. Thus, it functions as a stress relaxation layer that prevents the main surface (electronic circuit formation surface) of the first semiconductor element 21 from being broken.

  As an arrangement of the external connection terminal pads 22 and the insulating layer 25 on the main surface of the first semiconductor element 21, the configuration shown in FIG. 6A or FIG. 6B can be applied.

  That is, in the example shown in FIG. 6A, the external connection terminal pad 22 extends along the two sides in the vicinity of two sides facing each other among the four sides constituting the outer periphery of the main surface of the first semiconductor element 21C. Are arranged in a row. An insulating layer 25 is disposed between the external connection terminal pads 22 formed to face each other.

  On the other hand, in the example shown in FIG. 6B, external connection terminal pads 22-1 and 22-2 are arranged in a plurality of rows in the vicinity of each of the four sides constituting the outer periphery of the main surface of the first semiconductor element 21D. It is installed. An insulating layer 25 is disposed between the external connection terminal pads 22-2 formed to face each other.

  In the embodiment shown in FIG. 4, the insulating layer 25 is disposed on the main surface (electronic circuit forming surface) of the first semiconductor element 21. The insulating layer 25 is formed on the first semiconductor element. You may arrange | position on the 2nd main surface (back surface, electronic circuit non-formation surface) of the 2nd semiconductor element 31 located facing the element 21. FIG.

  Then, a cured first adhesive 41 is disposed between the main surface of the first semiconductor element 21 and the support substrate 11, and between the main surface of the second semiconductor element 31 and the support substrate 11. A cured second adhesive 43 is disposed between them. The second adhesive 43 is appropriately selected according to the flip-chip method, but is selected from thermosetting adhesives as with the first adhesive 41. An external connection terminal 13 made of a spherical electrode terminal is disposed on a conductive layer (not shown) disposed on the other main surface (back surface) of the support substrate 11.

  The height of the external connection terminal 13 has a value exceeding the position (height) of the lower surface US of the support substrate 11 formed corresponding to the recess S.

  As described above, in the semiconductor device 200 according to the second embodiment of the present invention, the first semiconductor element of the support substrate 11 on which the first semiconductor element 21 is mounted and fixed by the flip-chip method. 21 is selectively deformed in a direction away from the first semiconductor element 21, and the space between the first semiconductor element 21 and the support substrate 11 is the main part of the first semiconductor element 21. A recess S that is enlarged in a direction perpendicular to the surface is formed.

  Then, in the recess S, the second semiconductor element 31 is mounted and fixed to the support substrate 11 by a flip chip method, and the first semiconductor element 21 is superimposed on the second semiconductor element 31. It is installed.

  In other words, the semiconductor device 200 includes a first semiconductor element 21 and a second semiconductor element 31 mounted on the support substrate 11, and the second semiconductor element 31 includes the first semiconductor element 21 and the support substrate. 11 is accommodated and arranged in the recess S between the two.

  Therefore, in the semiconductor device 200, the thickness corresponding to substantially the entire thickness of the second semiconductor element 31 in spite of the two semiconductor elements being superimposed on the support substrate 11. There is no increase in height. Therefore, by combining a plurality of semiconductor elements, it is possible to realize a semiconductor device that has a high function and is thinner and smaller.

  Further, an adhesive 41 is disposed between the first semiconductor element 21 and the support substrate 11, while an adhesive 43 is disposed between the second semiconductor element 31 and the support substrate 11. Has been. That is, the connection portion between the main surface (circuit formation surface) of the first semiconductor element 21 and the support substrate 11 is sealed and protected by the adhesive 41, and the main surface of the second semiconductor element 31. A connection portion between the (circuit forming surface) and the support substrate 11 is sealed and protected by an adhesive 43.

  Thereby, the connection between the support substrate 11 and the first semiconductor element 21 is maintained by the adhesive 41, while the connection between the support substrate 11 and the second semiconductor element 31 is maintained by the adhesive 43 and the support is supported. The bent shape of the substrate 11 is maintained.

  Further, by disposing the insulating layer 25 between the first semiconductor element 21 and the second semiconductor element 31, the semiconductor elements are reliably separated from each other, and malfunction due to contact between the two semiconductor elements is prevented. . Accordingly, a semiconductor device having higher reliability can be realized.

(Third embodiment)
A semiconductor device 300 according to a third embodiment of the present invention is shown in FIG.

  In FIG. 7, the parts corresponding to the parts shown in FIG. 1 or FIG.

  In the semiconductor device 300, the semiconductor element 21 is mounted and fixed on one main surface (upper surface) of the support substrate 11 by a flip chip method.

  A region of the support substrate 11 that faces one main surface (electronic circuit formation surface) of the semiconductor element 21 protrudes in a direction that is selectively separated from the semiconductor element 21. A recess S is formed in which the gap with the substrate 11 is enlarged in the vertical direction, that is, in the direction perpendicular to the main surface of the semiconductor element 21. The concave portion S is located at a substantially central portion of the support substrate 11.

  In the semiconductor device 300, a plurality of passive elements 51 are connected to and mounted on the electrode terminals 15 on the support substrate 11 in the recess S.

  That is, in the recess S of the support substrate 11, the electrode terminal 15 is disposed as a part of the conductive layer of the support substrate 11, and the electrode of the passive element 51 is connected to the electrode terminal 15 via the conductive member 52. ing.

  The passive element 51 is a so-called chip component having a plate shape or a column shape, and corresponds to, for example, a capacitive element that functions as a bypass capacitor, an inductor that functions as a noise filter, or a resistive element. The passive element 51 includes an insulating element body 51a and a plurality of electrode terminals 51b disposed on both ends or one main surface of the element body 51a. The passive element 51 is appropriately selected according to the circuit configuration, scale, and the like of the semiconductor element 21, and the position and direction of the electrode terminal 15 are selected so as to be as close as possible to the electrode terminal of the semiconductor element 21 to be connected. Is done.

  The electrode terminal 51 b of the passive element 51 and the electrode terminal 15 of the support substrate 11 are electrically connected via a conductive member 52. As the conductive member 52, for example, a conductive material containing conductive fine particles such as silver (Ag), gold (Au), copper (Cu), nickel (Ni), or carbon black in an epoxy resin or a silicon resin. An adhesive or a solder material such as tin (Sn) -silver (Ag) solder or tin (Sn) -silver (Ag) -copper (Cu) solder is used.

  An external connection terminal 13 made of a spherical electrode terminal is disposed on a conductive layer (not shown) disposed on the other main surface (back surface) of the support substrate 11.

  The height of the external connection terminal 13 has a value exceeding the position (height) of the lower surface US of the support substrate 11 formed corresponding to the recess S.

  As described above, in the semiconductor device 300 according to the third embodiment of the present invention, the portion of the support substrate 11 on which the semiconductor element 21 is mounted and fixed by the flip chip method is opposed to the semiconductor element 21. Optionally, a recess S is formed that protrudes in a direction away from the semiconductor element 21 and is enlarged in a direction perpendicular to the main surface of the semiconductor element 21 between the semiconductor element 21 and the support substrate 11. Has been.

  And in the said recessed part S, the passive element 51 is mounted with respect to the support substrate 11, and the said semiconductor element 21 is mounted on the said passive element 51 so that it may overlap. That is, the semiconductor device 300 includes the semiconductor element 21 and the passive element 51 mounted on the support substrate 11, and the second passive element 51 is accommodated in the recess S between the semiconductor element 21 and the support substrate 11. -It has an arranged form.

  Therefore, the semiconductor device 300 substantially corresponds to the total thickness (height) of the passive element 51 even though the semiconductor element and the passive element are superimposed on the support substrate 11. No increase in thickness is brought about. Therefore, by combining a semiconductor element and a passive element, it is possible to realize a semiconductor device that is thinner and smaller while improving operational stability.

  An adhesive 41 is disposed between the semiconductor element 21 and the support substrate 11. That is, the connection portion between the main surface (circuit forming surface) of the semiconductor element 21 and the support substrate 11 and the passive element 51 are covered and protected by the adhesive 41. Accordingly, the connection between the support substrate 11 and the semiconductor element 21 and the connection between the support substrate 11 and the passive element 51 are maintained by the adhesive 41, and the bent shape of the support substrate 11 is maintained. Therefore, a highly reliable semiconductor device can be realized.

(Fourth embodiment)
A semiconductor device 400 according to a fourth embodiment of the present invention is shown in FIG.

  Also in FIG. 8, parts corresponding to those shown in FIG. 1, FIG. 4 and the like are denoted by the same reference numerals, and description thereof is omitted.

  In the semiconductor device 400, the first semiconductor element 21 is mounted and fixed on one main surface (upper surface) of the support substrate 11 by a flip chip method.

  A region of the support substrate 11 facing one main surface (electronic circuit forming surface) of the first semiconductor element 21 selectively protrudes in a direction away from the first semiconductor element 21. A recess S is formed in which the gap between the first semiconductor element 21 and the support substrate 11 is enlarged in the vertical direction, that is, in the direction perpendicular to the main surface of the first semiconductor element 21. The concave portion S is located at a substantially central portion of the support substrate 11.

  In the semiconductor device 400, in the recess S, the second semiconductor element 31 faces the one main surface (electronic circuit formation surface) and the die bond material 61 on the support substrate 11. The electrode 32 of the second semiconductor element 31 is connected to the electrode terminal 16 on the support substrate 11 via a bonding wire 34. Further, the second semiconductor element 21 is sealed with a sealing resin 62 together with the bonding wires 34. The die bond material 61 is made of a material mainly composed of, for example, polyimide resin or epoxy resin, and the electrode terminal 16 is made of the same material as the electrode terminal 12.

  Note that the surface of the external connection terminal pad 32 disposed on the main surface of the second semiconductor element 31 has, for example, a nickel (Ni) / gold (Au) two-layer plating layer in order from the lower layer. You may form by the electroplating method etc. The external connection terminal pad 32 of the second semiconductor element 31 and the electrode terminal 16 of the support substrate 11 are connected by a bonding wire 34 mainly composed of metal such as gold (Au) or copper (Cu). .

  The sealing resin 62 is made of a material mainly composed of an epoxy resin, for example.

  An external connection terminal 13 made of a spherical electrode terminal is disposed on a conductive layer (not shown) disposed on the other main surface (back surface) of the support substrate 11.

  The height of the external connection terminal 13 has a value exceeding the position (height) of the lower surface US of the support substrate 11 formed corresponding to the recess S.

  As described above, in the semiconductor device 400 according to the fourth embodiment of the present invention, the first semiconductor element of the support substrate 11 on which the first semiconductor element 21 is mounted and fixed by the flip-chip method. 21 is selectively protruded in a direction away from the first semiconductor element 21, and the main surface of the first semiconductor element 21 is between the first semiconductor element 21 and the support substrate 11. The recessed part S expanded in the direction perpendicular | vertical with respect to is formed.

  In the recess S, the second semiconductor element 31 is mounted and fixed in a so-called face-up state with respect to the support substrate 11, and the first semiconductor element 21 is superimposed on the second semiconductor element 31. It is installed. In other words, the semiconductor device 400 includes the first semiconductor element 21 and the second semiconductor element 31 mounted on the support substrate 11, and the second semiconductor element 31 includes the first semiconductor element 21 and the support substrate. 11 is accommodated and arranged in the recess S between the two.

  Therefore, in the semiconductor device 400, although the two semiconductor elements are superimposed on the support substrate 11, the thickness substantially corresponds to the entire thickness of the second semiconductor element 31. Will not increase. Therefore, by combining a plurality of semiconductor elements, it is possible to realize a semiconductor device that has a high function and is thinner and smaller.

  Moreover, it hardened | cured between the 1st semiconductor element 21 and the support substrate 11, and between the upper surface of the sealing resin 62 which has coat | covered the 1st semiconductor element 21 and the 2nd semiconductor element 31. An adhesive 41 is provided. That is, the connection portion between the main surface (electronic circuit forming surface) of the first semiconductor element 21 and the main surface of the support substrate 11 is sealed and protected by the adhesive 41.

  On the other hand, the connection portion between the main surface (electronic circuit forming surface) of the second semiconductor element 31 and the support substrate 11 is sealed and protected by a sealing resin 62. Therefore, the connection between the support substrate 11 and the first semiconductor element 21 is maintained by the adhesive 41, and the connection between the support substrate 11 and the second semiconductor element 31 is maintained by the sealing resin 62, and the support is supported. The bent shape of the substrate 11 can be fixed. Therefore, a highly reliable semiconductor device can be realized.

  A method of manufacturing a semiconductor device according to the present invention having such a characteristic configuration will be described below.

[Method for Manufacturing Semiconductor Device]
(Method for Manufacturing Semiconductor Device 100)
A method of manufacturing the semiconductor device 100 according to the first embodiment of the present invention will be described with reference to FIGS.

  In manufacturing the semiconductor device 100, first, the second semiconductor element 31 is flip-chip (face-down) mounted on one main surface (electronic circuit formation surface) of the first semiconductor element 21.

  As the flip chip mounting method, a thermocompression bonding method with an adhesive interposed, a soldering (brazing) bonding method, a thermocompression bonding method, an ultrasonic bonding method, or a connection method using an anisotropic conductive resin. Etc. can be applied.

  That is, in this manufacturing method, the second semiconductor element 31 is flip-chip mounted on one main surface (electronic circuit formation surface) of the first semiconductor element 21 with the adhesive 42 interposed. As a result, one main surface (electronic circuit formation surface) of the second semiconductor element 31 faces one main surface (electronic circuit formation surface) of the first semiconductor element 21. This will be described with reference to FIG.

In the flip chip mounting method, first, the first semiconductor element 21 is placed on the bonding stage 71 by vacuum suction through the suction hole 72, and one main surface (electronic circuit formation surface) is the upper surface. That is, the one main surface (electronic circuit forming surface) is exposed and held by suction. (See Fig. 9 (a))
A convex external connection terminal 24 is formed in advance on the first external connection terminal pad 22 on one main surface (electronic circuit formation surface) of the first semiconductor element 21. As the external connection terminal 24, a metal bump formed by a so-called ball bonding method or an electrolytic plating method using a wire bonding technique, or a gold bump formed by an electrolytic plating method, a transfer method, a printing method, or the like is used. it can.

  Further, in the later step, the surface of the second external connection terminal pad 23 to which the external connection terminal of the second semiconductor element 31 is connected is sequentially deposited from the lower layer by electrolytic plating or electroless plating. A nickel (Ni) / gold (Au) bilayer plating layer or a solder coating such as tin (Sn) or tin (Sn) alloy is applied.

  Further, an adhesive 42 made of a thermosetting material mainly composed of an epoxy resin is selectively applied to the surface region of the first semiconductor element 21 surrounded by the second external connection terminal pad 22. Has been.

  On the other hand, the second semiconductor element 31 is adsorbed on a bonding tool (jig) 81 heated to a predetermined temperature in advance through the adsorption hole 82 on the other main surface (rear surface, non-electronic circuit formation surface). Retained.

  As the external connection terminal 33, a metal bump by a so-called ball bonding method or an electrolytic plating method using a wire bonding technique, or a solder bump formed by an electrolytic plating method, a transfer method, a printing method, or the like is applied. The total value of the thickness of the second semiconductor element 31 and the height of the external connection terminal 33 disposed on the external connection terminal pad 32 of the second semiconductor element 31 is the first value. The semiconductor element 21 has a thickness (height) greater than the height of the external connection terminal 24 formed on the first external connection terminal pad 22.

  The external connection terminal 33 of the second semiconductor element 31 and the second external connection terminal pad 23 of the first semiconductor element 21 are opposed to perform alignment.

  Thereafter, the bonding tool 81 is lowered, and the external connection terminal 33 of the second semiconductor element 31 is pressed against and brought into contact with the second external connection terminal pad 23 of the first semiconductor element 21. Then, a predetermined load is applied to the external connection terminal 23 of the second semiconductor element 31 by the bonding tool 81, and the external connection terminal 23 of the second semiconductor element 31 is connected to the second connection terminal of the first semiconductor element 21. Connect to the external connection terminal pad 23.

  At this time, the adhesive 42 flows over the entire lower surface of the second semiconductor element 31 (the surface on which the electronic circuit is formed, the surface facing the first semiconductor element 21), and the second semiconductor element 31 and the first semiconductor element 31. It reaches between the semiconductor element 21 and the outer periphery of the side surface of the second semiconductor element 31.

Further, the adhesive 42 is thermally cured by heating from the bonding tool 81. (See Fig. 9 (b))
As a result, the second semiconductor element 31 is flip-chip mounted on the first semiconductor element 21.

Thereafter, the suction of the bonding tool 81 is released, and the bonding tool 81 and the second semiconductor element 31 are separated. For this reason, the bonding tool 81 is raised. (See Fig. 9 (c))
The step of arranging the external connection terminal 24 on the first external connection terminal pad 22 of the first semiconductor element 21 may be performed after the flip chip mounting process of the second semiconductor element 31 is performed. it can.

  Next, the first semiconductor element 21 in which the second semiconductor element 31 is flip-chip mounted is flip-chip mounted on the support substrate 11.

  A process of flip-chip mounting the first semiconductor element 21 on the support substrate 11 is shown in FIGS.

  Here, as the flip chip mounting method, a method in which the first semiconductor element 21 is thermocompression bonded to the support substrate 11 with an adhesive 41 interposed therebetween is used. As the flip chip mounting method, as long as heating and pressurization are performed by a bonding tool that holds the first semiconductor element 21 by suction, a method of thermocompression bonding with an adhesive interposed, soldering (brazing) bonding, or the like. It is possible to use a combination method, a thermocompression bonding method, a connection method using an anisotropic conductive resin, or the like.

First, the support substrate 11 is sucked and held on the bonding stage 91 by vacuum suction through the suction holes 92. (See Fig. 10 (a))
As a characteristic configuration in the embodiment of the present invention, a concave portion 93 is selectively disposed on the upper surface of the bonding stage 91. The concave portion 93 has a planar shape, size, and depth that allow the second semiconductor element 31 to be received together with a part of the support substrate 11. On the upper surface of the support substrate 11, a plurality of conductive layers formed on the support substrate 11 are arranged as first electrode terminals 12.

  Then, on the upper surface of the support substrate 11, an adhesive 41 made of a thermosetting material mainly composed of an epoxy resin is applied to a region surrounded by the plurality of first electrode terminals 12. Yes.

  The bonding stage 91 is heated to about 50 ° C. to 100 ° C.

  On the other hand, in the first semiconductor element 21 on which the second semiconductor element 31 is flip-chip mounted as described above, the second main surface (back surface, electronic circuit non-formation surface) has a predetermined temperature (270 ° C. or higher). It is sucked and held by the bonding tool 86 heated to 300 ° C. through the suction hole 87.

  Then, the external connection terminal 24 of the first semiconductor element 21 and the first electrode terminal 12 of the support substrate 11 are opposed to each other for alignment.

  As a result, the second semiconductor element 31 flip-chip mounted on the first semiconductor element 21 has its back surface (surface on which the electronic circuit is not formed) facing the adhesive 41 attached on the support substrate 11. It is assumed that

  After such alignment, the bonding tool 86 is lowered (arrow H).

  The time lapse of the position of the lower end surface of the bonding tool 86 is shown in FIG. 12A, and the time lapse of the load detected by a load sensor (not shown) connected to the bonding tool 86 is shown in FIG. Shown in b).

  12A and 12B, the position of the external connection terminal 24 of the first semiconductor element 21 and the first electrode terminal 12 of the support substrate 11 shown in FIG. Indicates the time when they were combined.

By lowering the bonding tool 86, the back surface (surface on which no electronic circuit is formed) of the second semiconductor element 31 flip-chip mounted on the first semiconductor element 21 contacts the support substrate 11 through the adhesive 41. To do. (See FIG. 10 (b))
The time when the contact occurs is defined as time T0. At this time, the total value of the thickness of the second semiconductor element 31 and the height of the external connection terminal 33 disposed on the external connection terminal pad 32 of the second semiconductor element 31 is the first semiconductor element 21. Since the height of the external connection terminal 24 formed on the first external connection terminal pad 22 is set to be larger than that of the external connection terminal 24 in the first semiconductor element 21, The lower end surface of the bonding tool 86 (the surface facing the support substrate 11) is not at the electrode terminal 12 and is at the height Z1.

  Thereafter, the pressing force accompanying the lowering of the bonding tool 86 is applied to the support substrate 11 via the first semiconductor element 21, the second semiconductor element 31, and the adhesive 42.

  Due to the pressing force, at least the back surface of the second semiconductor element 31 and the portion located around the support substrate 11 are pressed into the recessed portion 93 provided in the upper portion of the bonding stage 91 to extend.

  At this time, the bonding tool 86 is heated to a predetermined temperature as described above. The heat from the bonding tool 86 is conducted to the second semiconductor element 31 via the first semiconductor element 21 and the external connection terminal 24, and the support substrate 11 adjacent to the second semiconductor element 31 is locally To be heated. By such heating, local thermal expansion occurs and proceeds in the support substrate 11, and the support substrate 11 easily expands into the concave portion 93 in the bonding stage 91 and starts to bend.

  That is, as shown in FIG. 12B, the repulsive force acting on the bonding tool 86 from the support substrate 11 temporarily rises as the pressing force is applied by the bonding tool 86, but as the time elapses, the support substrate 11 With the deformation (elongation, deflection), the repulsive force decreases. In the figure, the strength of the repulsive force is displayed as the corresponding pressing load.

  The heating of the support substrate 11 further facilitates the extension of the support substrate 11 due to the pressing of the bonding tool 86, and the heating temperature is set to a temperature equal to or higher than the glass transition temperature of the support substrate 11. Thus, the support substrate 11 can be more easily deformed and bent.

  By applying such a pressing force and heating, the support substrate 11 extends and bends along the inner surface of the concave portion 93 in the concave portion 93 of the bonding stage 91, thereby generating the first semiconductor. A recess S that can receive the second semiconductor element 31 starts to be formed between the element 21 and the support substrate 11.

  In addition, the adhesive 41 that has been deposited on the support substrate 11 is reduced in viscosity due to the heat from the bonding tool 86 conducted by the contact between the support substrate 11 and the second semiconductor element 31, and has a fluidity. As a result, the first semiconductor element 21 is spread over the entire region facing the support substrate 11 between the support substrate 11 and the first semiconductor element 21.

Then, the bonding tool 86 is further lowered to bring the external connection terminal 24 in the first semiconductor element 21 into contact with the electrode terminal 12 on the support substrate 11. (First pressing by position control)
The time when the contact occurs is defined as time T1. (See Fig. 10 (c))
At this time, the lower end surface of the bonding tool 86 is at the position of the height Z2.

  When the external connection terminal 24 in the first semiconductor element 21 is in contact with the first electrode terminal 12 of the support substrate 11, the heat of the bonding tool 86 is changed to the first semiconductor element 21 and the second semiconductor element 21. Conduction is performed to the support substrate 11 through the semiconductor element 31, the external connection terminal 33, and the external connection terminal 24. Accordingly, the adhesive 41 further flows and reaches the periphery of the external connection terminal 12.

Flip chip mounting of the first semiconductor element 21 to the support substrate 11 is completed from the time when the external connection terminal 24 in the first semiconductor element 21 and the electrode terminal 12 on the support substrate 11 contact each other as described above. Until it is done (from time T1 to time T3), the load detected by the load sensor is controlled. (Second pressing by load control)
Then, control is performed so that the load detected by the load sensor reaches the set value F at time T2. The set value F is set to 10 gf to 60 gf for each external connection terminal 24 formed in the first semiconductor element 21. (See FIG. 12 (b))
By the application of the load, the external connection terminal 24 formed on the first semiconductor element 21 is connected to the first electrode terminal 12 of the support substrate 11. At this time, since the plastic deformation is accompanied (collapsed), the position of the lower end surface of the bonding tool 86 is slightly lowered from the height Z2 and located at the height Z3. (See FIG. 11 (d))
The load that has reached the set value at time T2 is maintained until a predetermined time T3.

  From time T2 to time T3, the support substrate 11 is heated by heat transfer from the bonding tool 86 via the first semiconductor element 21, the second semiconductor element 31, the external connection terminal 33, and the external connection terminal 24, The heating area is enlarged, and the local thermal expansion of the support substrate 11 further proceeds.

  As a result, the extension / deflection of the support substrate 11 in the recess 93 of the bonding stage 91 proceeds, and the repulsive force acting on the first semiconductor element 21 from the support substrate 11 via the second semiconductor element 31 decreases. .

  Further, between the support substrate 11 and the first semiconductor element 21, the thermosetting of the adhesive 41 that is spread over the entire area of the first semiconductor element 21 and reaches the periphery of the external connection terminal 24 proceeds. To do.

  In order to more effectively apply the load by the bonding tool 86, the suction hole 92 in the bonding stage 91 is external to the first electrode terminal 12 in the support substrate 11 in the first semiconductor element 21. It is arranged at a position different from the position directly below the connection position of the connection terminal 24.

At time T3, the mounting of the first semiconductor element 21 on the support substrate 11 is completed. (See FIG. 11 (e))
At this time, the distance between the support substrate 11 and the back surface of the second semiconductor element 31 is increased, and a repulsive force from the support substrate 11 to the first semiconductor element 21 via the second semiconductor element 31 is generated. Absent. The load detected by the load sensor maintains the set value F.

  Further, the lower end surface of the bonding tool 86 is maintained at the position of the height Z3.

  Then, the adhesive 41 is cured in a state where the support substrate 11 has a bent shape in the concave portion 93 of the bonding stage 91. Thereby, underfilling by the adhesive 41, that is, the circuit forming surface of the first semiconductor element 21 and the external connection terminal 24 are protected, and the first semiconductor element 21 and the support substrate 11 are fixed. The connection between the first semiconductor element 21 and the support substrate 11 via the external connection terminal 24 is maintained by the adhesive force and the curing shrinkage force of the adhesive 41.

When the first semiconductor element 21 is mounted on the support substrate 11, the suction of the bonding tool 86 is released and the bonding tool 86 is raised (arrow I). (Time Te, see FIG. 11 (f))
With the release of pressure by the bonding tool 86 and the curing and shrinkage of the adhesive 41, the support substrate 11 slightly lifts upward in the recess 93 of the bonding stage 91, and the support substrate 11 is lifted from the bonding stage 91. It is easy to take out.

  Then, external connection terminals are disposed on the support substrate 11 taken out from the bonding stage 91.

  That is, a plurality of external connection terminals 13 such as spherical electrode terminals mainly composed of solder are disposed on a conductive layer (not shown) selectively provided on the other main surface (back surface) of the support substrate 11. Then, the semiconductor device 100 shown in FIG. 1 is formed.

  As described above, in the manufacturing method according to the present embodiment, the pressure applied to the support substrate 11 by the bonding tool 86 is provided on the bonding stage 91 that includes the recess 93 and supports the support substrate 11. The first semiconductor element 21 flip-chip mounted on the support substrate 11 and the second semiconductor element 31 flip-chip mounted on the first semiconductor element 21 are performed. As a result, the support substrate 11 is locally pressurized on the recess 93.

  The support substrate 11 is locally heated by heat conducted from the bonding tool 86 via the first semiconductor element 21 and the second semiconductor element 31.

  As a result, the support substrate 11 extends in a direction away from the main surface on which the first semiconductor element 21 is mounted in the concave portion 93 of the bonding stage 91, and is bent. That is, a concave portion S capable of receiving the second semiconductor element 31 is formed in the support substrate 11 by the local extension and deflection of the support substrate 11 caused by the local pressurization and heating. . The recess S receives the second semiconductor element 31 in the thickness direction.

  Accordingly, even if the two semiconductor elements of the first semiconductor element 21 and the second semiconductor element 31 are disposed on the support substrate 11 in a stacked state, the thickness substantially corresponds to the entire thickness of the second semiconductor element 31. Increase in thickness (height).

  That is, in the manufacturing method according to the present embodiment, a semiconductor device that includes a plurality of semiconductor elements, the first semiconductor element 21 and the second semiconductor element 31, and that is required to be thin and small. Can be manufactured by a simple process, and a reduction in manufacturing cost can be achieved.

  Further, the bonding tool 86 is lowered while controlling the height position thereof, and the external connection terminal 24 formed on the first semiconductor element 21 is brought into contact with the first electrode terminal 12 of the support substrate 11. The load 86 is controlled to apply a load to the external connection terminal 24. Therefore, the external connection terminal 24 can be reliably connected to the first electrode terminal 12 of the support substrate 11 by such a load, and a mounting structure with high connection reliability can be obtained.

  At time T2, when the adhesive 41 is cured, the flip chip mounting of the first semiconductor element 21 to the support substrate 11 is completed. At this time, the suction of the bonding tool 86 is released. The bonding tool 86 may be raised.

  In addition, after the flip chip mounting of the first semiconductor element 21 to the support substrate 11 is completed, the post-curing process is performed, and the adhesion disposed between the second semiconductor element 31 and the first semiconductor element 21 is performed. The agent 42 may be cured.

  The inventor of the present invention was able to manufacture the semiconductor device 100 shown in FIG. 1 using the manufacturing method in the present embodiment under the following conditions.

  That is, a glass epoxy substrate having a thickness of 0.3 mm and a four-layer wiring structure was used as the support substrate 11. The glass transition temperature of such a substrate was 170 ° C. to 185 ° C. as a result of measurement by the TMA method defined in the copper clad laminate test method for printed wiring boards.

  As the first semiconductor element 21, a silicon semiconductor element having a size of 13 × 13 mm and a thickness of 200 μm was used. As external connection terminals 24 of the first semiconductor element 21, 840 gold (Au) bumps formed by a ball bonding method using gold (Au) wires were formed.

  On the other hand, as the second semiconductor element 31, a silicon semiconductor element having a size of 6 × 6 mm and a thickness of 100 μm was used. As external connection terminals 33 of the second semiconductor element 31, 380 gold (Au) bumps formed by a ball bonding method using gold (Au) wires were formed.

  The heating temperature of the bonding tool 86 for sucking and holding the first semiconductor element 21 is set to 270 ° C. to 300 ° C., and the heating temperature of the bonding stage 91 for sucking and holding the support substrate 11 is set to 50 ° C. to 100 ° C. did. Further, the concave portion 93 disposed on the bonding stage 91 has a rectangular shape of 8.5 mm × 8.5 mm, and the depth (DS2) is set to 0.2 mm.

  Under such conditions, the first semiconductor element 21 on which the second semiconductor element 31 was flip-chip mounted was flip-chip mounted on the support substrate 11 using the manufacturing method according to the present embodiment.

  The temperature reached by the support substrate 11 at the time of mounting was 200 ° C. to 230 ° C., and the sinking amount due to the bending deformation of the support substrate 11 after mounting was 130 μm.

  FIG. 13 shows a cross-sectional shape of the bottom of the concave portion 93 disposed in the bonding stage 91 and the inner side surface (side wall surface) following the manufacturing method according to the present embodiment.

  This is the portion surrounded by the dotted line A in FIG. 10A, but the illustration of the support substrate 11 is omitted here.

  That is, the inner side surface 93 a of the concave portion 93 has an arc-shaped cross section that extends from the flat concave bottom surface 93 b to the upper surface and has a convex shape toward the inner side of the concave portion 93.

  By adopting such an arc-shaped cross section, the concave portion 93 has an inner surface opened upward, so that when the support substrate 11 extends and bends, the support is supported even if it contacts the inner surface of the concave portion 93. It is possible to suppress and reduce the concentration of stress on a specific portion of the substrate 11, and the wiring layer formed on the support substrate 11 is not damaged.

  The bottom surface 93b of the concave portion 93 is flat, and the depth DS2 of the concave portion 93 is received when the second semiconductor element 31 is received in the thickness direction, and the support substrate 11 extends and bends. The lower surface (second main surface) is set to a depth at which it can contact the bottom surface of the recess 93. Thereby, the amount of bending of the support substrate 11 is limited, and the lower surface of the support substrate 11 exhibits a flat surface.

  In addition, the shape of the inner surface of the recess 93 is not limited to the form shown in FIG.

For example, the inner surface of the recess 93 can be an inclined surface 93aa that extends at an obtuse angle from the bottom. (See Fig. 14 (a))
Further, the inclination angle of the inner side surface can be changed in the middle to obtain inner side surfaces 93ab-1 and 93ab-2 having at least two inclination angles. (See Fig. 14 (b))
Further, the inner side surface may be a vertical surface 93ac-1 from the bottom to a predetermined height, and the inner side surface following this may be an inclined surface 93ac-2 having a predetermined inclination angle. (See Fig. 14 (c))
Further, the inner side surface may be a vertical surface 93ad-1 from the bottom to a predetermined height, and the inner side surface 93ad-2 following this may be arcuate. (See Fig. 14 (d))
In any form, since the recess 93 has an inner surface opened upward, when the support substrate 11 extends and bends, even if it contacts the inner surface of the recess 93, the specific portion of the support substrate 11 It is possible to suppress / reduce the concentration of stress on the wiring substrate, and the wiring layer formed on the support substrate 11 is not damaged.

  Further, in the embodiment described with reference to FIGS. 10 and 11, the pressing force is locally and mechanically applied to the support substrate 11 in the recess 93 provided in the bonding stage 91. While being added and heated, the expansion / deflection is caused. However, the extension / deflection of the support substrate 11 can also be promoted by sucking vacuum (reduced pressure) into the recess 93.

  A processing method involving suction in the recess 93 will be described with reference to FIGS. 15 and 16. In the configuration shown in FIGS. 15 and 16, parts corresponding to the parts shown in FIGS. 10 and 11 are given the same reference numerals, and the description thereof is omitted.

  In this processing method, a suction hole 94 connected to a suction mechanism (not shown) is disposed at the bottom of the concave portion 93 in the bonding stage 91, and the suction hole is driven to drive the suction hole. The inside of the recess 93 is vacuumed (reduced pressure) through 94. Thereby, the semiconductor element mounting portion of the support substrate 11 disposed on the bonding stage 91 is selectively sucked into the concave portion 93.

In this processing method, the support substrate 11 is held on the bonding stage 91 having such a structure by suction through the suction hole 92. (See Fig. 15 (a))
Further, as described above, the concave portion 93 has a planar shape, size, and depth that allow the second semiconductor element 31 to be received together with a part of the support substrate 11. The bonding stage 91 on which the support substrate 11 is placed and fixed is heated to 50 ° C. to 100 ° C. Further, along with this heating, the inside of the recess 93 in the bonding stage 91 is exhausted through the suction hole 94.

  On the upper surface of the support substrate 11, a plurality of conductive layers formed on the support substrate 11 are arranged as first electrode terminals 12.

  On the upper surface of the support substrate 11, a region 41 surrounded by the plurality of first electrode terminals 12 is formed of a thermosetting adhesive 41 made of a material mainly composed of an epoxy resin. It is attached.

  On the other hand, in the first semiconductor element 21 on which the second semiconductor element 31 is flip-chip mounted, the other main surface (back surface / non-electronic circuit formation surface) is previously set to a predetermined temperature (270 ° C. to 300 ° C.). It is sucked and held by the heated bonding tool 86 through the suction hole 87.

  Then, the external connection terminal 24 of the first semiconductor element 21 and the first electrode terminal 12 of the support substrate 11 are opposed to perform alignment.

After such alignment, while controlling the height position, the bonding tool 86 is lowered until the external connection terminal 24 in the first semiconductor element 21 contacts the first electrode terminal 12 of the support substrate 11. Crush (arrow J). (Refer to FIG. 15B, first pressing by position control)
By lowering the bonding tool 86, the back surface (surface on which no electronic circuit is formed) of the second semiconductor element 31 flip-chip mounted on the first semiconductor element 21 first contacts the support substrate 11 via the adhesive 41. To do. Since the thickness of the second semiconductor element 31 is set larger than the height of the external connection terminal 24 formed on the first external connection terminal pad 22 of the first semiconductor element 21, The external connection terminal 24 in one semiconductor element 21 does not contact the electrode terminal 12 on the support substrate 11. Then, the bonding tool 86 is further lowered to bring the external connection terminal 24 of the first semiconductor element 21 into contact with the electrode terminal 12 on the support substrate 11.

  Thereafter, the pressing force generated as the bonding tool 86 is lowered is applied to the support substrate 11 via the first semiconductor element 21, the second semiconductor element 31, and the adhesive 41.

  That is, by this pressing force, at least the mounting portion of the second semiconductor element 31 and its periphery are pressed into the concave portion 93 and the support substrate 11 extends.

  At this time, the bonding tool 86 that holds the first semiconductor element 21 by suction is heated to a predetermined temperature as described above. The heat from the bonding tool 86 is conducted to the second semiconductor element 31 via the first semiconductor element 21 and the external connection terminal 24, and the portion of the support substrate 11 adjacent to the second semiconductor element 31 is locally Heated. By such heating, local thermal expansion occurs and proceeds on the support substrate 11. Accordingly, the support substrate 11 easily expands into the recess 70 and begins to bend due to local thermal expansion due to local heating as well as expansion due to the pressing force.

  In the present processing method, along with such pressurization and heating, the inside of the concave portion 70 of the bonding stage 65 is evacuated, whereby the extension and deflection of the support substrate 11 are promoted.

  That is, by exhausting the inside of the concave portion 70 by suction driving through the suction hole 77, the inside of the concave portion 70 can be decompressed, and the extension / deflection generation portion in the support substrate 11 is sucked, and the extension is performed. -The bending deformation can be promoted. Moreover, since the air in the recessed part 70 reduces by this exhaust, the bending deformation of the support substrate 11 is not inhibited by the thermal expansion of the air.

  On the other hand, the adhesive 41 deposited on the support substrate 11 is reduced in viscosity due to the heat from the bonding tool 86 conducted by the contact between the support substrate 11 and the second semiconductor element 31 and becomes fluid. As a result, the first semiconductor element 21 is spread over the entire region facing the support substrate 11 between the support substrate 11 and the first semiconductor element 21.

Then, the external connection terminal 24 formed on the first semiconductor element 21 is in contact with and connected to the first electrode terminal 12 of the support substrate 11, so that the flip chip mounting of the first semiconductor element 21 to the support substrate 11 is performed. Is made. (See FIG. 16 (c))
The load detected by the load sensor connected to the bonding tool 86 is maintained until the connection of the external connection terminal 24 to the electrode terminal 12 is made. (Second pressing by load control)
When the first semiconductor element 21 is mounted on the support substrate 11, the support substrate 11 maintains a bent shape in the recess 93 of the bonding stage 91, and the adhesive 41 is cured. The connection between the first semiconductor element 21 and the support substrate 11 via the external connection terminal 24 is maintained by the adhesive force and the curing shrinkage force of the adhesive 41.

Next, the suction of the bonding tool 86 is released, and the bonding tool 86 is raised (arrow K). (See Fig. 16 (d))
Thereafter, a plurality of external connection terminals 13 such as spherical electrode terminals mainly composed of solder are disposed on the conductive layer selectively provided on the other main surface (back surface) of the support substrate 11. The semiconductor device 100 shown in FIG. As described above, in the present manufacturing method, the inside of the concave portion 93 disposed in the bonding stage 91 is evacuated by exhausting it through the suction hole 94, and local expansion / deflection occurs / progresses. By pulling the support substrate 11 into the recess 93, the bending deformation can be efficiently advanced. Further, the exhaust prevents the air in the concave portion 93 from thermally expanding and hinders the bending deformation of the support substrate 11. Therefore, a bent shape can be reliably formed on the support substrate 11.

(Method for Manufacturing Semiconductor Device 200)
A method of manufacturing the semiconductor device 200 according to the second embodiment of the present invention will be described with reference to FIGS. In FIGS. 17 to 19, parts corresponding to those shown in FIGS. 9 to 11 are denoted by the same reference numerals and description thereof is omitted.

  In manufacturing the semiconductor device 200, first, the second semiconductor element 31 is flip-chip (face-down) mounted on the support substrate 11. In the flip chip mounting, a thermocompression bonding method with an adhesive interposed, a soldering (brazing) bonding method, a thermocompression bonding method, an ultrasonic bonding method, and a connection method using an anisotropic conductive resin. Various flip chip mounting methods can be applied.

  In this manufacturing method, the second semiconductor element 31 is thermocompression bonded to the support substrate 11 with the adhesive 43 interposed therebetween, and is flip-chip mounted on the support substrate 11. This will be described with reference to FIG.

In the manufacturing method, first, the support substrate 11 is sucked and held on the bonding stage 71 by vacuum suction through the suction hole 81 to expose one main surface (semiconductor element mounting surface). To do. (See Fig. 17 (a))
A part of the conductive layer is exposed as a first electrode terminal 12 on the main surface of the support substrate 11, and the conductive layer of the support substrate 11 is located in a region surrounded by the first electrode terminal 12. As a part, a plurality of second electrode terminals 14 are exposed.

  Further, a second adhesive 43 made of a thermosetting material mainly composed of an epoxy resin is applied to a region surrounded by the second electrode terminal 14.

  On the other hand, the other main surface (rear surface, non-electronic circuit formation surface) of the second semiconductor element 31 is adsorbed and held via an adsorbing hole 82 by a bonding tool 81 heated to a predetermined temperature.

  External connection terminals 33 are arranged on the external connection terminal pads 32 of the second semiconductor element 31. As the external connection terminal 33, a metal bump formed by a so-called ball bonding method or an electrolytic plating method using a wire bonding technique, or a solder bump formed by an electrolytic plating method, a transfer method, a printing method, or the like is applied. The

  Then, the external connection terminal 33 of the second semiconductor element 31 and the second electrode terminal 14 of the support substrate 11 are opposed to perform alignment.

  Thereafter, the bonding tool 81 is lowered, and the external connection terminal 33 of the second semiconductor element 31 is pressed against and brought into contact with the second electrode terminal 14 on the support substrate 11. Then, a predetermined load is applied to the external connection terminal 33 of the second semiconductor element 31 by the bonding tool 81 to connect the external connection terminal 33 to the second electrode terminal 14 on the support substrate 11. At the same time, by heating from the bonding tool 81, the adhesive 43 is caused to flow over the entire main surface (the surface on which the electronic circuit is formed, the surface facing the support substrate 11) of the second semiconductor element 31. It reaches between the semiconductor element 31 and the support substrate 11 and further to the outer peripheral portion of the side surface of the semiconductor element 31.

Then, the adhesive 43 is thermally cured by heating from the bonding tool 81. (See FIG. 17 (b))
As a result, the second semiconductor element 31 is flip-chip mounted on the support substrate 11.

Thereafter, the suction of the bonding tool 81 is released, and the bonding tool 81 is raised. (See FIG. 17 (c))
Next, the first semiconductor element 21 is flip-chip mounted on the support substrate 11 so as to overlap the second semiconductor element 31.

  A process of flip-chip mounting the first semiconductor element 21 on the support substrate 11 is shown in FIGS.

  Here, as the flip-chip mounting method, the first semiconductor element 21 is thermocompression bonded onto the support substrate 11 with the first adhesive 41 interposed. As the flip chip mounting method, as long as heating and pressurization are performed by a bonding tool that holds the first semiconductor element 21 by suction, a method of thermocompression bonding with an adhesive interposed, a bonding method by soldering (brazing), A thermocompression bonding method or a connection method using an anisotropic conductive resin can be applied.

  First, the substrate to be processed 11 is sucked and held on the bonding stage 91 through the suction hole 92.

  Also in the embodiment of the present invention, as a characteristic configuration, a concave portion 93 is selectively provided on the upper surface of the bonding stage 91.

  The recess 93 has a planar shape, size, and depth that allow the second semiconductor element 31 to be received together with a part of the support substrate 11.

  Then, the support substrate 11 is sucked and held on the bonding stage 65 so that the second semiconductor element 31 is located at a substantially central portion of the recess 93. The bonding stage 65 on which the support substrate 11 is mounted is heated to 50 ° C. to 100 ° C.

  The bottom surface of the concave portion 93 and the inner side surface (side wall surface) following the bottom surface have an arc shape in which the cross-sectional shape extends from the bottom surface to the top surface of the concave portion and has a convex shape toward the inside of the concave portion 93. Has been. By adopting such a circular arc shape, the recess 93 has an inner surface opened upward, so that when the support substrate 11 extends and bends, the support substrate 11 is in contact with the inner surface of the recess 93. It is possible to suppress and reduce the concentration of stress on the specific part of the substrate, and the wiring layer formed on the support substrate 11 is not damaged.

  Further, the bottom of the recess 93 is flat, and the depth is such that when the support substrate 11 extends and bends, the lower surface of the support substrate 11 can contact the bottom surface of the recess 93. Set to Thereby, the amount of bending of the support substrate 11 is limited, and the lower surface of the support substrate 11 is formed with a flat surface.

  In addition, the shape of the inner side surface (side wall surface) of the recessed part 93 is not restricted to the said form, The form shown in the said FIG. 14 can also be applied.

Then, an area surrounded by the plurality of first electrode terminals 12 on the upper surface of the support substrate 11 sucked and held on the bonding stage 91 covers the second semiconductor element 31, for example, an epoxy system An adhesive 41 made of a thermosetting material mainly composed of resin is applied. (See FIG. 18 (d))
The coating of the adhesive 41 may be performed continuously after the second semiconductor element 31 is flip-chip mounted on the support substrate 11 on the bonding stage 91.

  On the other hand, in the first semiconductor element 21, the other main surface (back surface / electronic circuit non-formed surface) is heated to a predetermined temperature (270 ° C. to 300 ° C.) via a suction hole 87. Adsorbed and retained.

  A convex external connection terminal 24 is disposed on the first external connection terminal pad 22 of the first semiconductor element 21.

  The region of the electronic circuit formation surface of the first semiconductor element 21 and surrounded by the first external connection terminal pad 22 is mainly made of, for example, polyimide resin, silicon resin, or epoxy resin. An insulating layer 25 having elasticity, which is appropriately selected from the materials described above, is provided. The thickness of the insulating layer 25 is set to 1 μm to 15 μm.

  Next, the external connection terminal 24 of the first semiconductor element 21 and the first electrode terminal 12 of the support substrate 11 are opposed to perform alignment.

At this time, the first semiconductor element 21 is located on the second semiconductor element 21, and its main surface (electronic circuit forming surface) is the back surface (electronic circuit non-forming surface) of the second semiconductor element 31. Opposite. Then, the bonding tool 86 is lowered while controlling the height position thereof until the external connection terminal 24 in the first semiconductor element 21 contacts the first electrode terminal 12 of the support substrate 11 (arrow L). ). (See FIG. 18 (e)) (first press by position control)
Accordingly, a predetermined load is applied to the external connection terminal 24 of the first semiconductor element 21 by the bonding tool 75, and the external connection terminal 24 of the first semiconductor element 21 is applied to the electrode terminal 12 of the support substrate 11. Connected. At the same time, the first semiconductor element 21 presses the back surface of the second semiconductor element 31 via the insulating layer 25 disposed on the surface thereof.

  Therefore, the pressing force accompanying the lowering of the bonding tool 75 is applied to the support substrate 11 via the first semiconductor element 21, the second semiconductor element 31, and the adhesive 41.

  That is, by this pressing force, at least the second semiconductor element 31 mounting portion and the periphery thereof are pressed into the recess 93 in the bonding stage 91 and extended.

  At this time, the bonding tool 86 that holds the first semiconductor element 21 by suction is heated to a predetermined temperature.

  Heat in the bonding tool 86 is conducted to the support substrate 11 through the first semiconductor element 21 and the second semiconductor element 31. Accordingly, the support substrate 11 is locally heated, and local thermal expansion occurs and proceeds, and the support substrate 11 easily extends and bends into the recess 93.

  Furthermore, the viscosity of the adhesive 41 disposed on the support substrate 11 decreases due to heat from the bonding tool 86 conducted by contact between the support substrate 11 and the second semiconductor element 31. Its fluidity is improved. Therefore, the adhesive 41 is spread and flows over the entire area of the first semiconductor element 21 between the support substrate 11 and the first semiconductor element 21, and the thermosetting proceeds.

The external connection terminal 24 in the first semiconductor element 21 comes into contact with the first electrode terminal 12 of the support substrate 11, and the flip chip mounting of the first semiconductor element 21 to the support substrate 11 is completed. Until then, the load detected by a load sensor (not shown) is controlled. (See FIG. 19 (f)) (second pressing by load control)
As described above, the insulating layer 25 disposed on the electronic circuit formation surface of the first semiconductor element 21 has elasticity. Therefore, when flip chip mounting is performed, even if a load is applied to the electronic circuit formation surface of the first semiconductor element 21, it is possible to prevent damage to the electronic circuit formation surface. That is, when the first semiconductor element 21 is flip-chip mounted on the support substrate 11 so as to overlap the second semiconductor element 31, the insulating layer 25 is formed from the back surface of the second semiconductor element 31. It functions as a stress relaxation layer that relieves stress acting on the electronic circuit formation surface of the semiconductor element 21.

  When the first semiconductor element 21 is mounted on the support substrate 11, the adhesive 41 has a state in which the support substrate 11 maintains a bent shape in the concave portion 93 of the bonding stage 91. Hardens. The connection between the first semiconductor element 31 and the support substrate 11 via the external connection terminal 24 is maintained by the adhesive force and the curing shrinkage force of the adhesive 41.

Next, the suction of the bonding tool 86 is released, and the bonding tool 86 is raised (arrow M). (See FIG. 19 (g))
Thereafter, a plurality of external connection terminals 13 such as spherical electrode terminals mainly composed of solder are disposed on the conductive layer selectively provided on the other main surface (back surface) of the support substrate 11, as shown in FIG. The semiconductor device 200 shown is formed.

  As described above, in the manufacturing method according to the present embodiment, the pressure applied to the support substrate 11 by the bonding tool 86 is provided on the bonding stage 91 that includes the recess 93 and supports the support substrate 11. This is performed through the first semiconductor element 21 flip-chip mounted on the support substrate 11 and the second semiconductor element 31 similarly flip-chip mounted on the support substrate 11. As a result, the support substrate 11 is locally pressurized on the recess 93. The support substrate 11 is locally heated by heat conducted from the bonding tool 86 via the first semiconductor element 21 and the second semiconductor element 31.

  As a result, the support substrate 11 extends and bends in the recess 93 of the bonding stage 91. That is, a concave portion S capable of receiving the second semiconductor element 31 is formed in the support substrate 11 by the local extension and deflection of the support substrate 11 caused by the local pressurization and heating. Since the concave portion S receives the second semiconductor element 31 in the thickness direction, the two semiconductor elements including the second semiconductor element 31 are arranged in a stacked state on the support substrate 11. However, an increase in thickness (height) corresponding to substantially the entire thickness of the second semiconductor element 31 is not brought about.

  That is, in the manufacturing method according to the present embodiment, a semiconductor device that includes a plurality of semiconductor elements, the first semiconductor element 21 and the second semiconductor element 31, and that is required to be thin and small. Can be manufactured by a simple process, and a reduction in manufacturing cost can be achieved.

  Further, the bonding tool 86 is lowered while controlling the height position thereof so that the external connection terminal 24 disposed on the first semiconductor element 21 is brought into contact with the first electrode terminal 12 on the support substrate 11, and thereafter Then, the load of the bonding tool 86 is controlled to apply a load to the external connection terminal 24. By applying such pressure and load, the external connection terminal 24 is reliably connected to the first electrode terminal 12 of the support substrate 11, and a mounting structure with high connection reliability can be obtained.

  Note that after the flip chip mounting of the second semiconductor element 31 to the support substrate 11 is completed, a post cure process is performed to cure the adhesive 43 disposed between the second semiconductor element 31 and the support substrate 11. May be performed.

  Also in this manufacturing method, the suction hole 94 connected to the suction mechanism is disposed at the bottom of the recess 93 disposed in the bonding stage 91, and the recess 93 is evacuated and decompressed, The first semiconductor element 21 can be flip-chip mounted on the support substrate 11.

(Method for Manufacturing Semiconductor Device 300)
A method of manufacturing the semiconductor device 300 according to the third embodiment of the present invention will be described with reference to FIGS. In FIGS. 20 to 22, parts corresponding to those shown in FIGS. 9 to 11 are denoted by the same reference numerals, and description thereof is omitted.

  In manufacturing the semiconductor device 300, the passive component 51 is connected to the second electrode terminal 15 on the support substrate 11 in advance. Such a mounting process is shown in FIG.

That is, a part of the conductive layer is provided as a first electrode terminal 12 on one main surface, and a plurality of second electrode terminals 15 are provided in a region surrounded by the first electrode terminal 12. Individual support substrates 11 are formed. (See FIG. 20 (a))
The conductive member 52 is disposed on the first electrode terminal 15 by depositing, for example, silver (Ag) paste resin by a printing method using a metal mask. (See FIG. 20 (b))
For the deposition of the silver (Ag) paste resin, a method of discharging the silver (Ag) paste resin from a nozzle may be applied. As the conductive member 52, silver (Ag), gold (Au), copper (Cu), nickel (Ni), or carbon is used as the epoxy resin or silicon resin in addition to silver (Ag) paste resin. A conductive adhesive containing conductive fine particles such as black or a solder such as tin (Sn) -silver (Ag) solder or tin (Sn) -silver (Ag) -copper (Cu) solder may be applied. it can.

Next, a desired passive component 51 is mounted and fixed to the second electrode terminal 15 on the support substrate 11 through the conductive member 52 using a so-called chip mounter or the like. (See FIG. 20 (c))
The passive component 51 is a so-called chip component that has a plate shape or a column shape, and is a capacitance element that functions as a bypass capacitor, an inductor element that functions as a noise filter, a resistance element, or the like. Is selected corresponding to. The passive component 51 includes an insulating element body 51a and a plurality of electrode terminals 51b provided on both ends or one main surface of the element body 51a.

  That is, the electrode terminal 51 b of the passive component 51 and the second electrode terminal 15 of the support substrate 11 are electrically and mechanically connected via the conductive member 52.

Thereafter, the conductive member 52 is cured by heating with an oven or the like or irradiation with ultraviolet rays, and the passive element component 51 is mounted on the support substrate 11. (See FIG. 20 (d))
In the present manufacturing method, the semiconductor element 21 is flip-chip mounted on the support substrate 11 on which the passive component 51 is mounted in this manner.

  A process of flip-chip mounting the semiconductor element 21 on the support substrate 11 is shown in FIGS.

  Here, as the flip chip mounting method, a method in which the semiconductor element 21 is thermocompression bonded onto the support substrate 11 with the first adhesive 41 interposed therebetween is used. As the flip chip mounting method, as long as heating and pressurization are performed by a bonding tool that holds the semiconductor element 21 by suction, a method of thermocompression bonding with an adhesive interposed, a bonding method by soldering (brazing), a thermocompression bonding method Alternatively, a connection method using an anisotropic conductive resin or the like can be applied.

  First, the substrate to be processed 11 is sucked and held on the bonding stage 91 through the suction hole 92.

  As a characteristic configuration in the embodiment of the present invention, a concave portion 93 is disposed on the upper surface of the bonding stage 91. The recess 93 has a planar shape, dimensions, and depth that allow the passive component 51 to be received together with a part of the support substrate 11.

  The support substrate 11 is sucked and held on the bonding stage 65 so that the passive component 51 is positioned at the substantially central portion of the recess 93. The bonding stage 65 on which the support substrate 11 is mounted is heated to 50 ° C. to 100 ° C.

  The bottom surface of the concave portion 93 and the inner side surface (side wall surface) following the bottom surface have an arc shape in which the cross-sectional shape extends from the bottom surface to the top surface of the concave portion and has a convex shape toward the inside of the concave portion 93. Has been. By adopting such a circular arc shape, the recess 93 has an inner surface opened upward, so that when the support substrate 11 extends and bends, the support substrate 11 is in contact with the inner surface of the recess 93. It is possible to suppress and reduce the concentration of stress on the specific part of the substrate, and the wiring layer formed on the support substrate 11 is not damaged.

  Further, the bottom of the recess 93 is flat, and the depth is such that when the support substrate 11 extends and bends, the lower surface of the support substrate 11 can contact the bottom surface of the recess 93. Set to Thereby, the amount of bending of the support substrate 11 is limited, and the lower surface of the support substrate 11 is formed with a flat surface.

  In addition, the shape of the inner side surface (side wall surface) of the recessed part 93 is not restricted to the said form, The form shown in the said FIG. 14 can also be applied.

Then, in the region surrounded by the plurality of first electrode terminals 12 on the upper surface of the support substrate 11 sucked and held on the bonding stage 91, the passive component 51 is covered, for example, an epoxy resin. A first adhesive 41 made of a thermosetting material mainly composed of is attached. (See FIG. 21 (e))
The coating of the first adhesive 41 may be performed continuously after the passive component 51 is mounted on the support substrate 11 on the bonding stage 91.

  On the other hand, the semiconductor element 21 is adsorbed via a suction hole 87 to a bonding tool 86 whose other main surface (back surface / non-electronic circuit formation surface) is heated to a predetermined temperature (270 ° C. to 300 ° C.). -Retained.

  A convex external connection terminal 24 is disposed on the external connection terminal pad 22 of the semiconductor element 21.

  The region of the semiconductor element 21 on which the electronic circuit is formed and surrounded by the external connection terminal pads 22 is appropriately selected from materials mainly composed of, for example, polyimide resin, silicon resin, or epoxy resin. The insulating layer 25 having elasticity is provided. The thickness of the insulating layer 25 is set to 1 μm to 15 μm.

  Next, the external connection terminal 24 of the semiconductor element 21 and the first electrode terminal 15 of the support substrate 11 are opposed to perform alignment.

At this time, the semiconductor element 21 is positioned on the passive component 51, and its main surface (electronic circuit forming surface) faces the passive component 51. Then, the bonding tool 86 is lowered while controlling the height position thereof until the external connection terminal 24 in the semiconductor element 21 contacts the first electrode terminal 12 of the support substrate 11 (arrow N). (See FIG. 21 (f)) (first press by position control)
As a result, a predetermined load is applied to the external connection terminal 24 of the semiconductor element 21 by the bonding tool 86, and the external connection terminal 24 of the semiconductor element 21 is connected to the electrode terminal 12 of the support substrate 11. At the same time, the semiconductor element 21 presses the passive component 51 through the insulating layer 25 disposed on the surface thereof.

  Accordingly, the pressing force accompanying the lowering of the bonding tool 86 is applied to the support substrate 11 via the semiconductor element 21, the passive component 51, and the first adhesive 41.

  That is, by this pressing force, at least the passive component 51 mounting portion and its periphery are pressed into the concave portion 93 in the bonding stage 91 and extended.

  At this time, the bonding tool 86 is heated to a predetermined temperature.

  Heat in the bonding tool 86 is conducted to the support substrate 11 through the semiconductor element 21 and the passive component 51. Therefore, the support substrate 11 is locally heated, and local thermal expansion occurs and proceeds, and the support substrate 11 easily extends and bends in the recess 93.

  On the other hand, the adhesive 41 disposed on the support substrate 11 is reduced in viscosity due to heat from the bonding tool 86 conducted by contact between the support substrate 11 and the semiconductor element 21, and its fluidity is reduced. Rise. For this reason, the adhesive 41 is spread between the support substrate 11 and the semiconductor element 21 over the entire area of the surface facing the support substrate 11 of the semiconductor element 21, and the thermosetting proceeds.

It should be noted that the external connection terminal 24 in the semiconductor element 21 is in contact with the first electrode terminal 12 of the support substrate 11, and further, the load sensor (FIG. The load detected by (not shown) is controlled. (See FIG. 22 (g)) (second pressing by load control)
As described above, the insulating layer 25 disposed on the electronic circuit formation surface of the semiconductor element 21 has elasticity. Therefore, when flip chip mounting is performed, even if a load is applied to the electronic circuit formation surface of the semiconductor element 21, damage to the electronic circuit formation surface is prevented. That is, the insulating layer 25 applies stress acting on the electronic circuit formation surface of the semiconductor element 21 from the passive component 51 or the like when the semiconductor element 21 is flip-chip mounted on the support substrate 11 so as to overlap the passive component 51. It functions as a stress relaxation layer that relaxes.

  When the semiconductor element 21 is mounted on the support substrate 11, the adhesive 41 is cured while maintaining the bent shape in the recess 93 of the bonding stage 91 in the support substrate 11. . The connection between the semiconductor element 21 and the support substrate 11 via the external connection terminals 24 is maintained by the adhesive force and the curing shrinkage force of the adhesive 41.

Next, the suction of the bonding tool 86 is released, and the bonding tool 86 is raised (arrow O). (Refer to FIG. 22 (h))
Thereafter, a plurality of external connection terminals 13 such as spherical electrode terminals mainly composed of solder are disposed on the conductive layer selectively provided on the other main surface (back surface) of the support substrate 11, as shown in FIG. The semiconductor device 300 shown is formed.

  As described above, in the manufacturing method according to the present embodiment, the pressure applied to the support substrate 11 by the bonding tool 86 is provided on the bonding stage 91 that includes the recess 93 and supports the support substrate 11. This is performed through the semiconductor element 21 flip-chip mounted on the support substrate 11 and the passive component 51 mounted on the support substrate 11. As a result, the support substrate 11 is locally pressurized on the recess 93. Further, the support substrate 11 is locally heated by heat conducted from the bonding tool 86 through the semiconductor element 21 and the passive component 41.

  As a result, the support substrate 11 expands in the concave portion 93 of the bonding stage 91 and is bent. That is, a concave portion S capable of receiving the passive component 51 is formed in the support substrate 11 by the local extension and deflection of the support substrate 11 caused by the local pressurization and heating. Since the recess S receives the passive component 51 in the thickness direction, even if the passive component 51 and the semiconductor element 21 are arranged in a stacked state on the support substrate 11, the passive component 51 is substantially provided. No increase in thickness (height) corresponding to the total thickness of 51 is brought about.

  That is, in the manufacturing method according to the present embodiment, a semiconductor device that includes a plurality of electronic components such as the semiconductor element 21 and the passive component 51 and that is required to be thin and small can be manufactured by a simple process. It can be manufactured, and a reduction in manufacturing cost can be achieved.

  Further, the bonding tool 86 is lowered while controlling its height position, and the external connection terminal 24 formed on the semiconductor element 21 is brought into contact with the first electrode terminal 12 of the support substrate 11. Since the load is applied to the external connection terminal 24 by controlling the load, the load can be reliably connected to the first electrode terminal 12 of the support substrate 11. Therefore, a mounting structure with high connection reliability can be obtained.

  Also in this manufacturing method, the suction hole 94 connected to the suction mechanism is provided on the bottom surface of the concave portion 93 provided in the bonding stage 91, and the inside of the concave portion 93 is evacuated and depressurized while being supported. The semiconductor element 21 can be flip-chip mounted on the substrate 11.

(Method for Manufacturing Semiconductor Device 400)
A method for manufacturing the semiconductor device 400 according to the fourth embodiment of the present invention will be described with reference to FIGS. 23 to 25, parts corresponding to those shown in FIGS. 9 to 11 are denoted by the same reference numerals, and description thereof is omitted.

  In manufacturing the semiconductor device 400, the second semiconductor element 31 is mounted on the support substrate 11 in a so-called face-up state in advance, and the second semiconductor element 31 is sealed with resin. Such a mounting / sealing process is shown in FIG.

That is, a part of the conductive layer is exposed as a first electrode terminal 12 on one main surface, and a plurality of fourth electrode terminals 16 are provided in a region surrounded by the first electrode terminal 12. The support substrate 11 that is individually arranged and formed is formed. (See FIG. 23 (a))
Next, the second semiconductor element 31 is placed on the support substrate 11 in the region surrounded by the fourth electrode terminal 16 with the main surface (electronic circuit formation surface) facing up via the die bond material 61. Mount and stick. (See FIG. 23 (b))
External connection terminal pads 32 are disposed on the main surface of the second semiconductor element 31 so as to surround the electronic circuit forming portion. At this time, a so-called die bonder is used for fixing (die bonding) of the second semiconductor element 31, and a material mainly composed of polyimide resin or epoxy resin is applied as the die bond material 61.

Next, between the external connection terminal pad 32 formed on the circuit formation surface of the second semiconductor element 31 and the fourth electrode terminal 16 on the support substrate 11, gold (Au), copper (Cu And the like by a bonding wire 34 mainly composed of a metal such as). (See FIG. 23 (c))
In addition, on the surface of the external connection terminal pad 32 of the second semiconductor element 31, for example, a nickel (Ni) / gold (Au) two-layer plating layer is sequentially formed from the lower layer by an electroless plating method or the like. It may be arranged.

Thereafter, a resin molding method such as a transfer molding method or a compression molding method, or a potting method is applied, and the second semiconductor element 31, the bonding wire 34, and the fourth electrode terminal are used by using the sealing resin 62. 16 is resin-sealed. (See FIG. 23 (d))
As the sealing resin 62, for example, a material mainly composed of an epoxy resin can be applied.

  In the present manufacturing method, the second semiconductor element 31 is mounted in a so-called face-up state as described above, and the second semiconductor element 31 is further resin-sealed together with the bonding wires 62 and the like. On top, the first semiconductor element 21 is flip-chip mounted.

  A process of flip-chip mounting the first semiconductor element 21 on the support substrate 11 is shown in FIGS.

  Here, as the flip chip mounting method, a method in which the first semiconductor element 21 is thermocompression bonded onto the support substrate 11 with the first adhesive 41 interposed therebetween is used. As the flip chip mounting method, as long as heating and pressurization are performed by a bonding tool that holds the first semiconductor element 21 by suction, a method of thermocompression bonding with an adhesive interposed, a bonding method by soldering (brazing), A thermocompression bonding method or a connection method using an anisotropic conductive resin can be applied.

  First, the substrate to be processed 11 is sucked and held on the bonding stage 91 through the suction hole 92.

  As a characteristic configuration in the embodiment of the present invention, a concave portion 93 is disposed on the upper surface of the bonding stage 91. The concave portion 93 has a planar shape, size, and depth that allow the second semiconductor element 31 sealed with resin as described above to be received together with a part of the support substrate 11.

  The support substrate 11 is adsorbed and held on the bonding stage 91 so that the resin-sealed second semiconductor element 31 is positioned at a substantially central portion of the recess 93. The bonding stage 91 on which the support substrate 11 is mounted is heated to 50 ° C. to 100 ° C.

  The bottom surface of the concave portion 93 and the inner side surface (side wall surface) following the concave portion 93 have an arc-shaped cross section in which the cross-sectional shape extends from the bottom surface to the top surface of the concave portion and has a convex shape toward the inside of the concave portion 93. Have By exhibiting such an arc-shaped cross section, the concave portion 93 has an inner side surface opened upward. Therefore, when the support substrate 11 extends and bends, the support substrate is in contact with the inner side surface of the concave portion 93. It is possible to suppress and reduce the concentration of stress on the 11 specific parts, and the wiring layer formed on the support substrate 11 is not damaged.

  Further, the bottom of the recess 93 is flat, and the depth is such that when the support substrate 11 extends and bends, the lower surface of the support substrate 11 can contact the bottom surface of the recess 93. Set to Thereby, the amount of bending of the support substrate 11 is limited, and the lower surface of the support substrate 11 is formed with a flat surface.

  In addition, the shape of the inner side surface (side wall surface) of the recessed part 93 is not restricted to the said form, The form shown in the said FIG. 14 can also be applied.

Then, on the upper surface of the support substrate 11 adsorbed and held on the bonding stage 91, in the region surrounded by the plurality of first electrode terminals 12, the second semiconductor element 31 sealed with resin is used. For example, the first adhesive 41 made of a thermosetting material mainly composed of an epoxy resin is coated. (See FIG. 24 (e))
The coating of the first adhesive 41 may be performed continuously after the resin sealing portion including the second semiconductor element 31 is formed on the bonding stage 91.

  On the other hand, in the first semiconductor element 21, the other main surface (back surface / electronic circuit non-formed surface) is heated to a predetermined temperature (270 ° C. to 300 ° C.) via a suction hole 87. Adsorbed and retained.

  A convex external connection terminal 24 is disposed on the first external connection terminal pad 22 of the first semiconductor element 21.

  The region of the electronic circuit formation surface of the first semiconductor element 21 and surrounded by the first external connection terminal pad 22 is mainly made of, for example, polyimide resin, silicon resin, or epoxy resin. An insulating layer 25 having elasticity, which is appropriately selected from the materials described above, is provided. The thickness of the insulating layer 25 is set to 1 μm to 15 μm.

  Next, the external connection terminal 24 of the first semiconductor element 21 and the first electrode terminal 12 of the support substrate 11 are opposed to perform alignment.

At this time, the first semiconductor element 21 is positioned on the sealing resin 62 that covers the second semiconductor element 31, and its main surface (electronic circuit forming surface) faces the sealing resin 62. Then, the bonding tool 86 is lowered while controlling the height position thereof until the external connection terminal 24 in the first semiconductor element 21 comes into contact with the first electrode terminal 12 of the support substrate 11 (arrow P). ). (See FIG. 24F) (first pressing by position control)
As a result, a predetermined load is applied to the external connection terminal 24 of the first semiconductor element 21 by the bonding tool 86, and the external connection terminal 24 of the first semiconductor element 21 is connected to the electrode terminal 12 of the support substrate 11. Is done. At the same time, the first semiconductor element 21 presses the sealing resin 62 covering the second semiconductor element 31 through the insulating layer 25 disposed on the surface thereof.

  Therefore, the pressing force associated with the lowering of the bonding tool 75 is transmitted through the first semiconductor element 21, the sealing resin 62 covering the second semiconductor element 31, the second semiconductor element 31, and the first adhesive 41. , Applied to the support substrate 11.

  That is, due to the pressing force, the support substrate 11 is at least directly under the second semiconductor element 31, and immediately under and around the sealing resin 62 covering the semiconductor element 31, into the recess 93 in the bonding stage 91. Pressed and stretched.

  At this time, the bonding tool 86 that holds the first semiconductor element 21 by suction is heated to a predetermined temperature.

  Heat in the bonding tool 86 is conducted to the support substrate 11 through the first semiconductor element 21, the second semiconductor element 31, and the sealing resin 62 that covers the second semiconductor element 31. Accordingly, the support substrate 11 is locally heated, and local thermal expansion occurs and proceeds, and the support substrate 11 easily extends and bends into the recess 93 in the bonding stage 91.

  Furthermore, the first adhesive 41 disposed on the support substrate 11 is supplied from the bonding tool 86 conducted by contact between the support substrate 11 and the resin sealing portion including the second semiconductor element 31. Heat reduces the viscosity and improves its fluidity. Therefore, the first adhesive 41 flows between the support substrate 11 and the first semiconductor element 21 and is spread and flows over the entire area of the first semiconductor element 21 facing the support substrate 11. And thermosetting proceeds.

The external connection terminal 24 in the first semiconductor element 21 comes into contact with the first electrode terminal 12 of the support substrate 11, and the flip chip mounting of the first semiconductor element 21 to the support substrate 11 is completed. Until then, the load detected by a load sensor (not shown) is controlled. (See FIG. 25 (g)) (second pressing by load control)
As described above, the insulating layer 25 disposed on the electronic circuit formation surface of the first semiconductor element 21 has elasticity. Therefore, when flip chip mounting is performed, even if a load is applied to the electronic circuit formation surface of the first semiconductor element 21, it is possible to prevent damage to the electronic circuit formation surface. That is, the insulating layer 25 is formed when the first semiconductor element 21 is flip-chip mounted on the support substrate 11 so as to overlap the resin sealing portion including the second semiconductor element 31. It functions as a stress relieving layer that relieves stress acting on the electronic circuit formation surface of the first semiconductor element 21 from a resin-encapsulated portion containing bismuth.

  When the first semiconductor element 21 is mounted on the support substrate 11, in the support substrate 11, the concave shape 93 of the bonding stage 91 maintains a bent shape, and the first semiconductor element 21 is mounted. The adhesive 41 is cured. The connection between the first semiconductor element 21 and the support substrate 11 via the external connection terminal 24 is maintained by the adhesive force and the curing shrinkage force of the first adhesive 41.

Next, the suction of the bonding tool 86 is released, and the bonding tool 75 is raised (arrow Q). (See FIG. 25 (h))
Thereafter, a plurality of external connection terminals 13 such as spherical electrode terminals mainly composed of solder are disposed on the conductive layer selectively provided on the other main surface (back surface) of the support substrate 11, as shown in FIG. The semiconductor device 400 shown is formed.

  As described above, in the manufacturing method according to the present embodiment, the pressure applied to the support substrate 11 by the bonding tool 86 is provided on the bonding stage 91 that includes the recess 93 and supports the support substrate 11. The first semiconductor element 21 flip-chip mounted on the support substrate 11, the second semiconductor element 31 mounted face-up on the support substrate 11, and the sealing resin that covers the second semiconductor element 31 62. As a result, the support substrate 11 is locally pressurized on the recess 93.

  Further, the support substrate 11 is locally generated by heat conducted from the bonding tool 86 through the first semiconductor element 21, the second semiconductor element 31, and the sealing resin 62 covering the second semiconductor element 31. Heated. As a result, the support substrate 11 locally expands in the concave portion 93 of the bonding stage 91 to bend.

  That is, the support substrate 11 can receive the resin sealing portion including the second semiconductor element 31 by the local extension and deflection of the support substrate 11 caused by the local pressurization and heating. A recess S is formed. Since the recess S receives the second semiconductor element 31 and the sealing resin 62 covering the second semiconductor element 31 in the thickness direction, the second semiconductor element 31 and the second semiconductor element 31 are formed on the support substrate 11. Even when the sealing resin 62 covering the second semiconductor element 31 and the first semiconductor element 21 are arranged in a stacked state, the second semiconductor element 31 and the second semiconductor element 31 are substantially covered. The thickness (height) corresponding to the total thickness of the sealing resin 62 is not increased.

  That is, in the manufacturing method according to the present embodiment, a semiconductor device that includes a plurality of semiconductor elements, that is, the first semiconductor element 21 and the second semiconductor element 31, and that is required to be thin and downsized. Can be manufactured by a simple process, and a reduction in manufacturing cost can be achieved.

  Further, the bonding tool 86 is lowered while controlling the height position thereof, and the external connection terminal 24 formed on the first semiconductor element 21 is brought into contact with the first electrode terminal 12 of the support substrate 11, and thereafter Since the load is applied to the external connection terminal 24 by controlling the load of the bonding tool 86, the load can be reliably connected to the first electrode terminal 12 of the support substrate 11. Therefore, a mounting structure with high connection reliability can be obtained.

  Also in this manufacturing method, the suction hole 94 connected to the suction mechanism is provided on the bottom surface of the concave portion 93 provided in the bonding stage 91, and the inside of the concave portion 93 is evacuated and depressurized while being supported. The first semiconductor element 21 can be flip-chip mounted on the substrate 11.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims. Variations and changes are possible.

Regarding the above description, the following items are further disclosed.
(Appendix 1)
A support substrate;
A first semiconductor element mounted on one main surface of the support substrate;
An electronic component disposed between the support substrate and the first semiconductor element;
Comprising
The support substrate has a recess formed by being deformed in a direction away from the first semiconductor element,
A semiconductor device, wherein the electronic component is mounted such that at least a part of its thickness is accommodated in the recess.
(Appendix 2)
The support substrate is bent to the opposite side to the first semiconductor element;
The semiconductor device according to appendix 1, wherein the recess is formed in the support substrate by bending.
(Appendix 3)
The semiconductor device according to appendix 1 or 2, wherein a portion of the support substrate where the concave portion is formed has the same thickness as other portions of the support substrate.
(Appendix 4)
The semiconductor device according to any one of appendices 1 to 3, wherein the concave portion is smaller than a surface of the first semiconductor element facing the support substrate.
(Appendix 5)
The semiconductor device according to any one of appendices 1 to 4, wherein the electronic component is a second semiconductor element that is separate from the first semiconductor element.
(Appendix 6)
The first semiconductor element is flip-chip mounted on the support substrate via an external connection terminal,
The semiconductor device according to any one of appendices 1 to 5, wherein a thickness of the electronic component is larger than a height of the external connection terminal.
(Appendix 7)
8. The semiconductor device according to appendix 6, wherein an insulating layer having elasticity is provided in a gap between the first semiconductor element and the electronic component.
(Appendix 8)
The semiconductor device according to any one of appendices 1 to 7, wherein the electronic component is mounted on the support substrate, wire-bonded to the support substrate, and resin-sealed.
(Appendix 9)
The adhesive according to any one of appendices 1 to 9, wherein an adhesive is provided in the gap between the support substrate and the first semiconductor element, and the support substrate and the first semiconductor element are fixed to each other. Semiconductor device.
(Appendix 10)
11. The semiconductor device according to any one of appendices 1 to 10, wherein the support substrate expands by heating and has flexibility.
(Appendix 11)
An electronic component is pressed against one main surface of the support substrate via the first semiconductor element, and the support substrate is deformed in a direction away from the first semiconductor element, and the deformation causes the support substrate to be deformed. A method for manufacturing a semiconductor device, comprising the step of accommodating at least a part of the electronic component in a recess formed in the substrate.
(Appendix 12)
The method of manufacturing a semiconductor device according to appendix 11, wherein the support substrate is heated when the electronic component is pressed against the support substrate.
(Appendix 13)
13. The method for manufacturing a semiconductor device according to appendix 11 or 12, further comprising a step of mounting the first semiconductor element on one main surface of the support substrate.
(Appendix 14)
14. The method of manufacturing a semiconductor device according to any one of appendices 11 to 13, wherein the electronic component is a second semiconductor element separate from the first semiconductor element.
(Appendix 15)
The support substrate is mounted on a stage having a recess formed in the upper part,
The method of manufacturing a semiconductor device according to appendix 11, wherein the support substrate is bent into the recess when locally heated.
(Appendix 16)
16. The method of manufacturing a semiconductor device according to appendix 15, wherein a cross section of an end portion defining an outer peripheral portion of the recess formed on the stage has an upwardly expanding shape.
(Appendix 17)
The recess formed in the stage has a depth that allows the lower surface of the bent portion of the support substrate to contact the bottom surface of the recess when the support substrate is bent. A method for manufacturing a semiconductor device according to Supplementary Note 15 or 16.
(Appendix 18)
The first semiconductor element is heated by a jig that holds the first semiconductor element by suction,
Heat of the first semiconductor element is conducted to the support substrate through an external connection terminal provided on the first semiconductor element and connecting the support substrate and the first semiconductor element and the electronic component. 18. A method for manufacturing a semiconductor device according to any one of appendices 11 to 17, wherein:
(Appendix 19)
The method for manufacturing a semiconductor device according to any one of appendices 11 to 18, wherein the support substrate is locally heated to a temperature equal to or higher than a glass transition temperature of the support substrate.
(Appendix 20)
Disposing a second semiconductor element between the support substrate and the first semiconductor element;
A step of locally bending the support substrate by pressing the second semiconductor element against the support substrate via the first semiconductor element while the support substrate is heated;
Fixing the first semiconductor element to the support substrate in a state where the support substrate is bent; and
A method for manufacturing a semiconductor device, comprising:

100, 200, 300, 400 Semiconductor device 11 Support substrate 21, 31 Semiconductor element 14, 23 External connection terminals 24, 25, 33 Adhesive
32 Insulating layer 41 Passive element component 51 Bonding wire 52 Sealing resin 60, 65 Bonding stage 62, 75 Bonding tool S Recess

Claims (10)

  An electronic component is pressed against one main surface of the support substrate via the first semiconductor element, and the support substrate is deformed in a direction away from the first semiconductor element, and the deformation causes the support substrate to be deformed. A method for manufacturing a semiconductor device, comprising the step of accommodating at least a part of the electronic component in a recess formed in the substrate.   The method of manufacturing a semiconductor device according to claim 1, wherein the support substrate is heated when the electronic component is pressed against the support substrate.   3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of mounting the first semiconductor element on one main surface of the support substrate.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the electronic component is a second semiconductor element separate from the first semiconductor element. 5. The support substrate is mounted on a stage having a recess formed in the upper part,
The method of manufacturing a semiconductor device according to claim 1, wherein the support substrate is bent into the recess when locally heated.   6. The method of manufacturing a semiconductor device according to claim 5, wherein a cross section of an end portion defining an outer peripheral portion of the recess formed on the stage has an upwardly expanding shape.   The recess formed in the stage has a depth that allows the lower surface of the bent portion of the support substrate to contact the bottom surface of the recess when the support substrate is bent. A method of manufacturing a semiconductor device according to claim 5 or 6. The first semiconductor element is heated by a jig that holds the first semiconductor element by suction,
Heat of the first semiconductor element is conducted to the support substrate through an external connection terminal provided on the first semiconductor element and connecting the support substrate and the first semiconductor element and the electronic component. A method for manufacturing a semiconductor device according to claim 1, wherein:   9. The method for manufacturing a semiconductor device according to claim 1, wherein the support substrate is locally heated to a temperature equal to or higher than a glass transition temperature of the support substrate. Disposing a second semiconductor element between the support substrate and the first semiconductor element;
A step of locally bending the support substrate by pressing the second semiconductor element against the support substrate via the first semiconductor element while the support substrate is heated;
Fixing the first semiconductor element to the support substrate in a state where the support substrate is bent; and
A method for manufacturing a semiconductor device, comprising:

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