JPH0229541U - - Google Patents

Info

Publication number
JPH0229541U
JPH0229541U JP10752788U JP10752788U JPH0229541U JP H0229541 U JPH0229541 U JP H0229541U JP 10752788 U JP10752788 U JP 10752788U JP 10752788 U JP10752788 U JP 10752788U JP H0229541 U JPH0229541 U JP H0229541U
Authority
JP
Japan
Prior art keywords
chip
flip
flexible substrate
solder bumps
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10752788U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10752788U priority Critical patent/JPH0229541U/ja
Publication of JPH0229541U publication Critical patent/JPH0229541U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本考案のフエイスダウンしたＩＣチ
ツプを示す斜視図、第２図は、同ＩＣチツプの回
路形成面側を示す平面図、第３図は、本考案のフ
リツプチツプ実装状態を示す側面図、第４図は、
同外力による変形状態を示す側面図、第５図は、
従来のＩＣチツプの実装状態を示す側面図、第６
図は、同外力による変形状態を示す側面図である
。 １…Ｉチツプ、１１…回路形成面、１２，１３
，１４，１５…破砕溝、２，２，２，２…集積回
路、２Ａ，２Ｂ，２Ｃ，２Ｄ…チツプブロツク、
２１…配線、２２…半田バンプ、３…フレキシブ
ル基板、３１…ボンデングパツド。 Fig. 1 is a perspective view showing a face-down IC chip of the present invention, Fig. 2 is a plan view showing the circuit forming side of the IC chip, and Fig. 3 is a side view showing the flip-chip mounting state of the present invention. Figure 4 is
Fig. 5 is a side view showing the state of deformation caused by the same external force.
Side view showing the mounting state of a conventional IC chip, No. 6
The figure is a side view showing a deformed state due to the same external force. 1...I chip, 11...Circuit formation surface, 12, 13
, 14, 15... Crushing groove, 2, 2, 2, 2... Integrated circuit, 2A, 2B, 2C, 2D... Chip block,
21... Wiring, 22... Solder bump, 3... Flexible board, 31... Bonding pad.

Claims (1)

【実用新案登録請求の範囲】 集積回路を設けたＩＣチツプの回路形成面に設
けた半田バンプをフエイスダウンしてフレキシブ
ル基板のボンデングパツド上に搭載し、 前記半田バンプにより前記ＩＣチツプを前記フ
レキシブル基板に接続させるフリツプチツプ実装
において、 前記ＩＣチツプは、少なくとも一個以上の半田
バンプを設けた集積回路を複数個配置し、前記集
積回路相互を電気的に独立させるとともに、前記
集積回路を有する各チツプブロツクを破砕溝によ
り区分したことを特徴とするフリツプチツプ実装
におけるＩＣチツプの構造。[Claims for Utility Model Registration] Solder bumps provided on the circuit formation surface of an IC chip provided with an integrated circuit are mounted face down on a bonding pad of a flexible substrate, and the IC chip is attached to the flexible substrate by the solder bumps. In flip-chip mounting for connection, the IC chip has a plurality of integrated circuits provided with at least one solder bump, the integrated circuits are electrically independent from each other, and each chip block having the integrated circuit is placed in a crushing groove. The structure of an IC chip in flip-chip mounting, characterized by being classified by:
JP10752788U 1988-08-15 1988-08-15 Pending JPH0229541U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10752788U JPH0229541U (en) 1988-08-15 1988-08-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10752788U JPH0229541U (en) 1988-08-15 1988-08-15

Publications (1)

Publication Number Publication Date
JPH0229541U true JPH0229541U (en) 1990-02-26

Family

ID=31342022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10752788U Pending JPH0229541U (en) 1988-08-15 1988-08-15

Country Status (1)

Country Link
JP (1) JPH0229541U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010122728A1 (en) * 2009-04-22 2010-10-28 シャープ株式会社 Ic chip, display panel and display module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010122728A1 (en) * 2009-04-22 2010-10-28 シャープ株式会社 Ic chip, display panel and display module

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