JPS6035569U - Chip carrier bump connection structure - Google Patents
Chip carrier bump connection structureInfo
- Publication number
- JPS6035569U JPS6035569U JP12778683U JP12778683U JPS6035569U JP S6035569 U JPS6035569 U JP S6035569U JP 12778683 U JP12778683 U JP 12778683U JP 12778683 U JP12778683 U JP 12778683U JP S6035569 U JPS6035569 U JP S6035569U
- Authority
- JP
- Japan
- Prior art keywords
- chip carrier
- connection structure
- bump connection
- carrier bump
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はバンプを有するチップキャリアの従来の構造を
示す断面図と平面図、第２図はチップキャリアをプリン
ト基板に搭載した模様を示す側面図、第３図は本考案に
基づいたチップキャリアのバンプ接続用のパッドの一実
施例の構造を示す断面図および平面図、第４図は第３図
に示したチップキャリアをプリント基板に搭載した時の
両者の接続部の模様を示す断面図、第５図は本考案に基
づいた別の実施例を示す断面図である
図において、１はチップ基板、３はＩＣチップ、６はポ
ンディングパッド、７はビア、８，１８はバンプ接続用
パッド、９はバンプ、１０はプリント基板、１１はプリ
ント基板印刷回路のパッド、１２は半田層をそれぞれ示
す。Figure 1 is a cross-sectional view and a plan view showing the conventional structure of a chip carrier with bumps, Figure 2 is a side view showing the chip carrier mounted on a printed circuit board, and Figure 3 is a chip carrier based on the present invention. 4 is a sectional view and a plan view showing the structure of an embodiment of the bump connection pad, and FIG. 4 is a sectional view showing the pattern of the connection between the two when the chip carrier shown in FIG. 3 is mounted on a printed circuit board. , FIG. 5 is a sectional view showing another embodiment based on the present invention. In the figure, 1 is a chip substrate, 3 is an IC chip, 6 is a bonding pad, 7 is a via, and 8 and 18 are for bump connection. 9 is a bump, 10 is a printed circuit board, 11 is a pad of a printed circuit board, and 12 is a solder layer.
Claims (1)
外面に形成されたパッドとバンプとより構成された外部
回路への接続手段において、前記パッドが凸凹状に形成
されたことを特徴とするチップキャリアのバンプ接続構
造。A means for connecting to an external circuit comprising pads and bumps formed on the outer surface of a chip carrier substrate on which a semiconductor integrated circuit device or the like is mounted, wherein the pads are formed in an uneven shape. Bump connection structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12778683U JPS6035569U (en) | 1983-08-17 | 1983-08-17 | Chip carrier bump connection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12778683U JPS6035569U (en) | 1983-08-17 | 1983-08-17 | Chip carrier bump connection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6035569U true JPS6035569U (en) | 1985-03-11 |
Family
ID=30290113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12778683U Pending JPS6035569U (en) | 1983-08-17 | 1983-08-17 | Chip carrier bump connection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6035569U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0327908A (en) * | 1989-06-26 | 1991-02-06 | Babu Hitachi Kogyo Kk | Control device for core drill |
-
1983
- 1983-08-17 JP JP12778683U patent/JPS6035569U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0327908A (en) * | 1989-06-26 | 1991-02-06 | Babu Hitachi Kogyo Kk | Control device for core drill |
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