JPH0189752U - - Google Patents
Info
- Publication number
- JPH0189752U JPH0189752U JP15957688U JP15957688U JPH0189752U JP H0189752 U JPH0189752 U JP H0189752U JP 15957688 U JP15957688 U JP 15957688U JP 15957688 U JP15957688 U JP 15957688U JP H0189752 U JPH0189752 U JP H0189752U
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- circuit board
- brazed
- conductor pin
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000919 ceramic Substances 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は従来のパツケージを回路基板に装着し
た構造断面図例、第2図はそのパツケージの平面
図、第3図は本考案にかかる半導体パツケージの
断面図、第4図は本考案の一実施例による半導体
実装回路装置の断面図、第5図は第4図における
要部拡大図、第6図は本考案の他の実施例による
半導体実装回路装置の断面図を示す。
図中、1はパツケージ、2は回路基板、3,6
は半田、4は導体ピン、5は銀鑞、12は導体パ
ツド、21は接続用の電極を示している。
Figure 1 is an example of a structural cross-sectional view of a conventional package mounted on a circuit board, Figure 2 is a plan view of the package, Figure 3 is a cross-sectional view of a semiconductor package according to the present invention, and Figure 4 is an example of a semiconductor package according to the present invention. FIG. 5 is an enlarged view of the main part of FIG. 4, and FIG. 6 is a cross-sectional view of a semiconductor packaged circuit device according to another embodiment of the present invention. In the figure, 1 is a package, 2 is a circuit board, 3, 6
1 is solder, 4 is a conductor pin, 5 is silver solder, 12 is a conductor pad, and 21 is a connection electrode.
Claims (1)
取付けられる半導体パツケージにおいて、回路基
板に対向する面上にメタライズ層として形成され
る複数個の導体パツドには、夫々バネ性を有する
導体ピンの一端が高融点金属で鑞づけされ、該導
体ピンの他端が前記回路基板上の被接続導体に当
接して鑞づけされていることを特徴とする半導体
実装回路装置。 In a semiconductor package in which an IC chip is mounted inside the center of a laminated ceramic substrate, a plurality of conductor pads formed as a metallized layer on the surface facing the circuit board each have one end of a conductor pin having a spring property with a high melting point. 1. A semiconductor mounted circuit device characterized in that the conductor pin is brazed with metal, and the other end of the conductor pin is brazed in contact with a conductor to be connected on the circuit board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988159576U JPH0536275Y2 (en) | 1988-12-08 | 1988-12-08 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988159576U JPH0536275Y2 (en) | 1988-12-08 | 1988-12-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0189752U true JPH0189752U (en) | 1989-06-13 |
JPH0536275Y2 JPH0536275Y2 (en) | 1993-09-14 |
Family
ID=31440912
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1988159576U Expired - Lifetime JPH0536275Y2 (en) | 1988-12-08 | 1988-12-08 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0536275Y2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016048728A (en) * | 2014-08-27 | 2016-04-07 | 株式会社村田製作所 | Conductive post and manufacturing method of multilayer substrate using conductive post |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5559746A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Semiconductor device and its mounting circuit device |
JPS5743452A (en) * | 1980-08-28 | 1982-03-11 | Mitsubishi Electric Corp | Mounting structure for integrated circuit substrate |
JPS5791586A (en) * | 1980-11-29 | 1982-06-07 | Tokyo Shibaura Electric Co | Hybrid integrated circuit device |
JPS57121256A (en) * | 1981-01-21 | 1982-07-28 | Hitachi Ltd | Ceramic multilayer wiring structure |
JPS57181144A (en) * | 1981-05-01 | 1982-11-08 | Toshiba Corp | Semiconductor device |
-
1988
- 1988-12-08 JP JP1988159576U patent/JPH0536275Y2/ja not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5559746A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Semiconductor device and its mounting circuit device |
JPS5743452A (en) * | 1980-08-28 | 1982-03-11 | Mitsubishi Electric Corp | Mounting structure for integrated circuit substrate |
JPS5791586A (en) * | 1980-11-29 | 1982-06-07 | Tokyo Shibaura Electric Co | Hybrid integrated circuit device |
JPS57121256A (en) * | 1981-01-21 | 1982-07-28 | Hitachi Ltd | Ceramic multilayer wiring structure |
JPS57181144A (en) * | 1981-05-01 | 1982-11-08 | Toshiba Corp | Semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016048728A (en) * | 2014-08-27 | 2016-04-07 | 株式会社村田製作所 | Conductive post and manufacturing method of multilayer substrate using conductive post |
Also Published As
Publication number | Publication date |
---|---|
JPH0536275Y2 (en) | 1993-09-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH0189752U (en) | ||
JPH0284368U (en) | ||
JPS6237939U (en) | ||
JPS6338328U (en) | ||
JPS6389280U (en) | ||
JPS6192064U (en) | ||
JPS6130248U (en) | multilayer ceramic substrate | |
JPS6035569U (en) | Chip carrier bump connection structure | |
JPS61134039U (en) | ||
JPS59109150U (en) | IC chip package | |
JPS6153934U (en) | ||
JPS6429872U (en) | ||
JPS6413144U (en) | ||
JPH0184451U (en) | ||
JPS63140625U (en) | ||
JPS61153374U (en) | ||
JPH0288240U (en) | ||
JPS6142847U (en) | Packages for semiconductor devices | |
JPH0381643U (en) | ||
JPS622248U (en) | ||
JPS6247171U (en) | ||
JPS63197357U (en) | ||
JPH0351870U (en) | ||
JPH0265349U (en) | ||
JPS62197801U (en) |