JPS6142847U - Packages for semiconductor devices - Google Patents
Packages for semiconductor devicesInfo
- Publication number
- JPS6142847U JPS6142847U JP11032085U JP11032085U JPS6142847U JP S6142847 U JPS6142847 U JP S6142847U JP 11032085 U JP11032085 U JP 11032085U JP 11032085 U JP11032085 U JP 11032085U JP S6142847 U JPS6142847 U JP S6142847U
- Authority
- JP
- Japan
- Prior art keywords
- pad
- package
- main surface
- packages
- semiconductor devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図ａ及びｂは従来の倒立型リードレス・パッケージ
の説明に供する断面図及び要部拡大斜視図、第２図ａ及
びｂは本発明一実施例の半導体装置用パッケージを示す
断面図及び要部拡大斜視図である。
各図において、符号は以下のものを示している。
１・・・セラミック基体、２・・・半導体素子、３・・
・細線、４・・・ボンデイング・パッド、５・・・導電
層、６・・・キャップ、７・・・ソルダ・パッド、８・
・・切り欠き溝、９・・・測定用パッド。1A and 1B are a cross-sectional view and an enlarged perspective view of the main parts of a conventional inverted leadless package, and FIGS. 2A and 2B are cross-sectional views and an enlarged perspective view of a semiconductor device package according to an embodiment of the present invention. FIG. 3 is an enlarged perspective view of main parts. In each figure, the symbols indicate the following. 1... Ceramic base, 2... Semiconductor element, 3...
- Thin wire, 4... Bonding pad, 5... Conductive layer, 6... Cap, 7... Solder pad, 8...
...Notch groove, 9...Measuring pad.
Claims (1)
き溝を有する倒立型リードレス・パッケージにおいて、 キャップを接着する側の一主面にソルダ・パッドを、 他の主面に前記ソルダ・パッドより大きい面積を有ずる
測定用パッドを具備し、 該測定用パッドと前記ソルダ・パッドとは、ボンデイン
グパツドより導出され前記切り欠き溝全表面に延在する
導電層により電気的に接続されてな乏ことを特徴とする
半導体装置用パッケージ。[Claims for Utility Model Registration] In an inverted leadless package that has a notch groove formed on the side surface from one main surface to the other, a solder pad is attached to one main surface on the side to which a cap is attached. , a measuring pad having a larger area than the solder pad is provided on the other main surface, and the measuring pad and the solder pad are led out from the bonding pad and extend over the entire surface of the notched groove. A package for a semiconductor device, characterized in that the package is electrically connected by a conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11032085U JPS6142847U (en) | 1985-07-18 | 1985-07-18 | Packages for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11032085U JPS6142847U (en) | 1985-07-18 | 1985-07-18 | Packages for semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6142847U true JPS6142847U (en) | 1986-03-19 |
Family
ID=30669443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11032085U Pending JPS6142847U (en) | 1985-07-18 | 1985-07-18 | Packages for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6142847U (en) |
-
1985
- 1985-07-18 JP JP11032085U patent/JPS6142847U/en active Pending
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