JPS6094836U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6094836U
JPS6094836U JP1983187219U JP18721983U JPS6094836U JP S6094836 U JPS6094836 U JP S6094836U JP 1983187219 U JP1983187219 U JP 1983187219U JP 18721983 U JP18721983 U JP 18721983U JP S6094836 U JPS6094836 U JP S6094836U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor device
lead
protrusion
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1983187219U
Other languages
Japanese (ja)
Other versions
JPH0142345Y2 (en
Inventor
隆也 長畑
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ローム株式会社 filed Critical ローム株式会社
Priority to JP1983187219U priority Critical patent/JPS6094836U/en
Publication of JPS6094836U publication Critical patent/JPS6094836U/en
Application granted granted Critical
Publication of JPH0142345Y2 publication Critical patent/JPH0142345Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来例の断面図、第２図はこの考案の実施例を
示す断面図である。 １・・・・・・基板、２・・・・・・半導体チップ、３
・・・・・・リード、４・・・・・・ワイヤ、５・・・
・・・突出部。FIG. 1 is a sectional view of a conventional example, and FIG. 2 is a sectional view showing an embodiment of this invention. 1...Substrate, 2...Semiconductor chip, 3
...Lead, 4...Wire, 5...
...protrusion.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板上に設置された半導体チップとリープとをワイヤで
接続してなる半導体装置において、前記リードをグレー
ズからなる突出部の表面にまたがって形成し、そのリー
ドの前記突出部上の部分で前記ワイヤと接続してなる半
導体装置。In a semiconductor device in which a semiconductor chip placed on a substrate and a lead are connected by wires, the leads are formed across the surface of a protrusion made of glaze, and a portion of the lead above the protrusion is connected to the wire. A semiconductor device connected to
JP1983187219U 1983-12-02 1983-12-02 semiconductor equipment Granted JPS6094836U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983187219U JPS6094836U (en) 1983-12-02 1983-12-02 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983187219U JPS6094836U (en) 1983-12-02 1983-12-02 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS6094836U true JPS6094836U (en) 1985-06-28
JPH0142345Y2 JPH0142345Y2 (en) 1989-12-12

Family

ID=30404181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983187219U Granted JPS6094836U (en) 1983-12-02 1983-12-02 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6094836U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62165959A (en) * 1986-01-17 1987-07-22 Hitachi Ltd Semiconductor device and its lead frame

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62165959A (en) * 1986-01-17 1987-07-22 Hitachi Ltd Semiconductor device and its lead frame

Also Published As

Publication number Publication date
JPH0142345Y2 (en) 1989-12-12

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