JPS6094835U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6094835U JPS6094835U JP18721883U JP18721883U JPS6094835U JP S6094835 U JPS6094835 U JP S6094835U JP 18721883 U JP18721883 U JP 18721883U JP 18721883 U JP18721883 U JP 18721883U JP S6094835 U JPS6094835 U JP S6094835U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor equipment
- substrate
- semiconductor device
- semiconductor chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Die Bonding (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例の断面図、第２図はこの考案の実施例を
示す断面図である。
１・・・・・・基板、２・・・・・・半導体チップ、３
・・川・リード、４・・・・・・ワイヤ、５・・・・・
べぼみ部。FIG. 1 is a sectional view of a conventional example, and FIG. 2 is a sectional view showing an embodiment of this invention. 1...Substrate, 2...Semiconductor chip, 3
・・River・Reed, 4・・・・Wire, 5・・・・
Bebomi part.
Claims (1)
接続してなる半導体装置において、前記半導体チップを
前記基板の表面に設けたくぼみ部に設置してなる半導体
装置。A semiconductor device comprising a semiconductor chip placed on a substrate and a lead connected by a wire, the semiconductor device comprising the semiconductor chip placed in a recess provided on the surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18721883U JPS6094835U (en) | 1983-12-02 | 1983-12-02 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18721883U JPS6094835U (en) | 1983-12-02 | 1983-12-02 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6094835U true JPS6094835U (en) | 1985-06-28 |
Family
ID=30404179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18721883U Pending JPS6094835U (en) | 1983-12-02 | 1983-12-02 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6094835U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5874047A (en) * | 1981-10-28 | 1983-05-04 | Toshiba Corp | Hybrid integrated circuit |
-
1983
- 1983-12-02 JP JP18721883U patent/JPS6094835U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5874047A (en) * | 1981-10-28 | 1983-05-04 | Toshiba Corp | Hybrid integrated circuit |
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