JPS593556U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS593556U
JPS593556U JP9786182U JP9786182U JPS593556U JP S593556 U JPS593556 U JP S593556U JP 9786182 U JP9786182 U JP 9786182U JP 9786182 U JP9786182 U JP 9786182U JP S593556 U JPS593556 U JP S593556U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor pellet
semiconductor
notch
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9786182U
Other languages
Japanese (ja)
Inventor
孝志 八木
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP9786182U priority Critical patent/JPS593556U/en
Publication of JPS593556U publication Critical patent/JPS593556U/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体装置の一例を示す一部透視平面図
、第2図は第1図半導体装置の製造に用いられるリード
フレームの平面図、第3図はり−ドフレームの他の例を
示す平面図、第4図は第3−図A−A断面図、第5図及
び第7図は第3図リードフレームの製法を説明する平面
図、第6図は第5図B−B断面図、第8図は第7図C−
C断面図、第9図は第3図リードフレームの変形例を示
す側面図、第10図は本考案の一実施例を示す半導体装
置の一部透視平面図、第11図は第10図一部透視側面
図である。 13・・・基板、13b・・・切欠き部、14・・・半
導体ペレット、15.15C・・・リード。
Fig. 1 is a partially transparent plan view showing an example of a conventional semiconductor device, Fig. 2 is a plan view of a lead frame used in the manufacture of the semiconductor device shown in Fig. 1, and Fig. 3 shows another example of a lead frame. FIG. 4 is a sectional view taken along line A-A in FIG. 3, FIGS. 5 and 7 are plan views explaining the manufacturing method of the lead frame shown in FIG. Figure 8 is Figure 7C-
9 is a side view showing a modification of the lead frame shown in FIG. 3, FIG. 10 is a partially transparent plan view of a semiconductor device showing an embodiment of the present invention, and FIG. FIG. 13...Substrate, 13b...Notch, 14...Semiconductor pellet, 15.15C...Lead.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板に載置した半導体ペレットの電極と、半導体ペレッ
トの近傍に配置したリードの一端部とを電気的に接続し
たものにおいて、上記基板の半導、体ペレット載置部近
傍に切欠きを設け、リードの一端部を切欠き部に配置し
たことを特徴とする半導体装置。
In a device in which an electrode of a semiconductor pellet placed on a substrate and one end of a lead placed near the semiconductor pellet are electrically connected, a notch is provided near the semiconductor pellet placement part of the substrate, A semiconductor device characterized in that one end of a lead is arranged in a notch.
JP9786182U 1982-06-29 1982-06-29 semiconductor equipment Pending JPS593556U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9786182U JPS593556U (en) 1982-06-29 1982-06-29 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9786182U JPS593556U (en) 1982-06-29 1982-06-29 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS593556U true JPS593556U (en) 1984-01-11

Family

ID=30232595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9786182U Pending JPS593556U (en) 1982-06-29 1982-06-29 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS593556U (en)

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