JPS6416636U - - Google Patents

Info

Publication number
JPS6416636U
JPS6416636U JP1987110940U JP11094087U JPS6416636U JP S6416636 U JPS6416636 U JP S6416636U JP 1987110940 U JP1987110940 U JP 1987110940U JP 11094087 U JP11094087 U JP 11094087U JP S6416636 U JPS6416636 U JP S6416636U
Authority
JP
Japan
Prior art keywords
electrode
chip
mounting structure
substrate
height
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987110940U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987110940U priority Critical patent/JPS6416636U/ja
Publication of JPS6416636U publication Critical patent/JPS6416636U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例の斜視図、第２図は
同側面図、第３図は従来の実装構造の一例を示す
斜視図、第４図は同側面図、第５図は従来の別の
実装構造例を示す側面図、第６図はさらに別の例
を示す斜視図である。 １……ＩＣチツプ、２……ボンデイングパツド
、３……ボンデイングワイヤ、４……基板、５…
…電極、１０……配線導体、１１……絶縁体層。 Fig. 1 is a perspective view of an embodiment of the present invention, Fig. 2 is a side view of the same, Fig. 3 is a perspective view showing an example of a conventional mounting structure, Fig. 4 is a side view of the same, and Fig. 5 is a conventional FIG. 6 is a side view showing another example of the mounting structure, and FIG. 6 is a perspective view showing still another example. 1...IC chip, 2...bonding pad, 3...bonding wire, 4...substrate, 5...
... Electrode, 10 ... Wiring conductor, 11 ... Insulator layer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板上に形成された電極に対向してＩＣチツプ
が配置され、前記電極とＩＣチツプのボンデイン
グパツドとがボンデイングワイヤで接続された実
装構造において、前記基板上の電極とＩＣチツプ
の間に配線導体を設けるとともに、この配線導体
と前記電極の間に絶縁体層を形成し、この絶縁体
層の高さを前記配線導体の高さよりも大きく設定
したことを特徴とする集積回路装置の実装構造。 In a mounting structure in which an IC chip is placed facing an electrode formed on a substrate, and the electrode and a bonding pad of the IC chip are connected with a bonding wire, wiring is provided between the electrode on the substrate and the IC chip. A mounting structure for an integrated circuit device, characterized in that a conductor is provided, an insulating layer is formed between the wiring conductor and the electrode, and the height of the insulating layer is set larger than the height of the wiring conductor. .
JP1987110940U 1987-07-20 1987-07-20 Pending JPS6416636U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987110940U JPS6416636U (en) 1987-07-20 1987-07-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987110940U JPS6416636U (en) 1987-07-20 1987-07-20

Publications (1)

Publication Number Publication Date
JPS6416636U true JPS6416636U (en) 1989-01-27

Family

ID=31348553

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987110940U Pending JPS6416636U (en) 1987-07-20 1987-07-20

Country Status (1)

Country Link
JP (1) JPS6416636U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513654A (en) * 1991-07-05 1993-01-22 Hitachi Cable Ltd Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513654A (en) * 1991-07-05 1993-01-22 Hitachi Cable Ltd Semiconductor integrated circuit device

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