JPS63140625U - - Google Patents
Info
- Publication number
- JPS63140625U JPS63140625U JP3270287U JP3270287U JPS63140625U JP S63140625 U JPS63140625 U JP S63140625U JP 3270287 U JP3270287 U JP 3270287U JP 3270287 U JP3270287 U JP 3270287U JP S63140625 U JPS63140625 U JP S63140625U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- metal
- metal conductor
- external connection
- lead electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の半導体集積回路用パツケージ
の一実施例を示す図、第２図は従来の半導体集積
回路用パツケージを示す図である。
１はセラミツク基板、２は金属導電体、２ａ〜
２ｆは特定外部接続用リード電極に接続される金
属導電体、３は外部接続用リード電極、３ａ〜３
ｆは特定外部接続用リード電極、４は半導体チツ
プ、５はボンデイングワイヤ。なお、図中、同一
符号は同一、又は相当部分を示す。
FIG. 1 shows an embodiment of the semiconductor integrated circuit package of the present invention, and FIG. 2 shows a conventional semiconductor integrated circuit package. 1 is a ceramic substrate, 2 is a metal conductor, 2a~
2f is a metal conductor connected to a specific external connection lead electrode, 3 is an external connection lead electrode, 3a to 3
f is a lead electrode for specific external connection, 4 is a semiconductor chip, and 5 is a bonding wire. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
絶縁基板において、外部接続用リード電極の特定
ピンに接続されている金属導電体であることを表
示するために、他の金属導電体と形状を一部異に
して絶縁基板に印刷配線した金属導電体を有する
半導体集積回路用パツケージ。 In an insulated substrate with a metal conductor on which a semiconductor integrated circuit is mounted, a part of the shape is changed from that of other metal conductors to indicate that the metal conductor is connected to a specific pin of an external connection lead electrode. A package for semiconductor integrated circuits that has metal conductors printed on an insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3270287U JPS63140625U (en) | 1987-03-06 | 1987-03-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3270287U JPS63140625U (en) | 1987-03-06 | 1987-03-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63140625U true JPS63140625U (en) | 1988-09-16 |
Family
ID=30839634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3270287U Pending JPS63140625U (en) | 1987-03-06 | 1987-03-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63140625U (en) |
-
1987
- 1987-03-06 JP JP3270287U patent/JPS63140625U/ja active Pending
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