JPH02114943U - - Google Patents

Info

Publication number
JPH02114943U
JPH02114943U JP1989022554U JP2255489U JPH02114943U JP H02114943 U JPH02114943 U JP H02114943U JP 1989022554 U JP1989022554 U JP 1989022554U JP 2255489 U JP2255489 U JP 2255489U JP H02114943 U JPH02114943 U JP H02114943U
Authority
JP
Japan
Prior art keywords
semiconductor element
base metal
resin
mounting structure
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989022554U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989022554U priority Critical patent/JPH02114943U/ja
Publication of JPH02114943U publication Critical patent/JPH02114943U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例における半導体素子
の実装構造を示す断面図、第2図および第3図は
それぞれ別実施例を示す半導体素子の実装構造の
断面図である。第4図は半導体素子の実装構造の
従来例を示す断面図である。 1:半導体チツプ、2:ベース金属、4:リー
ド端子、5:ワイヤー、6:樹脂、7:絶縁層。
FIG. 1 is a cross-sectional view showing a semiconductor element mounting structure according to one embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views of semiconductor element mounting structures showing other embodiments. FIG. 4 is a sectional view showing a conventional example of a semiconductor element mounting structure. 1: Semiconductor chip, 2: Base metal, 4: Lead terminal, 5: Wire, 6: Resin, 7: Insulating layer.

Claims (1)

【実用新案登録請求の範囲】 ベース金属の表面に半導体素子を固着し、この
半導体素子の電極部とリード端子とをワイヤーに
て電気的に接続し、前記半導体素子とベース金属
とを樹脂で封止するとともに前記リード端子の一
端を樹脂外部に突出して成る半導体素子の実装構
造において、 前記ベース金属の裏面に予め一体に設けられた
絶縁層を有し、この絶縁層の下層を前記樹脂で封
止しないよう構成することを特徴とする半導体素
子の実装構造。
[Claims for Utility Model Registration] A semiconductor element is fixed to the surface of a base metal, the electrode portion of this semiconductor element and a lead terminal are electrically connected with a wire, and the semiconductor element and the base metal are sealed with a resin. In the mounting structure for a semiconductor element, the structure includes an insulating layer provided integrally with the back surface of the base metal, and a lower layer of the insulating layer being sealed with the resin. What is claimed is: 1. A mounting structure for a semiconductor element, characterized in that it is configured so as not to stop.
JP1989022554U 1989-02-28 1989-02-28 Pending JPH02114943U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989022554U JPH02114943U (en) 1989-02-28 1989-02-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989022554U JPH02114943U (en) 1989-02-28 1989-02-28

Publications (1)

Publication Number Publication Date
JPH02114943U true JPH02114943U (en) 1990-09-14

Family

ID=31240778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989022554U Pending JPH02114943U (en) 1989-02-28 1989-02-28

Country Status (1)

Country Link
JP (1) JPH02114943U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012248658A (en) * 2011-05-27 2012-12-13 Aisin Seiki Co Ltd Semiconductor device
JP2013536585A (en) * 2010-08-25 2013-09-19 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Electric circuit manufacturing method and electric circuit
WO2015037072A1 (en) * 2013-09-11 2015-03-19 三菱電機株式会社 Semiconductor device and manufacturing method for same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013536585A (en) * 2010-08-25 2013-09-19 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Electric circuit manufacturing method and electric circuit
JP2012248658A (en) * 2011-05-27 2012-12-13 Aisin Seiki Co Ltd Semiconductor device
WO2015037072A1 (en) * 2013-09-11 2015-03-19 三菱電機株式会社 Semiconductor device and manufacturing method for same
JPWO2015037072A1 (en) * 2013-09-11 2017-03-02 三菱電機株式会社 Semiconductor device and manufacturing method thereof

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