JPH0451145U - - Google Patents
Info
- Publication number
- JPH0451145U JPH0451145U JP9212090U JP9212090U JPH0451145U JP H0451145 U JPH0451145 U JP H0451145U JP 9212090 U JP9212090 U JP 9212090U JP 9212090 U JP9212090 U JP 9212090U JP H0451145 U JPH0451145 U JP H0451145U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- insulating material
- electrodes
- bonding
- covered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011810 insulating material Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 description 4
- 239000012774 insulation material Substances 0.000 description 1
Description
第１図は、本考案の実施例を示す半導体チツプ
部品を回路基板に搭載した状態の縦断側面図、第
２図は、従来例を示す半導体チツプ部品を回路基
板に搭載した状態の縦断側面図、第３図は、半導
体チツプ部品を回路基板に搭載した状態の絶縁材
を除く斜視図、第４図と第５図は、本考案の他の
各実施例を示す半導体チツプ部品を回路基板に搭
載した状態の縦断側面図である。
１……回路基板、２……ダイランド、３……ボ
ンデイング用電極、４……ワイヤー、５……チツ
プ部品、６……下面電極、７……上面電極、８…
…絶縁材、９……キヤツプ、９′……板体。
FIG. 1 is a vertical side view of a semiconductor chip component mounted on a circuit board, showing an embodiment of the present invention, and FIG. 2 is a vertical side view of a conventional example of a semiconductor chip component mounted on a circuit board. , FIG. 3 is a perspective view of a semiconductor chip component mounted on a circuit board with insulation material removed, and FIGS. 4 and 5 show semiconductor chip components mounted on a circuit board showing other embodiments of the present invention. FIG. 3 is a vertical side view of the vehicle in a mounted state. DESCRIPTION OF SYMBOLS 1... Circuit board, 2... Die land, 3... Bonding electrode, 4... Wire, 5... Chip parts, 6... Lower surface electrode, 7... Upper surface electrode, 8...
...insulating material, 9...cap, 9'...plate.
Claims (1)
，７…を有するチツプ部品５を回路基板１の上に
実装し、前記上面側電極７，７…をワイヤー４，
４…で回路基板１上のボンデイング用電極３，３
…に接続し、この周囲を絶縁材８で覆つてなる半
導体チツプ実装回路基板において、前記絶縁材８
の少なくとも上面に、チツプ部品５、ワイヤー４
，４…及びボンデイング電極３，３…に対して絶
縁された平板状の部材を被せたことを特徴とする
半導体チツプ実装回路基板。 Upper surface side electrode 7 for wire bonding on the upper surface
, 7... is mounted on the circuit board 1, and the upper surface side electrodes 7, 7... are connected to the wires 4, 7...
4... bonding electrodes 3, 3 on the circuit board 1
... and whose periphery is covered with an insulating material 8, the insulating material 8
At least on the upper surface of the chip part 5 and the wire 4
, 4... and bonding electrodes 3, 3... are covered with an insulated flat member.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9212090U JPH0451145U (en) | 1990-08-31 | 1990-08-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9212090U JPH0451145U (en) | 1990-08-31 | 1990-08-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0451145U true JPH0451145U (en) | 1992-04-30 |
Family
ID=31828339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9212090U Pending JPH0451145U (en) | 1990-08-31 | 1990-08-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451145U (en) |
-
1990
- 1990-08-31 JP JP9212090U patent/JPH0451145U/ja active Pending