JPS6397241U - - Google Patents
Info
- Publication number
- JPS6397241U JPS6397241U JP1986191531U JP19153186U JPS6397241U JP S6397241 U JPS6397241 U JP S6397241U JP 1986191531 U JP1986191531 U JP 1986191531U JP 19153186 U JP19153186 U JP 19153186U JP S6397241 U JPS6397241 U JP S6397241U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- semiconductor
- lead frame
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims 1
- 239000000615 nonconductor Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第1図、第2図は本考案の半導体装置の縦断面
図、第3図は従来の半導体装置の縦断面図である
。
1…リードフレーム、2…樹脂、3…ボンデイ
ングワイヤ、4…半導体集積回路。
1 and 2 are longitudinal sectional views of a semiconductor device of the present invention, and FIG. 3 is a longitudinal sectional view of a conventional semiconductor device. 1... Lead frame, 2... Resin, 3... Bonding wire, 4... Semiconductor integrated circuit.
Claims (1)
る型の半導体集積回路装置用プラスチツクパツケ
ージにおいて、リードフレームに搭載された半導
体集積回路等をカバーする電気的絶縁物上に、半
導体集積回路、ボンデイングワイヤ等に接触する
ことなく、表面に金属またはプラスチツク層を設
けたことを特徴とする半導体装置。 In a plastic package for a semiconductor integrated circuit device in which the semiconductor integrated circuit device is mounted on a lead frame, contact with the semiconductor integrated circuit, bonding wire, etc. is made on the electrical insulator that covers the semiconductor integrated circuit mounted on the lead frame. 1. A semiconductor device characterized in that a metal or plastic layer is provided on the surface of the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986191531U JPS6397241U (en) | 1986-12-12 | 1986-12-12 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986191531U JPS6397241U (en) | 1986-12-12 | 1986-12-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6397241U true JPS6397241U (en) | 1988-06-23 |
Family
ID=31145758
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986191531U Pending JPS6397241U (en) | 1986-12-12 | 1986-12-12 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6397241U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04127456A (en) * | 1989-09-14 | 1992-04-28 | Toshiba Corp | Resin-sealed semiconductor device and its manufacture |
-
1986
- 1986-12-12 JP JP1986191531U patent/JPS6397241U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04127456A (en) * | 1989-09-14 | 1992-04-28 | Toshiba Corp | Resin-sealed semiconductor device and its manufacture |