JPS62152456U - - Google Patents

Info

Publication number
JPS62152456U
JPS62152456U JP1986039079U JP3907986U JPS62152456U JP S62152456 U JPS62152456 U JP S62152456U JP 1986039079 U JP1986039079 U JP 1986039079U JP 3907986 U JP3907986 U JP 3907986U JP S62152456 U JPS62152456 U JP S62152456U
Authority
JP
Japan
Prior art keywords
insulating layer
lead frame
semiconductor device
semiconductor element
tab
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986039079U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986039079U priority Critical patent/JPS62152456U/ja
Publication of JPS62152456U publication Critical patent/JPS62152456U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の半導体装置の一実施例の一部
を破砕して示す斜視図、第2図は第1図における
リードフレームを示す斜視図、第3図は従来の半
導体装置の一例の一部を破砕して示す斜視図であ
る。 1…半導体素子、2…タブ吊りリード、3…タ
ブ、4…リードフレーム、5…ワイヤ、6…パツ
ケージ、10…本発明によるリードフレーム、2
0…リードフレームの基板、21…絶縁層、22
…配線パターン。
FIG. 1 is a partially fragmented perspective view of an embodiment of the semiconductor device of the present invention, FIG. 2 is a perspective view of the lead frame in FIG. 1, and FIG. 3 is an example of a conventional semiconductor device. FIG. 2 is a partially fragmented perspective view. DESCRIPTION OF SYMBOLS 1...Semiconductor element, 2...Tab suspension lead, 3...Tab, 4...Lead frame, 5...Wire, 6...Package, 10...Lead frame according to the present invention, 2
0... Lead frame substrate, 21... Insulating layer, 22
...Wiring pattern.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] タブに固着された半導体素子と、ワイヤによつ
て半導体素子と接続されたリードフレームとを樹
脂でモールドする半導体装置において、42アロ
イなどの金属材料を基板とする前記リードフレー
ムの表面に絶縁層を設け、この絶縁層上に配線パ
ターンを形成したことを特徴とする半導体装置。
In a semiconductor device in which a semiconductor element fixed to a tab and a lead frame connected to the semiconductor element by wire are molded with resin, an insulating layer is provided on the surface of the lead frame whose substrate is a metal material such as 42 alloy. What is claimed is: 1. A semiconductor device comprising: an insulating layer, and a wiring pattern formed on the insulating layer.
JP1986039079U 1986-03-19 1986-03-19 Pending JPS62152456U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986039079U JPS62152456U (en) 1986-03-19 1986-03-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986039079U JPS62152456U (en) 1986-03-19 1986-03-19

Publications (1)

Publication Number Publication Date
JPS62152456U true JPS62152456U (en) 1987-09-28

Family

ID=30851920

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986039079U Pending JPS62152456U (en) 1986-03-19 1986-03-19

Country Status (1)

Country Link
JP (1) JPS62152456U (en)

Similar Documents

Publication Publication Date Title
JPS62152456U (en)
JPH02114943U (en)
JPS6448051U (en)
JPS6234441U (en)
JPH0451145U (en)
JPH0233442U (en)
JPH0176040U (en)
JPH01174946U (en)
JPS6397241U (en)
JPS61114842U (en)
JPH0262734U (en)
JPH02146437U (en)
JPS61123544U (en)
JPS6364050U (en)
JPS61149347U (en)
JPS63201330U (en)
JPH0173935U (en)
JPS63142843U (en)
JPS62145337U (en)
JPH0336478U (en)
JPS6190244U (en)
JPH0256460U (en)
JPH01135736U (en)
JPH0476046U (en)
JPH0377454U (en)