JPS63201330U - - Google Patents
Info
- Publication number
- JPS63201330U JPS63201330U JP9358387U JP9358387U JPS63201330U JP S63201330 U JPS63201330 U JP S63201330U JP 9358387 U JP9358387 U JP 9358387U JP 9358387 U JP9358387 U JP 9358387U JP S63201330 U JPS63201330 U JP S63201330U
- Authority
- JP
- Japan
- Prior art keywords
- tab
- lead frame
- fixed
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Description
第１図は本考案の実施例を示す平面図、第２図
はその側面図、第３図は従来例を示す側面図であ
る。
１……タブ（リードフレームの）、２……半導
体素子、３……基板、４……パターン、６……金
線、７……絶縁体。
FIG. 1 is a plan view showing an embodiment of the present invention, FIG. 2 is a side view thereof, and FIG. 3 is a side view showing a conventional example. 1...Tab (of lead frame), 2...Semiconductor element, 3...Substrate, 4...Pattern, 6...Gold wire, 7...Insulator.
Claims (1)
ーンを配線している基板を固着し、該基板上に２
個以上の半導体素子をマウントをしてワイヤーボ
ンデイングした半導体装置において、 前記リードフレームのタブに凹部を作り、非導
電接着剤で基板を固着することを特徴とする半導
体装置。[Claims for Utility Model Registration] A board with patterns wired on both sides of the tab of a metal lead frame is fixed, and two
What is claimed is: 1. A semiconductor device in which more than one semiconductor element is mounted and wire bonded, the semiconductor device comprising: a recessed portion being formed in the tab of the lead frame, and a substrate being fixed with a non-conductive adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9358387U JPS63201330U (en) | 1987-06-18 | 1987-06-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9358387U JPS63201330U (en) | 1987-06-18 | 1987-06-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63201330U true JPS63201330U (en) | 1988-12-26 |
Family
ID=30956281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9358387U Pending JPS63201330U (en) | 1987-06-18 | 1987-06-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63201330U (en) |
-
1987
- 1987-06-18 JP JP9358387U patent/JPS63201330U/ja active Pending