JPS61207026U - - Google Patents
Info
- Publication number
- JPS61207026U JPS61207026U JP9011485U JP9011485U JPS61207026U JP S61207026 U JPS61207026 U JP S61207026U JP 9011485 U JP9011485 U JP 9011485U JP 9011485 U JP9011485 U JP 9011485U JP S61207026 U JPS61207026 U JP S61207026U
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- semiconductor chip
- die bonding
- bonding pattern
- smaller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
第１図は本考案の一実施例のパターンの平面図
、第２図は半導体チツプを実装した時の側面図で
ある。
１…半導体チツプ、４…マーク・パターン、５
…ワイヤー、７…基板。
FIG. 1 is a plan view of a pattern according to an embodiment of the present invention, and FIG. 2 is a side view when a semiconductor chip is mounted. 1...Semiconductor chip, 4...Mark pattern, 5
...wire, 7...board.
Claims (1)
において、半導体チツプよりも小さいダイボンデ
イング・パターンを有し、その周囲にワイヤーボ
ンデイング・パターンをもうけ、両パターンの間
に電気的に独立して、かつ半導体チツプの位置が
解かるマーク・パターンをもうけたことを特徴と
する半導体実装パツケージ。 In the pattern of a package that mounts a semiconductor chip, it has a die bonding pattern that is smaller than the semiconductor chip, a wire bonding pattern is provided around the die bonding pattern, and the pattern is electrically independent between the two patterns and the position of the semiconductor chip is smaller than the die bonding pattern. A semiconductor mounting package characterized by having a mark pattern that makes it easy to understand.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9011485U JPS61207026U (en) | 1985-06-17 | 1985-06-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9011485U JPS61207026U (en) | 1985-06-17 | 1985-06-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61207026U true JPS61207026U (en) | 1986-12-27 |
Family
ID=30644820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9011485U Pending JPS61207026U (en) | 1985-06-17 | 1985-06-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61207026U (en) |
-
1985
- 1985-06-17 JP JP9011485U patent/JPS61207026U/ja active Pending