JPS64332U - - Google Patents
Info
- Publication number
- JPS64332U JPS64332U JP9418787U JP9418787U JPS64332U JP S64332 U JPS64332 U JP S64332U JP 9418787 U JP9418787 U JP 9418787U JP 9418787 U JP9418787 U JP 9418787U JP S64332 U JPS64332 U JP S64332U
- Authority
- JP
- Japan
- Prior art keywords
- lead terminal
- inner lead
- recognition pattern
- ceramic
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例を示すセラミツク・
パツケージの平面図、第２図および第３図は本考
案にかかる十文字形状のリード側認識パターンに
リードの認識線をあてた状態を示す拡大図および
半導体集積回路素子の自動ボンデイングによる実
装図である。
１……セラミツク基板、２……セラミツク基板
のコーナー部、３……十文字形状のリード側認識
用パターン、４……インナー・リード端子、５…
…リード認識線、６……半導体集積回路素子、７
……ボンデイングワイヤ。
Figure 1 shows a ceramic plate showing an embodiment of the present invention.
The plan view of the package, FIGS. 2 and 3 are an enlarged view showing the lead recognition line applied to the cross-shaped lead side recognition pattern according to the present invention, and a mounting diagram of the semiconductor integrated circuit element by automatic bonding. . DESCRIPTION OF SYMBOLS 1...Ceramic board, 2...Corner part of ceramic board, 3...Cross-shaped lead side recognition pattern, 4...Inner lead terminal, 5...
...Lead recognition line, 6...Semiconductor integrated circuit element, 7
...Bonding wire.
Claims (1)
に前記インナー・リード端子とは形状の異なる特
有形状のリード側認識用パターンを設けることを
特徴とする半導体装置用セラミツク・パツケージ
。 A ceramic package for a semiconductor device, characterized in that a lead-side recognition pattern having a unique shape different from that of the inner lead terminal is provided near the inner lead terminal of the ceramic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9418787U JPS64332U (en) | 1987-06-18 | 1987-06-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9418787U JPS64332U (en) | 1987-06-18 | 1987-06-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS64332U true JPS64332U (en) | 1989-01-05 |
Family
ID=30957405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9418787U Pending JPS64332U (en) | 1987-06-18 | 1987-06-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS64332U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001024252A1 (en) * | 1999-09-28 | 2001-04-05 | Matsushita Electric Industrial Co., Ltd. | Electronic device and method of manufacture thereof |
-
1987
- 1987-06-18 JP JP9418787U patent/JPS64332U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001024252A1 (en) * | 1999-09-28 | 2001-04-05 | Matsushita Electric Industrial Co., Ltd. | Electronic device and method of manufacture thereof |