JPH0189722U - - Google Patents
Info
- Publication number
- JPH0189722U JPH0189722U JP18510787U JP18510787U JPH0189722U JP H0189722 U JPH0189722 U JP H0189722U JP 18510787 U JP18510787 U JP 18510787U JP 18510787 U JP18510787 U JP 18510787U JP H0189722 U JPH0189722 U JP H0189722U
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- chip electronic
- mounting
- resin
- large number
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図ａ，ｂは本考案の一実施例の底面図及び
断面図、第２図は第１図のチツプ電子部品を搭載
基板に実装した断面図、第３図は従来のチツプ電
子部品の一例の底面図及び断面図、第４図は第３
図のチツプ電子部品を搭載基板に実装した断面図
である。
１…モールド樹脂、２…凹凸、３…リード端子
、４…はんだ層、５…接着剤、６…導体層、７…
搭載基板、１１…モールド樹脂。
Figures 1a and b are a bottom view and a sectional view of an embodiment of the present invention, Figure 2 is a sectional view of the chip electronic component shown in Figure 1 mounted on a mounting board, and Figure 3 is a diagram of a conventional chip electronic component. An example of the bottom view and cross-sectional view, Figure 4 is the 3rd
FIG. 3 is a sectional view of the chip electronic component shown in the figure mounted on a mounting board. DESCRIPTION OF SYMBOLS 1...Mold resin, 2...Irregularities, 3...Lead terminals, 4...Solder layer, 5...Adhesive, 6...Conductor layer, 7...
Mounting board, 11...Mold resin.
Claims (1)
電子部品において、前記チツプ電子部品の搭載基
板との接着面が多数の微細な凹凸を有することを
特徴とするチツプ電子部品。 1. A resin-sealed chip electronic component for automatic solder dip mounting, characterized in that a bonding surface of the chip electronic component to a mounting substrate has a large number of fine irregularities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18510787U JPH0189722U (en) | 1987-12-03 | 1987-12-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18510787U JPH0189722U (en) | 1987-12-03 | 1987-12-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0189722U true JPH0189722U (en) | 1989-06-13 |
Family
ID=31476435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18510787U Pending JPH0189722U (en) | 1987-12-03 | 1987-12-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0189722U (en) |
-
1987
- 1987-12-03 JP JP18510787U patent/JPH0189722U/ja active Pending
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