JPH0179832U - - Google Patents
Info
- Publication number
- JPH0179832U JPH0179832U JP17623487U JP17623487U JPH0179832U JP H0179832 U JPH0179832 U JP H0179832U JP 17623487 U JP17623487 U JP 17623487U JP 17623487 U JP17623487 U JP 17623487U JP H0179832 U JPH0179832 U JP H0179832U
- Authority
- JP
- Japan
- Prior art keywords
- opening
- wiring board
- printed wiring
- bare chip
- semiconductor bare
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 1
- 239000002344 surface layer Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Description
第１図は本考案の実施例の説明図で、第２図は
その実装状態を示す断面図、第３図は本考案の他
の実施態様の説明図で、第４図はその実装状態を
示す断面図、第５図は従来技術の説明図。
１０……基板、１２……絶縁層、１４，１６…
…導体パターン、１８……開口部、５０……半導
体ベアチツプ、５２……ボンデイング接着剤、５
４……ボンデイングワイヤ、５６……封止樹脂。
Fig. 1 is an explanatory diagram of an embodiment of the present invention, Fig. 2 is a sectional view showing its mounting state, Fig. 3 is an explanatory diagram of another embodiment of the present invention, and Fig. 4 is an explanatory diagram of its mounting state. The sectional view shown in FIG. 5 is an explanatory diagram of the prior art. 10...Substrate, 12...Insulating layer, 14, 16...
...Conductor pattern, 18...Opening, 50...Semiconductor bare chip, 52...Bonding adhesive, 5
4... Bonding wire, 56... Sealing resin.
Claims (1)
ングする多層構造のプリント配線板において、基
板１０の少なくとも表面層に開口部１８を設けて
、当該開口部１８の底に当る中間層の部分を、半
導体ベアチツプ５０の実装部分にすることができ
るようにしたことを特徴とする、プリント配線板
。 (2) 開口部１８が階段状をなして上方にゆくほ
ど広くなつていることを特徴とする、実用新案登
録請求の範囲第１項に記載のプリント配線板。[Claims for Utility Model Registration] (1) In a printed wiring board with a multilayer structure in which a semiconductor bare chip 50 is directly die-bonded, an opening 18 is provided in at least the surface layer of the substrate 10, and an intermediate portion corresponding to the bottom of the opening 18 is provided. A printed wiring board characterized in that a layer portion can be used as a mounting portion for a semiconductor bare chip 50. (2) The printed wiring board according to claim 1, wherein the opening 18 is step-shaped and becomes wider as it goes upward.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17623487U JPH0179832U (en) | 1987-11-18 | 1987-11-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17623487U JPH0179832U (en) | 1987-11-18 | 1987-11-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0179832U true JPH0179832U (en) | 1989-05-29 |
Family
ID=31467979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17623487U Pending JPH0179832U (en) | 1987-11-18 | 1987-11-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0179832U (en) |
-
1987
- 1987-11-18 JP JP17623487U patent/JPH0179832U/ja active Pending