JPS61123544U - - Google Patents

Info

Publication number
JPS61123544U
JPS61123544U JP670185U JP670185U JPS61123544U JP S61123544 U JPS61123544 U JP S61123544U JP 670185 U JP670185 U JP 670185U JP 670185 U JP670185 U JP 670185U JP S61123544 U JPS61123544 U JP S61123544U
Authority
JP
Japan
Prior art keywords
insulating substrate
resin
semiconductor device
board
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP670185U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP670185U priority Critical patent/JPS61123544U/ja
Publication of JPS61123544U publication Critical patent/JPS61123544U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例の断面図、第２図は
第１図の三次元構成図、第３図は第２の実施例の
断面図、第４図はその立体図、第５図は第３図の
平面図である。 １…封止樹脂、２…半導体ペレツト、３…絶縁
基板、４…内部配線、５…Ａｕバンプ、６…ボン
デイングワイヤ。 Fig. 1 is a sectional view of one embodiment of the present invention, Fig. 2 is a three-dimensional configuration diagram of Fig. 1, Fig. 3 is a sectional view of the second embodiment, Fig. 4 is a three-dimensional view thereof, and Fig. 5 is a sectional view of the second embodiment. The figure is a plan view of FIG. 3. DESCRIPTION OF SYMBOLS 1... Sealing resin, 2... Semiconductor pellet, 3... Insulating substrate, 4... Internal wiring, 5... Au bump, 6... Bonding wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体ペレツト、タブ、リードよりなる樹脂封
止型半導体装置において、タブ材に絶縁基板ある
いは配線基板を使用し、その絶縁基板あるいは配
線基板の内部あるいは表面に電気配線を施し、基
板の上下にそれぞれ電気的に接続した１個あるい
は複数個の半導体ペレツト間の信号伝達を可能に
したことを特徴とする樹脂封止型半導体装置。 In a resin-sealed semiconductor device consisting of semiconductor pellets, tabs, and leads, an insulating substrate or a wiring board is used as the tab material, electrical wiring is provided inside or on the surface of the insulating substrate or wiring board, and electrical wiring is provided on the top and bottom of the board. 1. A resin-sealed semiconductor device characterized in that it enables signal transmission between one or more semiconductor pellets that are connected to each other.
JP670185U 1985-01-23 1985-01-23 Pending JPS61123544U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP670185U JPS61123544U (en) 1985-01-23 1985-01-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP670185U JPS61123544U (en) 1985-01-23 1985-01-23

Publications (1)

Publication Number Publication Date
JPS61123544U true JPS61123544U (en) 1986-08-04

Family

ID=30484386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP670185U Pending JPS61123544U (en) 1985-01-23 1985-01-23

Country Status (1)

Country Link
JP (1) JPS61123544U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06209072A (en) * 1994-02-03 1994-07-26 Kazumasa Sugano Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06209072A (en) * 1994-02-03 1994-07-26 Kazumasa Sugano Semiconductor integrated circuit

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