JPH0367430U - - Google Patents
Info
- Publication number
- JPH0367430U JPH0367430U JP1989128736U JP12873689U JPH0367430U JP H0367430 U JPH0367430 U JP H0367430U JP 1989128736 U JP1989128736 U JP 1989128736U JP 12873689 U JP12873689 U JP 12873689U JP H0367430 U JPH0367430 U JP H0367430U
- Authority
- JP
- Japan
- Prior art keywords
- package
- internal connection
- connection terminal
- protrusion
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
Landscapes
- Wire Bonding (AREA)
Description
第１図Ａ，Ｂ，Ｃは本考案でのマイクロ波パツ
ケージの構造例を示す図、第２図Ａ，Ｂ，Ｃは従
来例のマイクロ波パツケージの構造例を示す図、
である。
図において、１……外部端子、３……内部接続
端子、３ａ……突出部、５……パツケージ、５ｂ
……切欠部、７……集積基板、８……ベアチツプ
、９……金ワイヤ、を示す。
FIGS. 1A, B, and C are diagrams showing an example of the structure of a microwave package according to the present invention, and FIGS. 2A, B, and C are diagrams showing an example of the structure of a conventional microwave package.
It is. In the figure, 1...External terminal, 3...Internal connection terminal, 3a...Protrusion, 5...Package, 5b
. . . notch, 7 . . . integrated substrate, 8 . . . bare chip, 9 . . . gold wire.
Claims (1)
、外部バイアスを供給する内部接続端子３と、実
装面上にチツプ形状の半導体素子８を搭載した集
積基板７とからなり、かつそれぞれが金ワイヤ９
により接続されてパツケージ５に収納されたるも
のにおいて、 一方側の突出部３ａが前記パツケージ５の底部
５ａより低くなるように前記内部接続端子３を設
け、かつ該内部接続端子３の前記突出部３ａの周
囲の前記パツケージ５の部分にワイヤボンデイン
グを可能にする切欠部５ｂを設け、 前記内部接続端子３の上面領域を集積基板７の
実装可能領域にしたことを特徴とするマイクロ波
回路用パツケージ。[Claim for Utility Model Registration] An external terminal 1 serving as an input/output terminal for microwave signals, an internal connection terminal 3 for supplying an external bias, and an integrated substrate 7 on which a chip-shaped semiconductor element 8 is mounted on the mounting surface. and each gold wire 9
The internal connection terminal 3 is provided such that the protrusion 3a on one side is lower than the bottom 5a of the package 5, and the protrusion 3a of the internal connection terminal 3 is A package for a microwave circuit, characterized in that a notch 5b is provided in a portion of the package 5 around the periphery of the package 5 to enable wire bonding, and the upper surface area of the internal connection terminal 3 is made an area where an integrated substrate 7 can be mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989128736U JPH0719148Y2 (en) | 1989-11-01 | 1989-11-01 | Microwave circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989128736U JPH0719148Y2 (en) | 1989-11-01 | 1989-11-01 | Microwave circuit package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0367430U true JPH0367430U (en) | 1991-07-01 |
| JPH0719148Y2 JPH0719148Y2 (en) | 1995-05-01 |
Family
ID=31676422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989128736U Expired - Lifetime JPH0719148Y2 (en) | 1989-11-01 | 1989-11-01 | Microwave circuit package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0719148Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008026568A (en) * | 2006-07-20 | 2008-02-07 | Olympus Corp | Optical microscope |
-
1989
- 1989-11-01 JP JP1989128736U patent/JPH0719148Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008026568A (en) * | 2006-07-20 | 2008-02-07 | Olympus Corp | Optical microscope |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0719148Y2 (en) | 1995-05-01 |