JPS646038U - - Google Patents

Info

Publication number
JPS646038U
JPS646038U JP1987100847U JP10084787U JPS646038U JP S646038 U JPS646038 U JP S646038U JP 1987100847 U JP1987100847 U JP 1987100847U JP 10084787 U JP10084787 U JP 10084787U JP S646038 U JPS646038 U JP S646038U
Authority
JP
Japan
Prior art keywords
wire bonding
conductive pattern
chip
chip mount
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987100847U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987100847U priority Critical patent/JPS646038U/ja
Publication of JPS646038U publication Critical patent/JPS646038U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案に係る半導体素子の一実施例を
示すパツケージ樹脂除去状態の正面図、第２図は
同断面図、第３図は従来例を示す斜視図である。 １……絶縁基板、２……チツプマウント部、３
……ワイヤボンデイング部、４Ａ及び４Ｂ……外
部接続部、５Ａ及び５Ｂ……連絡部、６……半導
体チツプ、７……金線、８……樹脂パツケージ。 FIG. 1 is a front view showing an embodiment of a semiconductor device according to the present invention with the package resin removed, FIG. 2 is a sectional view of the same, and FIG. 3 is a perspective view of a conventional example. 1... Insulating board, 2... Chip mount section, 3
... wire bonding section, 4A and 4B ... external connection section, 5A and 5B ... communication section, 6 ... semiconductor chip, 7 ... gold wire, 8 ... resin package.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁基板に、チツプマウント部、ワイヤボンデ
イング部、外部接続部、連絡部を有するように導
電パターンを形成し、そのチツプマウント部に半
導体チツプを搭載して、その電極部と前記ワイヤ
ボンデイング部の間をワイヤボンデイングによつ
て接続し、前記半導体チツプなどの周りに樹脂モ
ールドによりパツケージを形成するようにしたミ
ニサイズの半導体素子において、前記導電パター
ンにおける外部接続部とチツプマウント部、ワイ
ヤボンデイング部との間を結ぶ連絡部をチツプマ
ウント部、ワイヤボンデイング部の周辺に回廊状
に形成したことを特徴とする半導体素子。 A conductive pattern is formed on an insulating substrate so as to have a chip mount part, a wire bonding part, an external connection part, and a communication part, a semiconductor chip is mounted on the chip mount part, and a conductive pattern is formed between the electrode part and the wire bonding part. In a mini-sized semiconductor device in which the semiconductor chips are connected by wire bonding and a package is formed around the semiconductor chip etc. by resin molding, the external connection part in the conductive pattern, the chip mount part, and the wire bonding part are connected to each other by wire bonding. What is claimed is: 1. A semiconductor device characterized in that a connecting part is formed in a corridor shape around a chip mount part and a wire bonding part.
JP1987100847U 1987-06-30 1987-06-30 Pending JPS646038U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987100847U JPS646038U (en) 1987-06-30 1987-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987100847U JPS646038U (en) 1987-06-30 1987-06-30

Publications (1)

Publication Number Publication Date
JPS646038U true JPS646038U (en) 1989-01-13

Family

ID=31329295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987100847U Pending JPS646038U (en) 1987-06-30 1987-06-30

Country Status (1)

Country Link
JP (1) JPS646038U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0922961A (en) * 1995-07-06 1997-01-21 Nec Corp Bga-type semiconductor device
JP2007059837A (en) * 2005-08-26 2007-03-08 Stanley Electric Co Ltd Surface mounted led

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0922961A (en) * 1995-07-06 1997-01-21 Nec Corp Bga-type semiconductor device
JP2007059837A (en) * 2005-08-26 2007-03-08 Stanley Electric Co Ltd Surface mounted led

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