JPH0192143U - - Google Patents
Info
- Publication number
- JPH0192143U JPH0192143U JP1987189105U JP18910587U JPH0192143U JP H0192143 U JPH0192143 U JP H0192143U JP 1987189105 U JP1987189105 U JP 1987189105U JP 18910587 U JP18910587 U JP 18910587U JP H0192143 U JPH0192143 U JP H0192143U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- bonded
- chip
- semiconductor
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
第１図は本考案の実施例の断面図、第２図は本
考案の他の実施例の断面図、第３図ａ，ｂはそれ
ぞれ従来例の断面図である。
図において、１は半導体チツプ、２は回路基板
、３は入出力信号線、４は電極、６はボンデイン
グワイヤ、７，２２は半田バンプ、１０は金属基
板、２０は冷却板、２１は半田層をそれぞれ示す
。
FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a sectional view of another embodiment of the invention, and FIGS. 3a and 3b are sectional views of a conventional example. In the figure, 1 is a semiconductor chip, 2 is a circuit board, 3 is an input/output signal line, 4 is an electrode, 6 is a bonding wire, 7 and 22 are solder bumps, 10 is a metal substrate, 20 is a cooling plate, and 21 is a solder layer. are shown respectively.
Claims (1)
プボンデイングした半導体装置であつて、 金属よりなる冷却板２０の下面が、半田層２１
、或いは多数の半田バンプ２２を介して、該半導
体チツプ１の底面に密着されてなることを特徴と
する半導体チツプの実装構造。[Scope of Claim for Utility Model Registration] A semiconductor device in which a semiconductor chip 1 is flip-chip bonded to a circuit board 2, wherein the lower surface of a cooling plate 20 made of metal is bonded to a solder layer 21.
, or a semiconductor chip mounting structure characterized in that the semiconductor chip 1 is closely attached to the bottom surface of the semiconductor chip 1 via a large number of solder bumps 22.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987189105U JPH0192143U (en) | 1987-12-10 | 1987-12-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987189105U JPH0192143U (en) | 1987-12-10 | 1987-12-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0192143U true JPH0192143U (en) | 1989-06-16 |
Family
ID=31480160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987189105U Pending JPH0192143U (en) | 1987-12-10 | 1987-12-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0192143U (en) |
-
1987
- 1987-12-10 JP JP1987189105U patent/JPH0192143U/ja active Pending
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