JPH01125544U - - Google Patents
Info
- Publication number
- JPH01125544U JPH01125544U JP1988020950U JP2095088U JPH01125544U JP H01125544 U JPH01125544 U JP H01125544U JP 1988020950 U JP1988020950 U JP 1988020950U JP 2095088 U JP2095088 U JP 2095088U JP H01125544 U JPH01125544 U JP H01125544U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- circuit board
- lead frame
- wiring pattern
- surface wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の実施例における半導体装置の
実装構造を示す断面図、第２図ａ，ｂは本考案の
実施例における回路基板の表裏両面を示す平面図
、第３図ａ〜ｄは本考案の実施例における実装構
造を得るための製造工程を示す断面図、第４図は
従来例における半導体装置の実装構造を示した断
面図である。
１……半導体装置、２……表面配線パターン、
３……回路基板、４……リードフレーム、５……
接合層、６……貫通孔、７……ハンダバンプ、８
……封止材、９……ボンデイングワイヤー、１０
……ベース。
FIG. 1 is a cross-sectional view showing the mounting structure of a semiconductor device in an embodiment of the present invention, FIGS. 2 a and b are plan views showing both the front and back surfaces of a circuit board in an embodiment of the present invention, and FIGS. FIG. 4 is a sectional view showing a manufacturing process for obtaining a mounting structure in an embodiment of the present invention, and FIG. 4 is a sectional view showing a mounting structure for a semiconductor device in a conventional example. 1...Semiconductor device, 2...Surface wiring pattern,
3... Circuit board, 4... Lead frame, 5...
Bonding layer, 6... Through hole, 7... Solder bump, 8
... Sealing material, 9 ... Bonding wire, 10
……base.
Claims (1)
イングして樹脂封止する半導体装置の実装構造に
おいて、前記回路基板は一方の側に前記半導体装
置の電極に対応して内側に向つて設ける表面配線
パターンと、前記回路基板のほぼ中央部に設ける
貫通孔と、前記貫通孔を介して前記表面配線パタ
ーンと接続する前記回路基板の他方の側に設ける
リードフレームと、前記表面配線パターンと前記
リードフレームとの表面に設ける導電材からなる
接合層とを有することを特徴とする半導体装置の
実装構造。 In a semiconductor device mounting structure in which a semiconductor device is face-down bonded to a circuit board and sealed with resin, the circuit board has a surface wiring pattern provided on one side facing inward corresponding to the electrodes of the semiconductor device; a through hole provided approximately in the center of the circuit board; a lead frame provided on the other side of the circuit board connected to the surface wiring pattern through the through hole; and a lead frame provided on the surface of the surface wiring pattern and the lead frame. A mounting structure for a semiconductor device, comprising a bonding layer made of a conductive material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988020950U JPH01125544U (en) | 1988-02-19 | 1988-02-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988020950U JPH01125544U (en) | 1988-02-19 | 1988-02-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01125544U true JPH01125544U (en) | 1989-08-28 |
Family
ID=31237752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988020950U Pending JPH01125544U (en) | 1988-02-19 | 1988-02-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01125544U (en) |
-
1988
- 1988-02-19 JP JP1988020950U patent/JPH01125544U/ja active Pending