JPH0284368U - - Google Patents

Info

Publication number
JPH0284368U
JPH0284368U JP16358788U JP16358788U JPH0284368U JP H0284368 U JPH0284368 U JP H0284368U JP 16358788 U JP16358788 U JP 16358788U JP 16358788 U JP16358788 U JP 16358788U JP H0284368 U JPH0284368 U JP H0284368U
Authority
JP
Japan
Prior art keywords
hybrid
solder bumps
surfaces face
whose surfaces
boards
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16358788U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16358788U priority Critical patent/JPH0284368U/ja
Publication of JPH0284368U publication Critical patent/JPH0284368U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Combinations Of Printed Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案によるハイブリツドＩＣの構造
の一実施例を示す断面図、第２図はその製造工程
の概略を示す側面図、第３図は本考案の他の実施
例を示す断面図、第４図はその一部であるパツド
部を示す断面図、第５図は本考案の他の実施例を
示す断面図である。 FIG. 1 is a sectional view showing one embodiment of the structure of a hybrid IC according to the present invention, FIG. 2 is a side view showing an outline of the manufacturing process, and FIG. 3 is a sectional view showing another embodiment of the present invention. FIG. 4 is a sectional view showing a part of the pad portion, and FIG. 5 is a sectional view showing another embodiment of the present invention.

Claims (1)

【実用新案登録請求の範囲】 １ 板面が対面する２枚の基板間を、半田バンプ
により結合したことを特徴とするハイブリツドＩ
Ｃの構造。 ２ 板面が対面する２枚の基板間を、半田バンプ
およびパツドとの積層構造により結合したことを
特徴とするハイブリツドＩＣの構造。 ３ 板面が対面する２枚の基板間に、基板に取付
けるリード端子の根本部を挟んで両基板間隔を設
定すると共に、両基板間を半田バンプにより結合
したことを特徴とするハイブリツドＩＣの構造。[Claims for Utility Model Registration] 1. Hybrid I characterized in that two substrates whose surfaces face each other are bonded by solder bumps.
Structure of C. 2. A structure of a hybrid IC characterized in that two substrates whose surfaces face each other are connected by a laminated structure of solder bumps and pads. 3. Structure of a hybrid IC characterized in that the spacing between two boards facing each other is set by sandwiching the base of a lead terminal to be attached to the board, and the two boards are connected by solder bumps. .
JP16358788U 1988-12-17 1988-12-17 Pending JPH0284368U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16358788U JPH0284368U (en) 1988-12-17 1988-12-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16358788U JPH0284368U (en) 1988-12-17 1988-12-17

Publications (1)

Publication Number Publication Date
JPH0284368U true JPH0284368U (en) 1990-06-29

Family

ID=31448440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16358788U Pending JPH0284368U (en) 1988-12-17 1988-12-17

Country Status (1)

Country Link
JP (1) JPH0284368U (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04102384A (en) * 1990-08-21 1992-04-03 Rohm Co Ltd Electronic circuit device
JP2000315866A (en) * 1999-04-30 2000-11-14 Ibiden Co Ltd Multilayer wiring board and manufacture thereof
JP2007184362A (en) * 2006-01-05 2007-07-19 Hitachi Cable Ltd Stacked semiconductor device and its manufacturing method
JP2008204998A (en) * 2007-02-16 2008-09-04 Toppan Printing Co Ltd Highly integrated semiconductor device
JP2010080749A (en) * 2008-09-26 2010-04-08 Kyocera Corp Circuit board structure and electronic device
JP2010103568A (en) * 2010-02-05 2010-05-06 Hitachi Cable Ltd Stacked semiconductor device and its manufacturing method
WO2015083249A1 (en) * 2013-12-04 2015-06-11 株式会社日立製作所 Multilayer wiring board and method for manufacturing same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04102384A (en) * 1990-08-21 1992-04-03 Rohm Co Ltd Electronic circuit device
JP2000315866A (en) * 1999-04-30 2000-11-14 Ibiden Co Ltd Multilayer wiring board and manufacture thereof
JP2007184362A (en) * 2006-01-05 2007-07-19 Hitachi Cable Ltd Stacked semiconductor device and its manufacturing method
JP4650269B2 (en) * 2006-01-05 2011-03-16 日立電線株式会社 Manufacturing method of stacked semiconductor device
JP2008204998A (en) * 2007-02-16 2008-09-04 Toppan Printing Co Ltd Highly integrated semiconductor device
JP2010080749A (en) * 2008-09-26 2010-04-08 Kyocera Corp Circuit board structure and electronic device
JP2010103568A (en) * 2010-02-05 2010-05-06 Hitachi Cable Ltd Stacked semiconductor device and its manufacturing method
WO2015083249A1 (en) * 2013-12-04 2015-06-11 株式会社日立製作所 Multilayer wiring board and method for manufacturing same

Similar Documents

Publication Publication Date Title
JPH0284368U (en)
JPS61234538A (en) Ic mounting structure
JPS6247171U (en)
JPS63110051U (en)
JPS62134254U (en)
JPH0241476U (en)
JPS6413144U (en)
JPH0286174U (en)
JPS62190376U (en)
JPS6418752U (en)
JPH0254234U (en)
JPH0229541U (en)
JPS6035569U (en) Chip carrier bump connection structure
JPS59107139U (en) IC chip mounting structure on circuit board
JPH0189752U (en)
JPH01179446U (en)
JPS6228474U (en)
JPS6234431U (en)
JPH0426520U (en)
JPS6192064U (en)
JPS6130248U (en) multilayer ceramic substrate
JPS6263936U (en)
JPS63162533U (en)
JPH0341934U (en)
JPH0363967U (en)