JPS6192064U - - Google Patents
Info
- Publication number
- JPS6192064U JPS6192064U JP17680284U JP17680284U JPS6192064U JP S6192064 U JPS6192064 U JP S6192064U JP 17680284 U JP17680284 U JP 17680284U JP 17680284 U JP17680284 U JP 17680284U JP S6192064 U JPS6192064 U JP S6192064U
- Authority
- JP
- Japan
- Prior art keywords
- package
- integrated circuit
- semiconductor integrated
- circuit device
- fired
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図ａ，ｂはそれぞれ本考案の半導体集積回
路装置のパツケージの一実施例を示す平面図、側
面図、第２図ａ，ｂおよび第３図ａ，ｂはそれぞ
れ第１図におけるセラミツクパツケージの第１お
よび第２の使用例を示す平面図、側面図および第
４図ａ，ｂはそれぞれ従来の半導体集積回路装置
のパツケージの一例を示す平面図、側面図である
。
１，１１…セラミツクケース、２…シールリン
グ、３…ボンデイングパツド、４…端子ピン、５
，６…導電性パツド、７…プリント回路印刷基板
、８…半導体集積回路装置、９…リード端子。
1A and 1B are a plan view and a side view showing an embodiment of the package of the semiconductor integrated circuit device of the present invention, respectively. FIGS. 2A and 2B and 3A and 3B are respectively the ceramic package shown in FIG. FIGS. 4a and 4b are a plan view and a side view, respectively, showing an example of a package of a conventional semiconductor integrated circuit device. 1, 11... Ceramic case, 2... Seal ring, 3... Bonding pad, 4... Terminal pin, 5
, 6... Conductive pad, 7... Printed circuit board, 8... Semiconductor integrated circuit device, 9... Lead terminal.
Claims (1)
ラミツク基板を積層焼成した半導体集積回路装置
のパツケージにおいて、前記パツケージの縁辺の
側面および上面に導電性のパツドを形成すること
を特徴とする半導体集積回路装置のパツケージ。 A package of a semiconductor integrated circuit device in which ceramic substrates on which a conductive layer with a predetermined wiring pattern is formed are laminated and fired, characterized in that conductive pads are formed on the side and top surfaces of the edges of the package. Equipment package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17680284U JPS6192064U (en) | 1984-11-21 | 1984-11-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17680284U JPS6192064U (en) | 1984-11-21 | 1984-11-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6192064U true JPS6192064U (en) | 1986-06-14 |
Family
ID=30734386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17680284U Pending JPS6192064U (en) | 1984-11-21 | 1984-11-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6192064U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63217653A (en) * | 1987-02-25 | 1988-09-09 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Integrated circuit package |
-
1984
- 1984-11-21 JP JP17680284U patent/JPS6192064U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63217653A (en) * | 1987-02-25 | 1988-09-09 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Integrated circuit package |
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