JPS6375068U - - Google Patents
Info
- Publication number
- JPS6375068U JPS6375068U JP1986169693U JP16969386U JPS6375068U JP S6375068 U JPS6375068 U JP S6375068U JP 1986169693 U JP1986169693 U JP 1986169693U JP 16969386 U JP16969386 U JP 16969386U JP S6375068 U JPS6375068 U JP S6375068U
- Authority
- JP
- Japan
- Prior art keywords
- flat package
- leads
- circuit board
- printed circuit
- larger
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 description 1
Description
第１図は本考案の一実施例を示す部分断面図、
第２図は同フラツトパツケージ形ＩＣの部分斜視
図、第３図ａ，ｂは従来例を示す半田付け作業前
および終了後のフラツトパツケージ形ＩＣの部分
斜視図、第４図ａ，ｂは他の従来例を示すパター
ンの平面図である。
１……プリント基板、２，２ａ……パターン、
３……フラツトパツケージ形ＩＣ、４……パター
ン、７……絶縁膜。
FIG. 1 is a partial sectional view showing an embodiment of the present invention;
Figure 2 is a partial perspective view of the same flat package type IC, Figures 3a and b are partial perspective views of the flat package type IC before and after soldering work, showing a conventional example, and Figures 4a and b. FIG. 2 is a plan view of a pattern showing another conventional example. 1...Printed circuit board, 2, 2a...pattern,
3... Flat package type IC, 4... Pattern, 7... Insulating film.
Claims (1)
も一方の端に位置するリードの接続面積を他のリ
ードよりも大きくしたフラツトパツケージ形ＩＣ
と、該フラツトパツケージ形ＩＣを搭載するプリ
ント基板とからなり、該プリント基板に形成した
パターンのうち、前記フラツトパツケージ形ＩＣ
の接続面積を大きくしたリードの下側に位置し、
かつ前記リードとの接続を要しないパターンはそ
の表面を絶縁膜で覆つてなることを特徴とするフ
ラツトパツケージ形ＩＣの接続構造。 A flat package IC in which the connection area of the lead located at at least one end of a plurality of leads arranged on one side is larger than that of the other leads.
and a printed circuit board on which the flat package type IC is mounted, and among the patterns formed on the printed circuit board, the flat package type IC
Located on the underside of the lead with a larger connection area,
A connection structure for a flat package IC, characterized in that the surfaces of the patterns that do not require connection with the leads are covered with an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986169693U JPS6375068U (en) | 1986-11-05 | 1986-11-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986169693U JPS6375068U (en) | 1986-11-05 | 1986-11-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6375068U true JPS6375068U (en) | 1988-05-19 |
Family
ID=31103735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986169693U Pending JPS6375068U (en) | 1986-11-05 | 1986-11-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6375068U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06260582A (en) * | 1993-03-09 | 1994-09-16 | Hitachi Ltd | Semiconductor device |
-
1986
- 1986-11-05 JP JP1986169693U patent/JPS6375068U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06260582A (en) * | 1993-03-09 | 1994-09-16 | Hitachi Ltd | Semiconductor device |